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You searched for subject:(Cache efficient). Showing records 1 – 10 of 10 total matches.

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University of Florida

1. Zhao, Chunchun. Cache Efficient Algorithms for Bioinformatics.

Degree: PhD, Computer Engineering - Computer and Information Science and Engineering, 2017, University of Florida

Subjects/Keywords: bioinformatics; cache-efficient

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, C. (2017). Cache Efficient Algorithms for Bioinformatics. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051398

Chicago Manual of Style (16th Edition):

Zhao, Chunchun. “Cache Efficient Algorithms for Bioinformatics.” 2017. Doctoral Dissertation, University of Florida. Accessed October 18, 2019. http://ufdc.ufl.edu/UFE0051398.

MLA Handbook (7th Edition):

Zhao, Chunchun. “Cache Efficient Algorithms for Bioinformatics.” 2017. Web. 18 Oct 2019.

Vancouver:

Zhao C. Cache Efficient Algorithms for Bioinformatics. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2019 Oct 18]. Available from: http://ufdc.ufl.edu/UFE0051398.

Council of Science Editors:

Zhao C. Cache Efficient Algorithms for Bioinformatics. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051398


Rice University

2. Xu, Xiaoran. Efficient Characterization of Processor Memory Hierarchies.

Degree: MS, Computer Science, 2017, Rice University

 A processor’s memory hierarchy has a major impact on the performance of running code. As memory hierarchies have become deeper and more complex, it has… (more)

Subjects/Keywords: Efficient Characterization; Automatic Analysis; Memory Hierarchies; Cache and TLB Test

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APA (6th Edition):

Xu, X. (2017). Efficient Characterization of Processor Memory Hierarchies. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/95522

Chicago Manual of Style (16th Edition):

Xu, Xiaoran. “Efficient Characterization of Processor Memory Hierarchies.” 2017. Masters Thesis, Rice University. Accessed October 18, 2019. http://hdl.handle.net/1911/95522.

MLA Handbook (7th Edition):

Xu, Xiaoran. “Efficient Characterization of Processor Memory Hierarchies.” 2017. Web. 18 Oct 2019.

Vancouver:

Xu X. Efficient Characterization of Processor Memory Hierarchies. [Internet] [Masters thesis]. Rice University; 2017. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1911/95522.

Council of Science Editors:

Xu X. Efficient Characterization of Processor Memory Hierarchies. [Masters Thesis]. Rice University; 2017. Available from: http://hdl.handle.net/1911/95522


Universidade do Rio Grande do Sul

3. Alves, Marco Antonio Zanata. Increasing energy efficiency of processor caches via line usage predictors.

Degree: 2014, Universidade do Rio Grande do Sul

 Energy consumption is becoming more important for processor architectures, where the number of cores inside the chip is increasing and the total power budget is… (more)

Subjects/Keywords: Line usage predictors; Processadores; Sub-block psage predictors; Memoria cache; Multiprocessadores; Replacement policy; Early write-back; Cache memories; Energy efficient

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alves, M. A. Z. (2014). Increasing energy efficiency of processor caches via line usage predictors. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/96062

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alves, Marco Antonio Zanata. “Increasing energy efficiency of processor caches via line usage predictors.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed October 18, 2019. http://hdl.handle.net/10183/96062.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alves, Marco Antonio Zanata. “Increasing energy efficiency of processor caches via line usage predictors.” 2014. Web. 18 Oct 2019.

Vancouver:

Alves MAZ. Increasing energy efficiency of processor caches via line usage predictors. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10183/96062.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves MAZ. Increasing energy efficiency of processor caches via line usage predictors. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/96062

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Surprise, Jason Mathew. An energy efficient TCAM enhanced cache architecture.

Degree: 2005, Texas A&M University

 Microprocessors are used in a variety of systems ranging from high-performance super computers running scientific applications to battery powered cell phones performing realtime tasks. Due… (more)

Subjects/Keywords: TCAM; compression; cache; low-power; area efficient; energy efficient

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APA (6th Edition):

Surprise, J. M. (2005). An energy efficient TCAM enhanced cache architecture. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/2314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Surprise, Jason Mathew. “An energy efficient TCAM enhanced cache architecture.” 2005. Thesis, Texas A&M University. Accessed October 18, 2019. http://hdl.handle.net/1969.1/2314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Surprise, Jason Mathew. “An energy efficient TCAM enhanced cache architecture.” 2005. Web. 18 Oct 2019.

Vancouver:

Surprise JM. An energy efficient TCAM enhanced cache architecture. [Internet] [Thesis]. Texas A&M University; 2005. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1969.1/2314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Surprise JM. An energy efficient TCAM enhanced cache architecture. [Thesis]. Texas A&M University; 2005. Available from: http://hdl.handle.net/1969.1/2314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kentucky

5. Kristipati, Pavan K. PERFORMANCE OPTIMIZATION OF A STRUCTURED CFD CODE - GHOST ON COMMODITY CLUSTER ARCHITECTURES.

Degree: 2008, University of Kentucky

 This thesis focuses on optimizing the performance of an in-house, structured, 2D CFD code – GHOST, on commodity cluster architectures. The basic philosophy of the… (more)

Subjects/Keywords: Cache Optimization|Structured CFD Code Optimization|Efficient Coding Techniques|Improving Performance Without Changing Algorithm|Commodity Cluster Architectures; Mechanical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kristipati, P. K. (2008). PERFORMANCE OPTIMIZATION OF A STRUCTURED CFD CODE - GHOST ON COMMODITY CLUSTER ARCHITECTURES. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/567

Chicago Manual of Style (16th Edition):

Kristipati, Pavan K. “PERFORMANCE OPTIMIZATION OF A STRUCTURED CFD CODE - GHOST ON COMMODITY CLUSTER ARCHITECTURES.” 2008. Masters Thesis, University of Kentucky. Accessed October 18, 2019. http://uknowledge.uky.edu/gradschool_theses/567.

MLA Handbook (7th Edition):

Kristipati, Pavan K. “PERFORMANCE OPTIMIZATION OF A STRUCTURED CFD CODE - GHOST ON COMMODITY CLUSTER ARCHITECTURES.” 2008. Web. 18 Oct 2019.

Vancouver:

Kristipati PK. PERFORMANCE OPTIMIZATION OF A STRUCTURED CFD CODE - GHOST ON COMMODITY CLUSTER ARCHITECTURES. [Internet] [Masters thesis]. University of Kentucky; 2008. [cited 2019 Oct 18]. Available from: http://uknowledge.uky.edu/gradschool_theses/567.

Council of Science Editors:

Kristipati PK. PERFORMANCE OPTIMIZATION OF A STRUCTURED CFD CODE - GHOST ON COMMODITY CLUSTER ARCHITECTURES. [Masters Thesis]. University of Kentucky; 2008. Available from: http://uknowledge.uky.edu/gradschool_theses/567


University of Cambridge

6. Joannou, Alexandre Jean-Michel Procopi. High-performance memory safety - Optimizing the CHERI capability machine .

Degree: 2018, University of Cambridge

 This work presents optimizations for modern capability machines and specifically for the CHERI architecture, a 64-bit MIPS instruction set extension for security, supporting fine-grained memory… (more)

Subjects/Keywords: memory safety; capabilities; hardware capability; capability compression; tagged memory; tag cache; efficient tagged memory; CHERI; Bluespec

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Joannou, A. J. P. (2018). High-performance memory safety - Optimizing the CHERI capability machine . (Thesis). University of Cambridge. Retrieved from https://www.repository.cam.ac.uk/handle/1810/274350

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Joannou, Alexandre Jean-Michel Procopi. “High-performance memory safety - Optimizing the CHERI capability machine .” 2018. Thesis, University of Cambridge. Accessed October 18, 2019. https://www.repository.cam.ac.uk/handle/1810/274350.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Joannou, Alexandre Jean-Michel Procopi. “High-performance memory safety - Optimizing the CHERI capability machine .” 2018. Web. 18 Oct 2019.

Vancouver:

Joannou AJP. High-performance memory safety - Optimizing the CHERI capability machine . [Internet] [Thesis]. University of Cambridge; 2018. [cited 2019 Oct 18]. Available from: https://www.repository.cam.ac.uk/handle/1810/274350.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Joannou AJP. High-performance memory safety - Optimizing the CHERI capability machine . [Thesis]. University of Cambridge; 2018. Available from: https://www.repository.cam.ac.uk/handle/1810/274350

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Xu, Xiaoran. Efficient Characterization of Processor Memory Hierarchies.

Degree: MS, Engineering, 2017, Rice University

 A processor’s memory hierarchy has a major impact on the performance of running code. As memory hierarchies have become deeper and more complex, it has… (more)

Subjects/Keywords: Efficient Characterization; Automatic Analysis; Memory Hierarchies; Cache and TLB Test

…reasonably efficient.1 Others, such as Sandoval’s work [San11], are decidedly expensive… …memory hierarchy, both cache and TLB. As with Sandoval’s roots, our toolset computes effective… …capacity. For example, on most microprocessors, the effective L1 data cache capacity is identical… …parameters has been measured incorrectly. (See Chapter 2) 3 because the L1 data cache… …is not shared with other cores; it is separate from the L1 instruction cache; and it is… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, X. (2017). Efficient Characterization of Processor Memory Hierarchies. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/95521

Chicago Manual of Style (16th Edition):

Xu, Xiaoran. “Efficient Characterization of Processor Memory Hierarchies.” 2017. Masters Thesis, Rice University. Accessed October 18, 2019. http://hdl.handle.net/1911/95521.

MLA Handbook (7th Edition):

Xu, Xiaoran. “Efficient Characterization of Processor Memory Hierarchies.” 2017. Web. 18 Oct 2019.

Vancouver:

Xu X. Efficient Characterization of Processor Memory Hierarchies. [Internet] [Masters thesis]. Rice University; 2017. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1911/95521.

Council of Science Editors:

Xu X. Efficient Characterization of Processor Memory Hierarchies. [Masters Thesis]. Rice University; 2017. Available from: http://hdl.handle.net/1911/95521


Penn State University

8. Hu, Jie. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY.

Degree: PhD, Computer Science and Engineering, 2004, Penn State University

Cache memories are widely employed in modern microprocessor designs to bridge the increasing speed gap between the processor and the off-chip main memory, which imposes… (more)

Subjects/Keywords: Power-Aware Systems Design; Energy-Efficient Cache Architectures; Computer Architecture; Compiler Optimization; Characterization; Algorithm; Performance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hu, J. (2004). ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/6286

Chicago Manual of Style (16th Edition):

Hu, Jie. “ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY.” 2004. Doctoral Dissertation, Penn State University. Accessed October 18, 2019. https://etda.libraries.psu.edu/catalog/6286.

MLA Handbook (7th Edition):

Hu, Jie. “ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY.” 2004. Web. 18 Oct 2019.

Vancouver:

Hu J. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY. [Internet] [Doctoral dissertation]. Penn State University; 2004. [cited 2019 Oct 18]. Available from: https://etda.libraries.psu.edu/catalog/6286.

Council of Science Editors:

Hu J. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY. [Doctoral Dissertation]. Penn State University; 2004. Available from: https://etda.libraries.psu.edu/catalog/6286

9. Ramaswamy, Subramanian. Active management of Cache resources.

Degree: PhD, Electrical and Computer Engineering, 2008, Georgia Tech

 This dissertation addresses two sets of challenges facing processor design as the industry enters the deep sub-micron region of semiconductor design. The first set of… (more)

Subjects/Keywords: Efficiency; Customized placement; Reconfigurable caches; Customized caches; Efficient caches; Cache memory; Memory management (Computer science); Energy conservation

…mapped cache can produce high effectiveness for structured accesses. An efficient cache must be… …LIST OF FIGURES Figure 1 Cache utilizations for traditional cache designs… …16 Figure 2 Cache efficiencies for traditional cache designs… …17 Figure 3 Sensitivity of efficiencies to cache size… …18 Figure 4 Sensitivity of efficiencies to cache associativity… 

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APA (6th Edition):

Ramaswamy, S. (2008). Active management of Cache resources. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/24663

Chicago Manual of Style (16th Edition):

Ramaswamy, Subramanian. “Active management of Cache resources.” 2008. Doctoral Dissertation, Georgia Tech. Accessed October 18, 2019. http://hdl.handle.net/1853/24663.

MLA Handbook (7th Edition):

Ramaswamy, Subramanian. “Active management of Cache resources.” 2008. Web. 18 Oct 2019.

Vancouver:

Ramaswamy S. Active management of Cache resources. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1853/24663.

Council of Science Editors:

Ramaswamy S. Active management of Cache resources. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/24663

10. Etcheverry, Arnaud. Simulation de la dynamique des dislocations à très grande échelle : Hybrid parallelism on large scale dislocation dynamic simulation.

Degree: Docteur es, Informatique, 2015, Bordeaux

Le travail réalisé durant cette thèse vise à offrir à un code de simulation en dynamique des dislocations les composantes essentielles pour permettre le passage… (more)

Subjects/Keywords: Dynamique des dislocations; Scalabilité; MPI; Mémoire distribuée; OpenMP; Mémoire partagée; Parallélisme hybride; Méthode multipôle rapide; Hiérarchie mémoire; Structure de données; Problème à N-corps; Simulation; Scalability; MPI; Distributed memory; Shared memory; OpenMP task; Hybrid; Parallelism; Fast Multipol method; Memory hierarchie; Cache efficient; Data structure; N-body problem; 3D; Dislocation dynamics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Etcheverry, A. (2015). Simulation de la dynamique des dislocations à très grande échelle : Hybrid parallelism on large scale dislocation dynamic simulation. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2015BORD0263

Chicago Manual of Style (16th Edition):

Etcheverry, Arnaud. “Simulation de la dynamique des dislocations à très grande échelle : Hybrid parallelism on large scale dislocation dynamic simulation.” 2015. Doctoral Dissertation, Bordeaux. Accessed October 18, 2019. http://www.theses.fr/2015BORD0263.

MLA Handbook (7th Edition):

Etcheverry, Arnaud. “Simulation de la dynamique des dislocations à très grande échelle : Hybrid parallelism on large scale dislocation dynamic simulation.” 2015. Web. 18 Oct 2019.

Vancouver:

Etcheverry A. Simulation de la dynamique des dislocations à très grande échelle : Hybrid parallelism on large scale dislocation dynamic simulation. [Internet] [Doctoral dissertation]. Bordeaux; 2015. [cited 2019 Oct 18]. Available from: http://www.theses.fr/2015BORD0263.

Council of Science Editors:

Etcheverry A. Simulation de la dynamique des dislocations à très grande échelle : Hybrid parallelism on large scale dislocation dynamic simulation. [Doctoral Dissertation]. Bordeaux; 2015. Available from: http://www.theses.fr/2015BORD0263

.