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You searched for subject:(Cache ). Showing records 1 – 30 of 804 total matches.

[1] [2] [3] [4] [5] … [27]

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University of Cincinnati

1. QI, BIN. PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

 In modern microprocessors, more memory hierarchy and larger caches are integrated on chip to bridge the performance gap between high-speed CPU core and low speed… (more)

Subjects/Keywords: cache; low power; L2 cache

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APA (6th Edition):

QI, B. (2007). PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845

Chicago Manual of Style (16th Edition):

QI, BIN. “PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM.” 2007. Masters Thesis, University of Cincinnati. Accessed April 09, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845.

MLA Handbook (7th Edition):

QI, BIN. “PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM.” 2007. Web. 09 Apr 2020.

Vancouver:

QI B. PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2020 Apr 09]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845.

Council of Science Editors:

QI B. PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845


Texas A&M University

2. Jindal, Sangam. Exploring Alternate Cache Indexing Techniques.

Degree: MS, Computer Engineering, 2018, Texas A&M University

Cache memory is a bridging component which covers the increasing gap between the speed of a processor and main memory. An excellent performance of the… (more)

Subjects/Keywords: Cache; CPU

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APA (6th Edition):

Jindal, S. (2018). Exploring Alternate Cache Indexing Techniques. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173812

Chicago Manual of Style (16th Edition):

Jindal, Sangam. “Exploring Alternate Cache Indexing Techniques.” 2018. Masters Thesis, Texas A&M University. Accessed April 09, 2020. http://hdl.handle.net/1969.1/173812.

MLA Handbook (7th Edition):

Jindal, Sangam. “Exploring Alternate Cache Indexing Techniques.” 2018. Web. 09 Apr 2020.

Vancouver:

Jindal S. Exploring Alternate Cache Indexing Techniques. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1969.1/173812.

Council of Science Editors:

Jindal S. Exploring Alternate Cache Indexing Techniques. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173812


Universitat Politècnica de València

3. Valls Mompó, Joan Josep. Improving Energy and Area Scalability of the Cache Hierarchy in CMPs .

Degree: 2017, Universitat Politècnica de València

 As the core counts increase in each chip multiprocessor generation, CMPs should improve scalability in performance, area, and energy consumption to meet the demands of… (more)

Subjects/Keywords: Cache architecture; scalability; CMPs; Direcotry cache

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APA (6th Edition):

Valls Mompó, J. J. (2017). Improving Energy and Area Scalability of the Cache Hierarchy in CMPs . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/79551

Chicago Manual of Style (16th Edition):

Valls Mompó, Joan Josep. “Improving Energy and Area Scalability of the Cache Hierarchy in CMPs .” 2017. Doctoral Dissertation, Universitat Politècnica de València. Accessed April 09, 2020. http://hdl.handle.net/10251/79551.

MLA Handbook (7th Edition):

Valls Mompó, Joan Josep. “Improving Energy and Area Scalability of the Cache Hierarchy in CMPs .” 2017. Web. 09 Apr 2020.

Vancouver:

Valls Mompó JJ. Improving Energy and Area Scalability of the Cache Hierarchy in CMPs . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2017. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10251/79551.

Council of Science Editors:

Valls Mompó JJ. Improving Energy and Area Scalability of the Cache Hierarchy in CMPs . [Doctoral Dissertation]. Universitat Politècnica de València; 2017. Available from: http://hdl.handle.net/10251/79551


Texas A&M University

4. Ruia, Atin. Flowcache: A Cache Based Approach for Improving SDN Scalability.

Degree: 2015, Texas A&M University

 Software Defined Networking (SDN) is a novel paradigm for designing, developing and managing communication networks. SDN separates the traditional network control and data planes, centralising… (more)

Subjects/Keywords: SDN; scalability; cache

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APA (6th Edition):

Ruia, A. (2015). Flowcache: A Cache Based Approach for Improving SDN Scalability. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ruia, Atin. “Flowcache: A Cache Based Approach for Improving SDN Scalability.” 2015. Thesis, Texas A&M University. Accessed April 09, 2020. http://hdl.handle.net/1969.1/161260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ruia, Atin. “Flowcache: A Cache Based Approach for Improving SDN Scalability.” 2015. Web. 09 Apr 2020.

Vancouver:

Ruia A. Flowcache: A Cache Based Approach for Improving SDN Scalability. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1969.1/161260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ruia A. Flowcache: A Cache Based Approach for Improving SDN Scalability. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/161260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Lai, Chun-Hung. A Versatile Cache Architecture for Better Utilization of the Cache Space.

Degree: PhD, Computer Science and Engineering, 2014, NSYSU

 Larger on-chip cache design is a clear design trend for general purpose systems to accommodate different characteristics in ever diversifying developments and applications of modern… (more)

Subjects/Keywords: Trace Compression; Trace Storage; Multi-Role Cache; Cache Tag Arrays; Reconfigurable Cache; SPM; Cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, C. (2014). A Versatile Cache Architecture for Better Utilization of the Cache Space. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-184928

Chicago Manual of Style (16th Edition):

Lai, Chun-Hung. “A Versatile Cache Architecture for Better Utilization of the Cache Space.” 2014. Doctoral Dissertation, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-184928.

MLA Handbook (7th Edition):

Lai, Chun-Hung. “A Versatile Cache Architecture for Better Utilization of the Cache Space.” 2014. Web. 09 Apr 2020.

Vancouver:

Lai C. A Versatile Cache Architecture for Better Utilization of the Cache Space. [Internet] [Doctoral dissertation]. NSYSU; 2014. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-184928.

Council of Science Editors:

Lai C. A Versatile Cache Architecture for Better Utilization of the Cache Space. [Doctoral Dissertation]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-184928


NSYSU

6. Yang, Yun-Chung. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In almost every typical SoCs (System-on-Chip) in modern days, the size of cache grows larger as new SoC fabrics enhanced to satisfy the variety of… (more)

Subjects/Keywords: Memory architecture; Cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, Y. (2014). A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Yun-Chung. “A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.” 2014. Thesis, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Yun-Chung. “A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.” 2014. Web. 09 Apr 2020.

Vancouver:

Yang Y. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang Y. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

7. Nwachukwu, Izuchukwu Udochi. Techniques for Improving Uniformity in Direct Mapped Caches.

Degree: 2011, University of North Texas

 Directly mapped caches are an attractive option for processor designers as they combine fast lookup times with reduced complexity and area. However, directly-mapped caches are… (more)

Subjects/Keywords: cache; memory; indexing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nwachukwu, I. U. (2011). Techniques for Improving Uniformity in Direct Mapped Caches. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc68025/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nwachukwu, Izuchukwu Udochi. “Techniques for Improving Uniformity in Direct Mapped Caches.” 2011. Thesis, University of North Texas. Accessed April 09, 2020. https://digital.library.unt.edu/ark:/67531/metadc68025/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nwachukwu, Izuchukwu Udochi. “Techniques for Improving Uniformity in Direct Mapped Caches.” 2011. Web. 09 Apr 2020.

Vancouver:

Nwachukwu IU. Techniques for Improving Uniformity in Direct Mapped Caches. [Internet] [Thesis]. University of North Texas; 2011. [cited 2020 Apr 09]. Available from: https://digital.library.unt.edu/ark:/67531/metadc68025/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nwachukwu IU. Techniques for Improving Uniformity in Direct Mapped Caches. [Thesis]. University of North Texas; 2011. Available from: https://digital.library.unt.edu/ark:/67531/metadc68025/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

8. Gregory, Brittney. Geologic and Lithic Analysis of the Red River Cache.

Degree: 2011, University of North Texas

 The Red River Cache is an assemblage of 33 bifaces, found in Cooke County, along Cache Creek, a tributary to the Red River. Also found… (more)

Subjects/Keywords: Archeology; cache; geoarcheology

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APA (6th Edition):

Gregory, B. (2011). Geologic and Lithic Analysis of the Red River Cache. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc67986/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gregory, Brittney. “Geologic and Lithic Analysis of the Red River Cache.” 2011. Thesis, University of North Texas. Accessed April 09, 2020. https://digital.library.unt.edu/ark:/67531/metadc67986/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gregory, Brittney. “Geologic and Lithic Analysis of the Red River Cache.” 2011. Web. 09 Apr 2020.

Vancouver:

Gregory B. Geologic and Lithic Analysis of the Red River Cache. [Internet] [Thesis]. University of North Texas; 2011. [cited 2020 Apr 09]. Available from: https://digital.library.unt.edu/ark:/67531/metadc67986/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gregory B. Geologic and Lithic Analysis of the Red River Cache. [Thesis]. University of North Texas; 2011. Available from: https://digital.library.unt.edu/ark:/67531/metadc67986/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

9. Zheng, Tianhao, Ph. D. Efficient fine-grained virtual memory.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Virtual memory in modern computer systems provides a single abstraction of the memory hierarchy. By hiding fragmentation and overlays of physical memory, virtual memory frees… (more)

Subjects/Keywords: Memory; Cache; Metadata

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APA (6th Edition):

Zheng, Tianhao, P. D. (2018). Efficient fine-grained virtual memory. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68079

Chicago Manual of Style (16th Edition):

Zheng, Tianhao, Ph D. “Efficient fine-grained virtual memory.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed April 09, 2020. http://hdl.handle.net/2152/68079.

MLA Handbook (7th Edition):

Zheng, Tianhao, Ph D. “Efficient fine-grained virtual memory.” 2018. Web. 09 Apr 2020.

Vancouver:

Zheng, Tianhao PD. Efficient fine-grained virtual memory. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2152/68079.

Council of Science Editors:

Zheng, Tianhao PD. Efficient fine-grained virtual memory. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68079


Indian Institute of Science

10. Agarwal, Tanuj Kumar. Cache Coherence State Based Replacement Policies.

Degree: 2015, Indian Institute of Science

Cache replacement policies can play a pivotal role in the overall performance of a system by preserving data locality and thus limiting the o -chip… (more)

Subjects/Keywords: Cache Replacement Policy; Cache Coherence; Computer Architecture; Cache Memory; Computer Storage Devices; Cache Replacement Policies; Cache Coherence Protocol; Computer Science

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APA (6th Edition):

Agarwal, T. K. (2015). Cache Coherence State Based Replacement Policies. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agarwal, Tanuj Kumar. “Cache Coherence State Based Replacement Policies.” 2015. Thesis, Indian Institute of Science. Accessed April 09, 2020. http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agarwal, Tanuj Kumar. “Cache Coherence State Based Replacement Policies.” 2015. Web. 09 Apr 2020.

Vancouver:

Agarwal TK. Cache Coherence State Based Replacement Policies. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2020 Apr 09]. Available from: http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agarwal TK. Cache Coherence State Based Replacement Policies. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Adelaide

11. Mahrom, Norfadila. Dynamic cache partitioning and adaptive cache replacement schemes for chip multiprocessors.

Degree: 2015, University of Adelaide

 One of the dominant approaches towards implementing fast and high performance computer architectures is the Chip Multi Processor (CMP), in which the design of the… (more)

Subjects/Keywords: shared cache; last level cache; on-chip cache; cache partitioning; cache replacement policy; dynamic partitioning; multiprocessors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mahrom, N. (2015). Dynamic cache partitioning and adaptive cache replacement schemes for chip multiprocessors. (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/95309

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mahrom, Norfadila. “Dynamic cache partitioning and adaptive cache replacement schemes for chip multiprocessors.” 2015. Thesis, University of Adelaide. Accessed April 09, 2020. http://hdl.handle.net/2440/95309.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mahrom, Norfadila. “Dynamic cache partitioning and adaptive cache replacement schemes for chip multiprocessors.” 2015. Web. 09 Apr 2020.

Vancouver:

Mahrom N. Dynamic cache partitioning and adaptive cache replacement schemes for chip multiprocessors. [Internet] [Thesis]. University of Adelaide; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2440/95309.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mahrom N. Dynamic cache partitioning and adaptive cache replacement schemes for chip multiprocessors. [Thesis]. University of Adelaide; 2015. Available from: http://hdl.handle.net/2440/95309

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

12. -9080-1279. Performance and complexity tradeoffs in partially-inclusive caches.

Degree: MSin Engineering, Electrical and Computer Engineering, 2015, University of Texas – Austin

 Multi-level inclusive cache hierarchies have historically provided a convenient tradeoff between performance and design complexity. However, as the desire for more intermediate levels of caches… (more)

Subjects/Keywords: Cache coherence; Data duplication; Back invalidation; Inclusion property; Inclusive cache; Noninclusive cache; Partially inclusive cache; Mid level cache

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APA (6th Edition):

-9080-1279. (2015). Performance and complexity tradeoffs in partially-inclusive caches. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32269

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-9080-1279. “Performance and complexity tradeoffs in partially-inclusive caches.” 2015. Masters Thesis, University of Texas – Austin. Accessed April 09, 2020. http://hdl.handle.net/2152/32269.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-9080-1279. “Performance and complexity tradeoffs in partially-inclusive caches.” 2015. Web. 09 Apr 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-9080-1279. Performance and complexity tradeoffs in partially-inclusive caches. [Internet] [Masters thesis]. University of Texas – Austin; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2152/32269.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-9080-1279. Performance and complexity tradeoffs in partially-inclusive caches. [Masters Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32269

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Universidade de Brasília

13. Marcos Fagundes Caetano. Uma abordagem colaborativa de cache em redes ad hoc.

Degree: 2008, Universidade de Brasília

 O avanço das tecnologias de rede sem fio permitiu o surgimento de redes ad-hoc. A partir de um ambiente não infra-estruturado é possível o estabelecimento… (more)

Subjects/Keywords: cache colaborativo; cache cooperativo; cache; wireless; redes ad-hoc; MANET; CIENCIA DA COMPUTACAO

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APA (6th Edition):

Caetano, M. F. (2008). Uma abordagem colaborativa de cache em redes ad hoc. (Thesis). Universidade de Brasília. Retrieved from http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=4753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Caetano, Marcos Fagundes. “Uma abordagem colaborativa de cache em redes ad hoc.” 2008. Thesis, Universidade de Brasília. Accessed April 09, 2020. http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=4753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Caetano, Marcos Fagundes. “Uma abordagem colaborativa de cache em redes ad hoc.” 2008. Web. 09 Apr 2020.

Vancouver:

Caetano MF. Uma abordagem colaborativa de cache em redes ad hoc. [Internet] [Thesis]. Universidade de Brasília; 2008. [cited 2020 Apr 09]. Available from: http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=4753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Caetano MF. Uma abordagem colaborativa de cache em redes ad hoc. [Thesis]. Universidade de Brasília; 2008. Available from: http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=4753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Suuronen, Janne. CONTROLLING CACHE PARTITIONSIZES TO INCREASE APPLICATIONRELIABILITY.

Degree: Design and Engineering, 2018, Mälardalen University

  A problem with multi-core platforms is the competition of shared cache memory which is also knownas cache contention. Cache contention can negatively affect process… (more)

Subjects/Keywords: cache; cache partitioning; cache partition sizing; partition sizes; Computer Sciences; Datavetenskap (datalogi)

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APA (6th Edition):

Suuronen, J. (2018). CONTROLLING CACHE PARTITIONSIZES TO INCREASE APPLICATIONRELIABILITY. (Thesis). Mälardalen University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-39773

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Suuronen, Janne. “CONTROLLING CACHE PARTITIONSIZES TO INCREASE APPLICATIONRELIABILITY.” 2018. Thesis, Mälardalen University. Accessed April 09, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-39773.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Suuronen, Janne. “CONTROLLING CACHE PARTITIONSIZES TO INCREASE APPLICATIONRELIABILITY.” 2018. Web. 09 Apr 2020.

Vancouver:

Suuronen J. CONTROLLING CACHE PARTITIONSIZES TO INCREASE APPLICATIONRELIABILITY. [Internet] [Thesis]. Mälardalen University; 2018. [cited 2020 Apr 09]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-39773.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Suuronen J. CONTROLLING CACHE PARTITIONSIZES TO INCREASE APPLICATIONRELIABILITY. [Thesis]. Mälardalen University; 2018. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-39773

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

15. Ho, Yui Luen. Processor memory traffic characteristics for on-chip cache.

Degree: MS, xElectrical and Computer Engineering, 1992, Oregon State University

 The motivation of this research is to study different cache designs for on-chip caches that improve processor performance and at the same time minimize the… (more)

Subjects/Keywords: Cache memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, Y. L. (1992). Processor memory traffic characteristics for on-chip cache. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36922

Chicago Manual of Style (16th Edition):

Ho, Yui Luen. “Processor memory traffic characteristics for on-chip cache.” 1992. Masters Thesis, Oregon State University. Accessed April 09, 2020. http://hdl.handle.net/1957/36922.

MLA Handbook (7th Edition):

Ho, Yui Luen. “Processor memory traffic characteristics for on-chip cache.” 1992. Web. 09 Apr 2020.

Vancouver:

Ho YL. Processor memory traffic characteristics for on-chip cache. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1957/36922.

Council of Science Editors:

Ho YL. Processor memory traffic characteristics for on-chip cache. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/36922


University of Edinburgh

16. Huang, Cheng-Chieh. Optimizing cache utilization in modern cache hierarchies.

Degree: PhD, 2016, University of Edinburgh

 Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between… (more)

Subjects/Keywords: 004.5; cache; DRAM; memory hierarchy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, C. (2016). Optimizing cache utilization in modern cache hierarchies. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/19571

Chicago Manual of Style (16th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed April 09, 2020. http://hdl.handle.net/1842/19571.

MLA Handbook (7th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Web. 09 Apr 2020.

Vancouver:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1842/19571.

Council of Science Editors:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/19571


Rochester Institute of Technology

17. Shrivastava, Meenakshi. Hadoop-cc (collaborative caching) in real time HDFS.

Degree: Computer Science (GCCIS), 2012, Rochester Institute of Technology

  Data is being generated at an enormous rate, due to online activities and use of resources related to computing. To access and handle such… (more)

Subjects/Keywords: Cache manager; Collaborative caching; Hadoop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shrivastava, M. (2012). Hadoop-cc (collaborative caching) in real time HDFS. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shrivastava, Meenakshi. “Hadoop-cc (collaborative caching) in real time HDFS.” 2012. Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/5520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shrivastava, Meenakshi. “Hadoop-cc (collaborative caching) in real time HDFS.” 2012. Web. 09 Apr 2020.

Vancouver:

Shrivastava M. Hadoop-cc (collaborative caching) in real time HDFS. [Internet] [Thesis]. Rochester Institute of Technology; 2012. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/5520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shrivastava M. Hadoop-cc (collaborative caching) in real time HDFS. [Thesis]. Rochester Institute of Technology; 2012. Available from: https://scholarworks.rit.edu/theses/5520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

18. Fitzgerald, Brendan. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.

Degree: Computer Engineering, 2012, Rochester Institute of Technology

 Power consumption in computing today has lead the industry towards energy efficient computing. As transistor technology shrinks, new techniques have to be developed to keep… (more)

Subjects/Keywords: Cache; Energy; Low-power

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APA (6th Edition):

Fitzgerald, B. (2012). Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/4600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fitzgerald, Brendan. “Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.” 2012. Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/4600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fitzgerald, Brendan. “Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.” 2012. Web. 09 Apr 2020.

Vancouver:

Fitzgerald B. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. [Internet] [Thesis]. Rochester Institute of Technology; 2012. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/4600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fitzgerald B. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. [Thesis]. Rochester Institute of Technology; 2012. Available from: https://scholarworks.rit.edu/theses/4600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Yang, Chieh-Hsiang. Efficient and Hierarchical Architectures for WWW Cache Design.

Degree: Master, Electrical Engineering, 2000, NSYSU

 For the past few years, WWW (World Wide Web) traffic has been tremendously growing on the Internet. However, it ironically becomes âWorld Wide Waitâ due… (more)

Subjects/Keywords: WWW Cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, C. (2000). Efficient and Hierarchical Architectures for WWW Cache Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726100-171149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Chieh-Hsiang. “Efficient and Hierarchical Architectures for WWW Cache Design.” 2000. Thesis, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726100-171149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Chieh-Hsiang. “Efficient and Hierarchical Architectures for WWW Cache Design.” 2000. Web. 09 Apr 2020.

Vancouver:

Yang C. Efficient and Hierarchical Architectures for WWW Cache Design. [Internet] [Thesis]. NSYSU; 2000. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726100-171149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. Efficient and Hierarchical Architectures for WWW Cache Design. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726100-171149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

20. Srikantaiah, Shekhar Shashi. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors.

Degree: PhD, Computer Science and Engineering, 2011, Penn State University

 Chip multiprocessors (CMPs) are being accepted as the microprocessor architecture of choice and have received strong impetus from almost all leading chip manufactures. The dream… (more)

Subjects/Keywords: Multicore; Shared cache; predictable performance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srikantaiah, S. S. (2011). Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12062

Chicago Manual of Style (16th Edition):

Srikantaiah, Shekhar Shashi. “Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors.” 2011. Doctoral Dissertation, Penn State University. Accessed April 09, 2020. https://etda.libraries.psu.edu/catalog/12062.

MLA Handbook (7th Edition):

Srikantaiah, Shekhar Shashi. “Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors.” 2011. Web. 09 Apr 2020.

Vancouver:

Srikantaiah SS. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2020 Apr 09]. Available from: https://etda.libraries.psu.edu/catalog/12062.

Council of Science Editors:

Srikantaiah SS. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12062


Oklahoma State University

21. Mulia, Wira Damis. Dynamic Cache-Usage Profiler for the Xen Hypervisor.

Degree: School of Electrical & Computer Engineering, 2009, Oklahoma State University

 This study focuses on improving virtualization performance by utilizing existing architectural infrastructures. The system encompasses the profiler that interacts with low-level architecture resources, a data… (more)

Subjects/Keywords: cache memory; dynamic feedback; virtualization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mulia, W. D. (2009). Dynamic Cache-Usage Profiler for the Xen Hypervisor. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mulia, Wira Damis. “Dynamic Cache-Usage Profiler for the Xen Hypervisor.” 2009. Thesis, Oklahoma State University. Accessed April 09, 2020. http://hdl.handle.net/11244/10247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mulia, Wira Damis. “Dynamic Cache-Usage Profiler for the Xen Hypervisor.” 2009. Web. 09 Apr 2020.

Vancouver:

Mulia WD. Dynamic Cache-Usage Profiler for the Xen Hypervisor. [Internet] [Thesis]. Oklahoma State University; 2009. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/11244/10247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mulia WD. Dynamic Cache-Usage Profiler for the Xen Hypervisor. [Thesis]. Oklahoma State University; 2009. Available from: http://hdl.handle.net/11244/10247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Folz, Pauline. Collaboration dans une fédération de consommateurs de données liées : Collaboration in a Federation of Linked Data Consumers.

Degree: Docteur es, Informatique et applications, 2017, Nantes

Les producteurs de données ont publié des millions de faits RDF sur le Web en suivant les principes des données liées. N’importe qui peut récupérer… (more)

Subjects/Keywords: Cache collaboratif; Réseaux superposés; TPF

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Folz, P. (2017). Collaboration dans une fédération de consommateurs de données liées : Collaboration in a Federation of Linked Data Consumers. (Doctoral Dissertation). Nantes. Retrieved from http://www.theses.fr/2017NANT4052

Chicago Manual of Style (16th Edition):

Folz, Pauline. “Collaboration dans une fédération de consommateurs de données liées : Collaboration in a Federation of Linked Data Consumers.” 2017. Doctoral Dissertation, Nantes. Accessed April 09, 2020. http://www.theses.fr/2017NANT4052.

MLA Handbook (7th Edition):

Folz, Pauline. “Collaboration dans une fédération de consommateurs de données liées : Collaboration in a Federation of Linked Data Consumers.” 2017. Web. 09 Apr 2020.

Vancouver:

Folz P. Collaboration dans une fédération de consommateurs de données liées : Collaboration in a Federation of Linked Data Consumers. [Internet] [Doctoral dissertation]. Nantes; 2017. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2017NANT4052.

Council of Science Editors:

Folz P. Collaboration dans une fédération de consommateurs de données liées : Collaboration in a Federation of Linked Data Consumers. [Doctoral Dissertation]. Nantes; 2017. Available from: http://www.theses.fr/2017NANT4052


University of New South Wales

23. Schneider, Josef. Temperature, energy and performance: addressing embedded system challenges through fast cache simulation.

Degree: Computer Science & Engineering, 2015, University of New South Wales

 Temperature, energy and performance are essential design considerations during the conception of modern digital systems. The work presented in this thesis focusses on three aspects… (more)

Subjects/Keywords: FPGA; CPU Cache; Simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schneider, J. (2015). Temperature, energy and performance: addressing embedded system challenges through fast cache simulation. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/54412 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:34932/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Schneider, Josef. “Temperature, energy and performance: addressing embedded system challenges through fast cache simulation.” 2015. Doctoral Dissertation, University of New South Wales. Accessed April 09, 2020. http://handle.unsw.edu.au/1959.4/54412 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:34932/SOURCE02?view=true.

MLA Handbook (7th Edition):

Schneider, Josef. “Temperature, energy and performance: addressing embedded system challenges through fast cache simulation.” 2015. Web. 09 Apr 2020.

Vancouver:

Schneider J. Temperature, energy and performance: addressing embedded system challenges through fast cache simulation. [Internet] [Doctoral dissertation]. University of New South Wales; 2015. [cited 2020 Apr 09]. Available from: http://handle.unsw.edu.au/1959.4/54412 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:34932/SOURCE02?view=true.

Council of Science Editors:

Schneider J. Temperature, energy and performance: addressing embedded system challenges through fast cache simulation. [Doctoral Dissertation]. University of New South Wales; 2015. Available from: http://handle.unsw.edu.au/1959.4/54412 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:34932/SOURCE02?view=true


University of Adelaide

24. Ashenden, Peter J. An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden.

Degree: 1997, University of Adelaide

This thesis examines cache coherence protocols designed for use in bus connected shared memory multiprocessors. Advisors/Committee Members: Dept. of Computer Science (school).

Subjects/Keywords: Cache memory.

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APA (6th Edition):

Ashenden, P. J. (1997). An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden. (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/19025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ashenden, Peter J. “An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden.” 1997. Thesis, University of Adelaide. Accessed April 09, 2020. http://hdl.handle.net/2440/19025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ashenden, Peter J. “An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden.” 1997. Web. 09 Apr 2020.

Vancouver:

Ashenden PJ. An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden. [Internet] [Thesis]. University of Adelaide; 1997. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2440/19025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ashenden PJ. An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden. [Thesis]. University of Adelaide; 1997. Available from: http://hdl.handle.net/2440/19025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

25. Dai, Jie. Collaborative caching in content-oriented networks.

Degree: 2012, Hong Kong University of Science and Technology

 The content-oriented network is becoming a reality with enormous amount of contents such as high-definition videos and software packages being spreading across the entire network… (more)

Subjects/Keywords: Cache memory ; Electronic data processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dai, J. (2012). Collaborative caching in content-oriented networks. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7560 ; https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dai, Jie. “Collaborative caching in content-oriented networks.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed April 09, 2020. http://repository.ust.hk/ir/Record/1783.1-7560 ; https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dai, Jie. “Collaborative caching in content-oriented networks.” 2012. Web. 09 Apr 2020.

Vancouver:

Dai J. Collaborative caching in content-oriented networks. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2020 Apr 09]. Available from: http://repository.ust.hk/ir/Record/1783.1-7560 ; https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dai J. Collaborative caching in content-oriented networks. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: http://repository.ust.hk/ir/Record/1783.1-7560 ; https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

26. Srinath, Vinayak Bhargav. Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing.

Degree: MS, Electrical Engineering, 2015, University of Minnesota

 A processor's power consumption can be most efficiently reduced by lowering the supply voltage. But with reduced voltage levels comes the major concern of failure… (more)

Subjects/Keywords: Approximate; Cache; Energy reduction; SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srinath, V. B. (2015). Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/174718

Chicago Manual of Style (16th Edition):

Srinath, Vinayak Bhargav. “Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing.” 2015. Masters Thesis, University of Minnesota. Accessed April 09, 2020. http://hdl.handle.net/11299/174718.

MLA Handbook (7th Edition):

Srinath, Vinayak Bhargav. “Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing.” 2015. Web. 09 Apr 2020.

Vancouver:

Srinath VB. Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing. [Internet] [Masters thesis]. University of Minnesota; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/11299/174718.

Council of Science Editors:

Srinath VB. Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing. [Masters Thesis]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/174718


Rochester Institute of Technology

27. Kotas, Gerald. Exploration of GPU Cache Architectures Targeting Machine Learning Applications.

Degree: MS, Computer Engineering, 2019, Rochester Institute of Technology

  The computation power from graphics processing units (GPUs) has become prevalent in many fields of computer engineering. Massively parallel workloads and large data set… (more)

Subjects/Keywords: Cache architecture; GPU; Machine learning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kotas, G. (2019). Exploration of GPU Cache Architectures Targeting Machine Learning Applications. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10159

Chicago Manual of Style (16th Edition):

Kotas, Gerald. “Exploration of GPU Cache Architectures Targeting Machine Learning Applications.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed April 09, 2020. https://scholarworks.rit.edu/theses/10159.

MLA Handbook (7th Edition):

Kotas, Gerald. “Exploration of GPU Cache Architectures Targeting Machine Learning Applications.” 2019. Web. 09 Apr 2020.

Vancouver:

Kotas G. Exploration of GPU Cache Architectures Targeting Machine Learning Applications. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Apr 09]. Available from: https://scholarworks.rit.edu/theses/10159.

Council of Science Editors:

Kotas G. Exploration of GPU Cache Architectures Targeting Machine Learning Applications. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10159


University of Arizona

28. Simons, Brad. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .

Degree: 2016, University of Arizona

 Last Level Caches (LLCs) are critical to reducing processor stalls to off-chip memory and improving processing throughput, and replacement policy plays an important role in… (more)

Subjects/Keywords: Memory; Electrical & Computer Engineering; Cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Simons, B. (2016). Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/621128

Chicago Manual of Style (16th Edition):

Simons, Brad. “Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .” 2016. Masters Thesis, University of Arizona. Accessed April 09, 2020. http://hdl.handle.net/10150/621128.

MLA Handbook (7th Edition):

Simons, Brad. “Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .” 2016. Web. 09 Apr 2020.

Vancouver:

Simons B. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . [Internet] [Masters thesis]. University of Arizona; 2016. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10150/621128.

Council of Science Editors:

Simons B. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . [Masters Thesis]. University of Arizona; 2016. Available from: http://hdl.handle.net/10150/621128


University of Southern California

29. Manoochehri, Mehrtash. Reliable cache memories.

Degree: PhD, Computer Engineering, 2015, University of Southern California

 Due to shrinking feature sizes, cache memories have become highly vulnerable to soft errors. In this thesis, reliability of caches is studied in two ways:… (more)

Subjects/Keywords: cache; reliability; parity; ECC

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APA (6th Edition):

Manoochehri, M. (2015). Reliable cache memories. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/523809/rec/5523

Chicago Manual of Style (16th Edition):

Manoochehri, Mehrtash. “Reliable cache memories.” 2015. Doctoral Dissertation, University of Southern California. Accessed April 09, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/523809/rec/5523.

MLA Handbook (7th Edition):

Manoochehri, Mehrtash. “Reliable cache memories.” 2015. Web. 09 Apr 2020.

Vancouver:

Manoochehri M. Reliable cache memories. [Internet] [Doctoral dissertation]. University of Southern California; 2015. [cited 2020 Apr 09]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/523809/rec/5523.

Council of Science Editors:

Manoochehri M. Reliable cache memories. [Doctoral Dissertation]. University of Southern California; 2015. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/523809/rec/5523


Universitat Politècnica de València

30. Martí Campoy, Antonio. Utilización de memorias cache con bloqueo en sistemas de tiempo real.

Degree: 2015, Universitat Politècnica de València

 Los procesadores actuales ofrecen una relación precio prestaciones muy interesante, además de otras cualidades como la garantía de funcionamiento o la gran disponibilidad de herramientas… (more)

Subjects/Keywords: Memoria cache; Bloqueo; Tiempo real

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APA (6th Edition):

Martí Campoy, A. (2015). Utilización de memorias cache con bloqueo en sistemas de tiempo real. (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/55328

Chicago Manual of Style (16th Edition):

Martí Campoy, Antonio. “Utilización de memorias cache con bloqueo en sistemas de tiempo real. ” 2015. Doctoral Dissertation, Universitat Politècnica de València. Accessed April 09, 2020. http://hdl.handle.net/10251/55328.

MLA Handbook (7th Edition):

Martí Campoy, Antonio. “Utilización de memorias cache con bloqueo en sistemas de tiempo real. ” 2015. Web. 09 Apr 2020.

Vancouver:

Martí Campoy A. Utilización de memorias cache con bloqueo en sistemas de tiempo real. [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10251/55328.

Council of Science Editors:

Martí Campoy A. Utilización de memorias cache con bloqueo en sistemas de tiempo real. [Doctoral Dissertation]. Universitat Politècnica de València; 2015. Available from: http://hdl.handle.net/10251/55328

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