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You searched for subject:(COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUITS CMOS MICROELECTRONICS ). Showing records 1 – 30 of 25999 total matches.

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University of Limerick

1. Zaidi, Muhaned Ali Hussein. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.

Degree: 2018, University of Limerick

 The operational amplifier (op-amp) is one of the most commonly used analogue circuits for analogue and mixed-signal Integrated Circuit (IC) designs. The op-amp is widely… (more)

Subjects/Keywords: operational amplifier (op-amp); analogue circuits; complementary metal-oxide-semiconductor (CMOS)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zaidi, M. A. H. (2018). Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. (Thesis). University of Limerick. Retrieved from http://hdl.handle.net/10344/7599

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zaidi, Muhaned Ali Hussein. “Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.” 2018. Thesis, University of Limerick. Accessed December 15, 2019. http://hdl.handle.net/10344/7599.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zaidi, Muhaned Ali Hussein. “Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.” 2018. Web. 15 Dec 2019.

Vancouver:

Zaidi MAH. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. [Internet] [Thesis]. University of Limerick; 2018. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/10344/7599.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zaidi MAH. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. [Thesis]. University of Limerick; 2018. Available from: http://hdl.handle.net/10344/7599

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dublin City University

2. Liu, Jun. Compact modelling in RF CMOS technology.

Degree: School of Electronic Engineering, 2011, Dublin City University

 With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today,… (more)

Subjects/Keywords: Electronic engineering; complementary metal-oxide-semiconductor; CMOS

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APA (6th Edition):

Liu, J. (2011). Compact modelling in RF CMOS technology. (Thesis). Dublin City University. Retrieved from http://doras.dcu.ie/16590/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Jun. “Compact modelling in RF CMOS technology.” 2011. Thesis, Dublin City University. Accessed December 15, 2019. http://doras.dcu.ie/16590/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Jun. “Compact modelling in RF CMOS technology.” 2011. Web. 15 Dec 2019.

Vancouver:

Liu J. Compact modelling in RF CMOS technology. [Internet] [Thesis]. Dublin City University; 2011. [cited 2019 Dec 15]. Available from: http://doras.dcu.ie/16590/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu J. Compact modelling in RF CMOS technology. [Thesis]. Dublin City University; 2011. Available from: http://doras.dcu.ie/16590/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

3. Weiss, Jonas Rudolf Michael. Nanometer-scale CMOS circuits and packaging for electro-optical high density interconnects up to 40 Gb/s.

Degree: 2008, ETH Zürich

Subjects/Keywords: KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); NANOELEKTRONIK; COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); NANOELECTRONICS; info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Weiss, J. R. M. (2008). Nanometer-scale CMOS circuits and packaging for electro-optical high density interconnects up to 40 Gb/s. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/150363

Chicago Manual of Style (16th Edition):

Weiss, Jonas Rudolf Michael. “Nanometer-scale CMOS circuits and packaging for electro-optical high density interconnects up to 40 Gb/s.” 2008. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/150363.

MLA Handbook (7th Edition):

Weiss, Jonas Rudolf Michael. “Nanometer-scale CMOS circuits and packaging for electro-optical high density interconnects up to 40 Gb/s.” 2008. Web. 15 Dec 2019.

Vancouver:

Weiss JRM. Nanometer-scale CMOS circuits and packaging for electro-optical high density interconnects up to 40 Gb/s. [Internet] [Doctoral dissertation]. ETH Zürich; 2008. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/150363.

Council of Science Editors:

Weiss JRM. Nanometer-scale CMOS circuits and packaging for electro-optical high density interconnects up to 40 Gb/s. [Doctoral Dissertation]. ETH Zürich; 2008. Available from: http://hdl.handle.net/20.500.11850/150363


University of Illinois – Urbana-Champaign

4. Ho, Aaron Daniel. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will… (more)

Subjects/Keywords: complementary metal–oxide–semiconductor (CMOS) integrated circuits; digital control; low-power electronics; power convertors; asymmetric interleaving; digital control; heterogeneous power rails; low voltage complementary metal–oxide–semiconductor (CMOS) power management; multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system; multiphase power converters; multiple supply rails; reduced input current ripple; size 180 nm; Hardware; Mathematical model; Prototypes; Table lookup; Time-domain analysis

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APA (6th Edition):

Ho, A. D. (2015). Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Aaron Daniel. “Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/88219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Aaron Daniel. “Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.” 2015. Web. 15 Dec 2019.

Vancouver:

Ho AD. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/88219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho AD. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

5. Graham, Sean R. Distributed scalable model for CMOS FET power amplifier.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 Integrated circuits are very popular for understandable reasons. A circuit implemented within an IC is more cost effective and reliable. A vast majority of ICs… (more)

Subjects/Keywords: Radio Frequency (RF)+; Complementary metal???oxide???semiconductor (CMOS); Power Amplifier

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APA (6th Edition):

Graham, S. R. (2011). Distributed scalable model for CMOS FET power amplifier. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18454

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Graham, Sean R. “Distributed scalable model for CMOS FET power amplifier.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/18454.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Graham, Sean R. “Distributed scalable model for CMOS FET power amplifier.” 2011. Web. 15 Dec 2019.

Vancouver:

Graham SR. Distributed scalable model for CMOS FET power amplifier. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/18454.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Graham SR. Distributed scalable model for CMOS FET power amplifier. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18454

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

6. Steiner Vanha, Ralph. Rotary switch and current monitor by Hall-based microsystems.

Degree: 1999, ETH Zürich

Subjects/Keywords: COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); HALL SENSORS (APPLIED MAGNETISM); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); HALLSENSOREN (TECHNISCHER MAGNETISMUS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Steiner Vanha, R. (1999). Rotary switch and current monitor by Hall-based microsystems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144145

Chicago Manual of Style (16th Edition):

Steiner Vanha, Ralph. “Rotary switch and current monitor by Hall-based microsystems.” 1999. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/144145.

MLA Handbook (7th Edition):

Steiner Vanha, Ralph. “Rotary switch and current monitor by Hall-based microsystems.” 1999. Web. 15 Dec 2019.

Vancouver:

Steiner Vanha R. Rotary switch and current monitor by Hall-based microsystems. [Internet] [Doctoral dissertation]. ETH Zürich; 1999. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/144145.

Council of Science Editors:

Steiner Vanha R. Rotary switch and current monitor by Hall-based microsystems. [Doctoral Dissertation]. ETH Zürich; 1999. Available from: http://hdl.handle.net/20.500.11850/144145


ETH Zürich

7. Metz, Matthias. Offset in CMOS magnetotransistors: analysis and reduction.

Degree: 1999, ETH Zürich

Subjects/Keywords: MAGNETOTRANSISTOREN (ELEKTRONIK); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MAGNETOTRANSISTORS (ELECTRONICS); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Metz, M. (1999). Offset in CMOS magnetotransistors: analysis and reduction. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144349

Chicago Manual of Style (16th Edition):

Metz, Matthias. “Offset in CMOS magnetotransistors: analysis and reduction.” 1999. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/144349.

MLA Handbook (7th Edition):

Metz, Matthias. “Offset in CMOS magnetotransistors: analysis and reduction.” 1999. Web. 15 Dec 2019.

Vancouver:

Metz M. Offset in CMOS magnetotransistors: analysis and reduction. [Internet] [Doctoral dissertation]. ETH Zürich; 1999. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/144349.

Council of Science Editors:

Metz M. Offset in CMOS magnetotransistors: analysis and reduction. [Doctoral Dissertation]. ETH Zürich; 1999. Available from: http://hdl.handle.net/20.500.11850/144349


ETH Zürich

8. Müller, Thomas. An industrial CMOS process family for integrated silicon sensors.

Degree: 1999, ETH Zürich

Subjects/Keywords: KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MIKROSENSOREN (PHYSIK); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); MICROSENSORS (PHYSICS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Müller, T. (1999). An industrial CMOS process family for integrated silicon sensors. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144488

Chicago Manual of Style (16th Edition):

Müller, Thomas. “An industrial CMOS process family for integrated silicon sensors.” 1999. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/144488.

MLA Handbook (7th Edition):

Müller, Thomas. “An industrial CMOS process family for integrated silicon sensors.” 1999. Web. 15 Dec 2019.

Vancouver:

Müller T. An industrial CMOS process family for integrated silicon sensors. [Internet] [Doctoral dissertation]. ETH Zürich; 1999. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/144488.

Council of Science Editors:

Müller T. An industrial CMOS process family for integrated silicon sensors. [Doctoral Dissertation]. ETH Zürich; 1999. Available from: http://hdl.handle.net/20.500.11850/144488


ETH Zürich

9. Rothe, Jörg. Fully integrated CMOS microelectrode array for electrochemical measurements.

Degree: 2014, ETH Zürich

Subjects/Keywords: ELECTROCHEMISTRY; ELEKTROCHEMIE; KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MIKROELEKTRODEN (ELEKTROTECHNIK); MICROELECTRODES (ELECTRICAL ENGINEERING); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); info:eu-repo/classification/ddc/610; Medical sciences, medicine

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APA (6th Edition):

Rothe, J. (2014). Fully integrated CMOS microelectrode array for electrochemical measurements. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/97077

Chicago Manual of Style (16th Edition):

Rothe, Jörg. “Fully integrated CMOS microelectrode array for electrochemical measurements.” 2014. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/97077.

MLA Handbook (7th Edition):

Rothe, Jörg. “Fully integrated CMOS microelectrode array for electrochemical measurements.” 2014. Web. 15 Dec 2019.

Vancouver:

Rothe J. Fully integrated CMOS microelectrode array for electrochemical measurements. [Internet] [Doctoral dissertation]. ETH Zürich; 2014. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/97077.

Council of Science Editors:

Rothe J. Fully integrated CMOS microelectrode array for electrochemical measurements. [Doctoral Dissertation]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/97077


Indian Institute of Science

10. Ajayan, K R. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.

Degree: 2014, Indian Institute of Science

 Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As… (more)

Subjects/Keywords: Metal Oxide Semiconductors (MOS); Digital Integrated Circuits; Complementary Metal Oxide Semiconductors (CMOS); N-type Metal-Oxide Semiconductors (NMOS); P-type Metal-Oxide Semiconductors (PMOS); Metal Oxode Semiconductor Device Modeling; Look Up Table Model (LUT); Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET); MOSFET Models; BSIM Models; Variability Aware Device Modeling; Integrated Circuit Modeling; Circuit Design; 45nm Analog CMOS Technology; Electrical Communication Engineering

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APA (6th Edition):

Ajayan, K. R. (2014). Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Thesis, Indian Institute of Science. Accessed December 15, 2019. http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Web. 15 Dec 2019.

Vancouver:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2019 Dec 15]. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Ding, Hao. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.

Degree: Docteur es, Informatique, 2011, Université Blaise-Pascale, Clermont-Ferrand II

En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus… (more)

Subjects/Keywords: Électrocardiographie (ECG); Complementary Metal Oxide Semiconductor (CMOS); Acquisition Comprimée (CS); Arythmies cardiaques; Vectocardiographie (VCG); Electrocardiography (ECG); Complementary Metal Oxide Semiconductor (CMOS); Compressed Sensing (CS); Cardiac arrhythmias; Vectorcardiography (VCG)

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APA (6th Edition):

Ding, H. (2011). Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. (Doctoral Dissertation). Université Blaise-Pascale, Clermont-Ferrand II. Retrieved from http://www.theses.fr/2011CLF22166

Chicago Manual of Style (16th Edition):

Ding, Hao. “Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.” 2011. Doctoral Dissertation, Université Blaise-Pascale, Clermont-Ferrand II. Accessed December 15, 2019. http://www.theses.fr/2011CLF22166.

MLA Handbook (7th Edition):

Ding, Hao. “Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.” 2011. Web. 15 Dec 2019.

Vancouver:

Ding H. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. [Internet] [Doctoral dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2011. [cited 2019 Dec 15]. Available from: http://www.theses.fr/2011CLF22166.

Council of Science Editors:

Ding H. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. [Doctoral Dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2011. Available from: http://www.theses.fr/2011CLF22166


University of Edinburgh

12. Walker, Richard John. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.

Degree: PhD, 2012, University of Edinburgh

 Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time… (more)

Subjects/Keywords: 621.3; 3D camera; 3D imaging; CMOS; ?S; sigma-delta; Complementary Metal Oxide semiconductor

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APA (6th Edition):

Walker, R. J. (2012). Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/6214

Chicago Manual of Style (16th Edition):

Walker, Richard John. “Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.” 2012. Doctoral Dissertation, University of Edinburgh. Accessed December 15, 2019. http://hdl.handle.net/1842/6214.

MLA Handbook (7th Edition):

Walker, Richard John. “Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.” 2012. Web. 15 Dec 2019.

Vancouver:

Walker RJ. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. [Internet] [Doctoral dissertation]. University of Edinburgh; 2012. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/1842/6214.

Council of Science Editors:

Walker RJ. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. [Doctoral Dissertation]. University of Edinburgh; 2012. Available from: http://hdl.handle.net/1842/6214

13. Morais, Paulo Sérgio Nogueira. Circuitos digitais em modo de corrente .

Degree: 2010, Universidade de Aveiro

 Este trabalho de dissertação insere-se na área da electrónica digital, e consiste no projecto, construção e caracterização de circuitos digitais em Modo de Corrente, empregando… (more)

Subjects/Keywords: Engenharia electrónica; Electrónica digital; Circuitos integrados; Semicondutores de óxidos metálicos; CMOS (Complementary metal-oxide-semiconductor)

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APA (6th Edition):

Morais, P. S. N. (2010). Circuitos digitais em modo de corrente . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/3710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morais, Paulo Sérgio Nogueira. “Circuitos digitais em modo de corrente .” 2010. Thesis, Universidade de Aveiro. Accessed December 15, 2019. http://hdl.handle.net/10773/3710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morais, Paulo Sérgio Nogueira. “Circuitos digitais em modo de corrente .” 2010. Web. 15 Dec 2019.

Vancouver:

Morais PSN. Circuitos digitais em modo de corrente . [Internet] [Thesis]. Universidade de Aveiro; 2010. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/10773/3710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morais PSN. Circuitos digitais em modo de corrente . [Thesis]. Universidade de Aveiro; 2010. Available from: http://hdl.handle.net/10773/3710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

14. Almulla, Saoud A E A. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Spectroscopic analysis is an integral part of biological and chemical sensing. However, most spectroscopic equipment is relegated to laboratories. Compact and portable alternatives to conventional… (more)

Subjects/Keywords: Linear variable filter; Spectroscopy; Colorimetry; Fluorometry; Complementary metal-oxide semiconductor (CMOS) sensor

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APA (6th Edition):

Almulla, S. A. E. A. (2017). Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almulla, Saoud A E A. “Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/98318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almulla, Saoud A E A. “Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.” 2017. Web. 15 Dec 2019.

Vancouver:

Almulla SAEA. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/98318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almulla SAEA. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dalhousie University

15. Yu, Haoran. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.

Degree: PhD, Department of Electrical & Computer Engineering, 2014, Dalhousie University

 Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move… (more)

Subjects/Keywords: CMOS; bulk-driven; Metal oxide semiconductors, Complementary; Metal oxide semiconductors, Complementary

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, H. (2014). Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. (Doctoral Dissertation). Dalhousie University. Retrieved from http://hdl.handle.net/10222/55992

Chicago Manual of Style (16th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Doctoral Dissertation, Dalhousie University. Accessed December 15, 2019. http://hdl.handle.net/10222/55992.

MLA Handbook (7th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Web. 15 Dec 2019.

Vancouver:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Internet] [Doctoral dissertation]. Dalhousie University; 2014. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/10222/55992.

Council of Science Editors:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Doctoral Dissertation]. Dalhousie University; 2014. Available from: http://hdl.handle.net/10222/55992


ETH Zürich

16. Loeliger, Teddy. Large-area photosensing in CMOS.

Degree: 2001, ETH Zürich

Subjects/Keywords: OPTISCHE SENSOREN (OPTISCHE INSTRUMENTE); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); OPTICAL SENSORS (OPTICAL INSTRUMENTS); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); info:eu-repo/classification/ddc/530; info:eu-repo/classification/ddc/621.3; Physics; Electric engineering

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APA (6th Edition):

Loeliger, T. (2001). Large-area photosensing in CMOS. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/145213

Chicago Manual of Style (16th Edition):

Loeliger, Teddy. “Large-area photosensing in CMOS.” 2001. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/145213.

MLA Handbook (7th Edition):

Loeliger, Teddy. “Large-area photosensing in CMOS.” 2001. Web. 15 Dec 2019.

Vancouver:

Loeliger T. Large-area photosensing in CMOS. [Internet] [Doctoral dissertation]. ETH Zürich; 2001. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/145213.

Council of Science Editors:

Loeliger T. Large-area photosensing in CMOS. [Doctoral Dissertation]. ETH Zürich; 2001. Available from: http://hdl.handle.net/20.500.11850/145213


ETH Zürich

17. Hafizović, Sadik. Neural interface and atomic-force microscope in CMOS technology.

Degree: 2006, ETH Zürich

Subjects/Keywords: KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MIKROSYSTEMTECHNIK, MST; RASTERKRAFTMIKROSKOPE, RKM + RASTERKRAFTMIKROSKOPIE; COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); MICRO SYSTEM TECHNOLOGIES, MST; ATOMIC FORCE MICROSCOPES, AFM + ATOMIC FORCE MICROSCOPY; info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Hafizović, S. (2006). Neural interface and atomic-force microscope in CMOS technology. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/149751

Chicago Manual of Style (16th Edition):

Hafizović, Sadik. “Neural interface and atomic-force microscope in CMOS technology.” 2006. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/149751.

MLA Handbook (7th Edition):

Hafizović, Sadik. “Neural interface and atomic-force microscope in CMOS technology.” 2006. Web. 15 Dec 2019.

Vancouver:

Hafizović S. Neural interface and atomic-force microscope in CMOS technology. [Internet] [Doctoral dissertation]. ETH Zürich; 2006. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/149751.

Council of Science Editors:

Hafizović S. Neural interface and atomic-force microscope in CMOS technology. [Doctoral Dissertation]. ETH Zürich; 2006. Available from: http://hdl.handle.net/20.500.11850/149751


ETH Zürich

18. Frey, Urs. High-density neural interface and microhotplate gas sensor in CMOS technology.

Degree: 2007, ETH Zürich

Subjects/Keywords: NERVENFORTSÄTZE + NEURITEN (CYTOLOGIE, HISTOLOGIE); GAS SENSORS (PHYSICS); GASSENSOREN (PHYSIK); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MICROSENSORS (PHYSICS); NEURONAL PROCESSES + NEURITES (CYTOLOGY, HISTOLOGY); MIKROSENSOREN (PHYSIK); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Frey, U. (2007). High-density neural interface and microhotplate gas sensor in CMOS technology. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/71331

Chicago Manual of Style (16th Edition):

Frey, Urs. “High-density neural interface and microhotplate gas sensor in CMOS technology.” 2007. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/71331.

MLA Handbook (7th Edition):

Frey, Urs. “High-density neural interface and microhotplate gas sensor in CMOS technology.” 2007. Web. 15 Dec 2019.

Vancouver:

Frey U. High-density neural interface and microhotplate gas sensor in CMOS technology. [Internet] [Doctoral dissertation]. ETH Zürich; 2007. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/71331.

Council of Science Editors:

Frey U. High-density neural interface and microhotplate gas sensor in CMOS technology. [Doctoral Dissertation]. ETH Zürich; 2007. Available from: http://hdl.handle.net/20.500.11850/71331


ETH Zürich

19. Jones, Ian L. Optical and Electrical Stimulation of Retinal Ganglion Cells on a CMOS Microelectrode Array.

Degree: 2015, ETH Zürich

Subjects/Keywords: RETINAL GANGLION CELLS (SENSORY PHYSIOLOGY); RETINALE GANGLIENZELLEN (SINNESPHYSIOLOGIE); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MIKROELEKTRODEN (ELEKTROTECHNIK); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); MICROELECTRODES (ELECTRICAL ENGINEERING); info:eu-repo/classification/ddc/610; Medical sciences, medicine

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APA (6th Edition):

Jones, I. L. (2015). Optical and Electrical Stimulation of Retinal Ganglion Cells on a CMOS Microelectrode Array. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/106530

Chicago Manual of Style (16th Edition):

Jones, Ian L. “Optical and Electrical Stimulation of Retinal Ganglion Cells on a CMOS Microelectrode Array.” 2015. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/106530.

MLA Handbook (7th Edition):

Jones, Ian L. “Optical and Electrical Stimulation of Retinal Ganglion Cells on a CMOS Microelectrode Array.” 2015. Web. 15 Dec 2019.

Vancouver:

Jones IL. Optical and Electrical Stimulation of Retinal Ganglion Cells on a CMOS Microelectrode Array. [Internet] [Doctoral dissertation]. ETH Zürich; 2015. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/106530.

Council of Science Editors:

Jones IL. Optical and Electrical Stimulation of Retinal Ganglion Cells on a CMOS Microelectrode Array. [Doctoral Dissertation]. ETH Zürich; 2015. Available from: http://hdl.handle.net/20.500.11850/106530


ETH Zürich

20. Müller, Jan. High-Density Microelectrode Array Platform in CMOS Technology.

Degree: 2015, ETH Zürich

Subjects/Keywords: RETINAL GANGLION CELLS (SENSORY PHYSIOLOGY); RETINALE GANGLIENZELLEN (SINNESPHYSIOLOGIE); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); MIKROELEKTRODEN (ELEKTROTECHNIK); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); MICROELECTRODES (ELECTRICAL ENGINEERING); info:eu-repo/classification/ddc/610; Medical sciences, medicine

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APA (6th Edition):

Müller, J. (2015). High-Density Microelectrode Array Platform in CMOS Technology. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/106679

Chicago Manual of Style (16th Edition):

Müller, Jan. “High-Density Microelectrode Array Platform in CMOS Technology.” 2015. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/106679.

MLA Handbook (7th Edition):

Müller, Jan. “High-Density Microelectrode Array Platform in CMOS Technology.” 2015. Web. 15 Dec 2019.

Vancouver:

Müller J. High-Density Microelectrode Array Platform in CMOS Technology. [Internet] [Doctoral dissertation]. ETH Zürich; 2015. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/106679.

Council of Science Editors:

Müller J. High-Density Microelectrode Array Platform in CMOS Technology. [Doctoral Dissertation]. ETH Zürich; 2015. Available from: http://hdl.handle.net/20.500.11850/106679


ETH Zürich

21. Villiger, Thomas. Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems.

Degree: 2005, ETH Zürich

Subjects/Keywords: http://dx.doi.org/10.3929/ethz-a-004948731; KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); SYSTEM ON A CHIP, SOC (MIKROELEKTRONIK); ASYNCHRONOUS INTEGRATED CIRCUITS (MICROELECTRONICS); SYSTEM ON A CHIP, SOC (MICROELECTRONICS); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); ASYNCHRONE INTEGRIERTE SCHALTUNGEN (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Villiger, T. (2005). Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/87052

Chicago Manual of Style (16th Edition):

Villiger, Thomas. “Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems.” 2005. Doctoral Dissertation, ETH Zürich. Accessed December 15, 2019. http://hdl.handle.net/20.500.11850/87052.

MLA Handbook (7th Edition):

Villiger, Thomas. “Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems.” 2005. Web. 15 Dec 2019.

Vancouver:

Villiger T. Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2005. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/20.500.11850/87052.

Council of Science Editors:

Villiger T. Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems. [Doctoral Dissertation]. ETH Zürich; 2005. Available from: http://hdl.handle.net/20.500.11850/87052


Indian Institute of Science

22. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed December 15, 2019. http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 15 Dec 2019.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Dec 15]. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

23. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed December 15, 2019. http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 15 Dec 2019.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

24. Yoon, Sangwoong. LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies.

Degree: PhD, Electrical and Computer Engineering, 2004, Georgia Tech

 This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those… (more)

Subjects/Keywords: High quality inductor; CMOS VCO; Embedded inductor; Packaging technology; Ball grid array technology; Electric inductors Mathematical models; Integrated circuits Wafer-scale integration; Metal oxide semiconductors, Complementary; Microelectronic packaging; Multichip modules (Microelectronics); Semiconductor wafers; Voltage-controlled oscillators

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APA (6th Edition):

Yoon, S. (2004). LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4887

Chicago Manual of Style (16th Edition):

Yoon, Sangwoong. “LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies.” 2004. Doctoral Dissertation, Georgia Tech. Accessed December 15, 2019. http://hdl.handle.net/1853/4887.

MLA Handbook (7th Edition):

Yoon, Sangwoong. “LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies.” 2004. Web. 15 Dec 2019.

Vancouver:

Yoon S. LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/1853/4887.

Council of Science Editors:

Yoon S. LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4887


Georgia Tech

25. Zahorian, Jaime S. Fabrication technology and design for CMUTS on CMOS for IVUS catheters.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 The objective of this research is to develop novel capacitive micromachined ultrasonic transducer (CMUT) arrays for intravascular ultrasonic (IVUS) imaging along with the fabrication processes… (more)

Subjects/Keywords: Intravascular ultrasonic (IVUS); Capacitive micromachined ultrasonic transducer (CMUT); Complementary metal oxide semiconductor (CMOS); Metal oxide semiconductors, Complementary; Ultrasonic transducer; Diagnostic ultrasonic imaging; Intravascular ultrasonography

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APA (6th Edition):

Zahorian, J. S. (2013). Fabrication technology and design for CMUTS on CMOS for IVUS catheters. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51730

Chicago Manual of Style (16th Edition):

Zahorian, Jaime S. “Fabrication technology and design for CMUTS on CMOS for IVUS catheters.” 2013. Doctoral Dissertation, Georgia Tech. Accessed December 15, 2019. http://hdl.handle.net/1853/51730.

MLA Handbook (7th Edition):

Zahorian, Jaime S. “Fabrication technology and design for CMUTS on CMOS for IVUS catheters.” 2013. Web. 15 Dec 2019.

Vancouver:

Zahorian JS. Fabrication technology and design for CMUTS on CMOS for IVUS catheters. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/1853/51730.

Council of Science Editors:

Zahorian JS. Fabrication technology and design for CMUTS on CMOS for IVUS catheters. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51730


Brunel University

26. Greig, Thomas Alexander. Development of CMOS active pixel sensors.

Degree: 2008, Brunel University

 This thesis describes an investigation into the suitability of complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) devices for scientific imaging applications. CMOS APS… (more)

Subjects/Keywords: 681.25; Complementary metal oxide semiconductor (CMOS); Charge-coupled device (CCD); Quantum efficiency (QE); Charge conversion gain (responsivity); Pixel capacitance

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APA (6th Edition):

Greig, T. A. (2008). Development of CMOS active pixel sensors. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925

Chicago Manual of Style (16th Edition):

Greig, Thomas Alexander. “Development of CMOS active pixel sensors.” 2008. Doctoral Dissertation, Brunel University. Accessed December 15, 2019. http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925.

MLA Handbook (7th Edition):

Greig, Thomas Alexander. “Development of CMOS active pixel sensors.” 2008. Web. 15 Dec 2019.

Vancouver:

Greig TA. Development of CMOS active pixel sensors. [Internet] [Doctoral dissertation]. Brunel University; 2008. [cited 2019 Dec 15]. Available from: http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925.

Council of Science Editors:

Greig TA. Development of CMOS active pixel sensors. [Doctoral Dissertation]. Brunel University; 2008. Available from: http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925


NSYSU

27. Chung, Chun-lin. Back-contact photovoltaic device realized by standard CMOS foundry process and its application.

Degree: Master, Electro-Optical Engineering, 2015, NSYSU

 In this thesis, an interdigitated back-contact photovoltaic device is realized by high-resolution doping and multi-layer interconnections provided by standard bulk CMOS processes. Since the device… (more)

Subjects/Keywords: complementary metal-oxide-semiconductor (CMOS); interdigitated back-contact solar cell; integrated passive device; implantable device; surface texture

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APA (6th Edition):

Chung, C. (2015). Back-contact photovoltaic device realized by standard CMOS foundry process and its application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Chun-lin. “Back-contact photovoltaic device realized by standard CMOS foundry process and its application.” 2015. Thesis, NSYSU. Accessed December 15, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Chun-lin. “Back-contact photovoltaic device realized by standard CMOS foundry process and its application.” 2015. Web. 15 Dec 2019.

Vancouver:

Chung C. Back-contact photovoltaic device realized by standard CMOS foundry process and its application. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Dec 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung C. Back-contact photovoltaic device realized by standard CMOS foundry process and its application. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Anek Wuthayavanich. Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ.

Degree: 博士(工学), 2017, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Complementary metal-oxide semiconductor (CMOS) image sensor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wuthayavanich, A. (2017). Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/11710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wuthayavanich, Anek. “Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ.” 2017. Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed December 15, 2019. http://hdl.handle.net/10061/11710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wuthayavanich, Anek. “Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ.” 2017. Web. 15 Dec 2019.

Vancouver:

Wuthayavanich A. Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; 2017. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/10061/11710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wuthayavanich A. Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; 2017. Available from: http://hdl.handle.net/10061/11710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

29. Chan, Doris A. CMOS Power Device Modeling and Amplifier Circuits.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 A power amplifier (PA) is a key part of the RF front-end in transmitters for a local broadband network. Today, commercial PAs are made of… (more)

Subjects/Keywords: Complementary Metal Oxide Semiconductor (CMOS); millimeter-wave; coplanar waveguide; Worldwide Interoperability for Microwave Access (WiMAX); power divider/combiner; power amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chan, D. A. (2011). CMOS Power Device Modeling and Amplifier Circuits. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18249

Chicago Manual of Style (16th Edition):

Chan, Doris A. “CMOS Power Device Modeling and Amplifier Circuits.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/18249.

MLA Handbook (7th Edition):

Chan, Doris A. “CMOS Power Device Modeling and Amplifier Circuits.” 2011. Web. 15 Dec 2019.

Vancouver:

Chan DA. CMOS Power Device Modeling and Amplifier Circuits. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/18249.

Council of Science Editors:

Chan DA. CMOS Power Device Modeling and Amplifier Circuits. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18249


University of Illinois – Urbana-Champaign

30. Carlson, John Anthony. Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 A set of semiconductor designs shown to be capable of facilitating scalable and reconfigurable layouts for electronic-photonic integrated circuitry is presented. Three emphases are established… (more)

Subjects/Keywords: Photonic integration; III-V on silicon; Gallium nitride; Complementary metal–oxide–semiconductor (CMOS) compatibility; Scalable processes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carlson, J. A. (2017). Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carlson, John Anthony. “Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/97634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carlson, John Anthony. “Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry.” 2017. Web. 15 Dec 2019.

Vancouver:

Carlson JA. Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/97634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carlson JA. Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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