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You searched for subject:(CMOS 45nm). Showing records 1 – 3 of 3 total matches.

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University of Texas – Austin

1. Naganathan, Vignesh. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.

Degree: MSin Engineering, Electrical and Computer Engineering, 2015, University of Texas – Austin

Binary adders form a major part in various arithmetic logical operation units including multipliers, dividers and digital signal processors. Parallel prefix adders represent a set of efficient structures for binary addition, greatly suited for VLSI implementation due to their regularity and speed. This report is focused on the comparative analysis of 5 major types of parallel prefix adder frameworks namely Kooge-Stone, Knowles adders, Brent-Kung, Han-Carlson and Ladner-Fischer adders implemented in Synopsys's SAED 32nm static CMOS technology operating at 1.05V for 8-bit, 16-bit and 32-bit input vectors based on power, performance and area (PPA) metrics. The process technology is modeled with 9 metal tracks. Power, performance and area metrics based on circuit simulations are used for comparison. The metrics are compared across SAED 32nm and FreePDK 45nm technology to quantify the impact of technology on architecture. Advisors/Committee Members: Swartzlander, Earl E., Jr., 1945- (advisor), JOHN, LIZY K (committee member).

Subjects/Keywords: Parallel prefix adders; CMOS 32nm; CMOS 45nm

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APA (6th Edition):

Naganathan, V. (2015). A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32303

Chicago Manual of Style (16th Edition):

Naganathan, Vignesh. “A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.” 2015. Masters Thesis, University of Texas – Austin. Accessed June 05, 2020. http://hdl.handle.net/2152/32303.

MLA Handbook (7th Edition):

Naganathan, Vignesh. “A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.” 2015. Web. 05 Jun 2020.

Vancouver:

Naganathan V. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. [Internet] [Masters thesis]. University of Texas – Austin; 2015. [cited 2020 Jun 05]. Available from: http://hdl.handle.net/2152/32303.

Council of Science Editors:

Naganathan V. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. [Masters Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32303

2. Aggrawal, Himanshu. High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization.

Degree: MS, Engineering, 2015, Rice University

Last few decades have seen a puissant desire for fast communication links that has shaped the evolution of high-speed circuits and silicon- based technology. This desire accompanied with a large consumer market has fueled the development of ever-shrinking, faster technology nodes. These advanced nodes open doors for designers to develop new ways of transferring data with unprecedented speed and accuracy. There are a number of challenges in building high-speed, secure communication links, one being the lack of availability of fast Analog to Digital Converters (ADCs), which form the front end of a receiver. Even in advanced technology nodes, the leakage in the transmission gate due to parasitic source-drain capacitance provides an alternate path for signals to pass, thus lowering the performance of the ADCs at high frequencies. Second, the current communication schemes use beam-forming or Direct Antenna Modulation (DAM) to narrow the information beam and point it in the direction of communication. Such techniques still have a wide information beam compared pulse-based directional modulation, as discussed in this thesis. In this dissertation, we address the issue of parasitic leakages in the transmission gate of a fast sampler by introducing active cancellation. A track-and-hold amplifier with active cancellation is designed and fabricated in 45nm CMOS SOI technology, which can operate at 40GSample/second real-time. In addition to this, we also study a pulse-based directional modulation scheme which can be used for secure communication, imaging and localization. Two coherent pulse generators with pulse width less than 200ps were used to attain an information beamwidth of less than 1 degree and localize objects with millimeter accuracy. Advisors/Committee Members: Babakhani, Aydin (advisor), Cavallaro, Joseph (committee member), Mittleman, Daniel (committee member).

Subjects/Keywords: Track and hold Amplifier; Sampler; CMOS; 45nm; Directional Modulation; Secure Communication; Localization; Radar; Pulse

…T/H) architecture with active cancellation, which is fabricated in IBM 45nm CMOS SOI… …3.10 Chip micrograph in 45nm. . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 34 34… …isolation of a CMOS switch degrades at high frequencies. In a series switch, the gate-source (… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aggrawal, H. (2015). High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/87740

Chicago Manual of Style (16th Edition):

Aggrawal, Himanshu. “High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization.” 2015. Masters Thesis, Rice University. Accessed June 05, 2020. http://hdl.handle.net/1911/87740.

MLA Handbook (7th Edition):

Aggrawal, Himanshu. “High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization.” 2015. Web. 05 Jun 2020.

Vancouver:

Aggrawal H. High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization. [Internet] [Masters thesis]. Rice University; 2015. [cited 2020 Jun 05]. Available from: http://hdl.handle.net/1911/87740.

Council of Science Editors:

Aggrawal H. High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization. [Masters Thesis]. Rice University; 2015. Available from: http://hdl.handle.net/1911/87740


Indian Institute of Science

3. Ajayan, K R. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.

Degree: 2014, Indian Institute of Science

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model… Advisors/Committee Members: Bhat, Navakanta.

Subjects/Keywords: Metal Oxide Semiconductors (MOS); Digital Integrated Circuits; Complementary Metal Oxide Semiconductors (CMOS); N-type Metal-Oxide Semiconductors (NMOS); P-type Metal-Oxide Semiconductors (PMOS); Metal Oxode Semiconductor Device Modeling; Look Up Table Model (LUT); Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET); MOSFET Models; BSIM Models; Variability Aware Device Modeling; Integrated Circuit Modeling; Circuit Design; 45nm Analog CMOS Technology; Electrical Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ajayan, K. R. (2014). Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Thesis, Indian Institute of Science. Accessed June 05, 2020. http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Web. 05 Jun 2020.

Vancouver:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2020 Jun 05]. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.