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University of Texas – Austin

1. Naganathan, Vignesh. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.

Degree: MSin Engineering, Electrical and Computer Engineering, 2015, University of Texas – Austin

Binary adders form a major part in various arithmetic logical operation units including multipliers, dividers and digital signal processors. Parallel prefix adders represent a set of efficient structures for binary addition, greatly suited for VLSI implementation due to their regularity and speed. This report is focused on the comparative analysis of 5 major types of parallel prefix adder frameworks namely Kooge-Stone, Knowles adders, Brent-Kung, Han-Carlson and Ladner-Fischer adders implemented in Synopsys's SAED 32nm static CMOS technology operating at 1.05V for 8-bit, 16-bit and 32-bit input vectors based on power, performance and area (PPA) metrics. The process technology is modeled with 9 metal tracks. Power, performance and area metrics based on circuit simulations are used for comparison. The metrics are compared across SAED 32nm and FreePDK 45nm technology to quantify the impact of technology on architecture. Advisors/Committee Members: Swartzlander, Earl E., Jr., 1945- (advisor), JOHN, LIZY K (committee member).

Subjects/Keywords: Parallel prefix adders; CMOS 32nm; CMOS 45nm

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Naganathan, V. (2015). A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32303

Chicago Manual of Style (16th Edition):

Naganathan, Vignesh. “A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.” 2015. Masters Thesis, University of Texas – Austin. Accessed May 30, 2020. http://hdl.handle.net/2152/32303.

MLA Handbook (7th Edition):

Naganathan, Vignesh. “A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.” 2015. Web. 30 May 2020.

Vancouver:

Naganathan V. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. [Internet] [Masters thesis]. University of Texas – Austin; 2015. [cited 2020 May 30]. Available from: http://hdl.handle.net/2152/32303.

Council of Science Editors:

Naganathan V. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. [Masters Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32303

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