subject:(CML to CMOS converter)

University of Pretoria

1. Veale, Gerhardus Ignatius Potgieter. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC.

Degree: Electrical, Electronic and Computer Engineering, 2010, University of Pretoria

► Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs.… (more)

Subjects/Keywords: Cml-to-cmos converter; Cml flicker noise; Fractional-n; Cmos pfd; Cml pfd; Cml 4-bit counter; Cml; Cml 2/3-prescaler; Ssb phase noise; Pulse-swallow counter; Low division; Programmable modulus accumulator; High voltage charge-pump; In-band phase noise; UCTD

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APA (6^th Edition):

Veale, G. I. (2010). Low phase noise 2 GHz Fractional-N CMOS synthesizer IC. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/27921

Chicago Manual of Style (16^th Edition):

Veale, Gerhardus Ignatius. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC.” 2010. Masters Thesis, University of Pretoria. Accessed April 22, 2018. http://hdl.handle.net/2263/27921.

MLA Handbook (7^th Edition):

Veale, Gerhardus Ignatius. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC.” 2010. Web. 22 Apr 2018.

Vancouver:

Veale GI. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC. [Internet] [Masters thesis]. University of Pretoria; 2010. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/2263/27921.

Council of Science Editors:

Veale GI. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC. [Masters Thesis]. University of Pretoria; 2010. Available from: http://hdl.handle.net/2263/27921

University of Pretoria

2. [No author]. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC .

Degree: 2010, University of Pretoria

URL: http://upetd.up.ac.za/thesis/available/etd-09132010-162013/

► Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs.… (more)

Subjects/Keywords: Cml-to-cmos converter; Cml flicker noise; Fractional-n; Cmos pfd; Cml pfd; Cml 4-bit counter; Cml; Cml 2/3-prescaler; Ssb phase noise; Pulse-swallow counter; Low division; Programmable modulus accumulator; High voltage charge-pump; In-band phase noise; UCTD

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APA (6^th Edition):

author], [. (2010). Low phase noise 2 GHz Fractional-N CMOS synthesizer IC . (Masters Thesis). University of Pretoria. Retrieved from http://upetd.up.ac.za/thesis/available/etd-09132010-162013/

Chicago Manual of Style (16^th Edition):

author], [No. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC .” 2010. Masters Thesis, University of Pretoria. Accessed April 22, 2018. http://upetd.up.ac.za/thesis/available/etd-09132010-162013/.

MLA Handbook (7^th Edition):

author], [No. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC .” 2010. Web. 22 Apr 2018.

Vancouver:

author] [. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC . [Internet] [Masters thesis]. University of Pretoria; 2010. [cited 2018 Apr 22]. Available from: http://upetd.up.ac.za/thesis/available/etd-09132010-162013/.

Council of Science Editors:

author] [. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC . [Masters Thesis]. University of Pretoria; 2010. Available from: http://upetd.up.ac.za/thesis/available/etd-09132010-162013/

Brno University of Technology

3. Buček, Vladimír. Návrh číslicově-analogového převodníku s vysokým rozlišením .

Degree: 2011, Brno University of Technology

URL: http://hdl.handle.net/11012/1802

► Tato práce se zabývá návrhem digitálně-analogového převodníku. Používaná technologie tohoto návrhu je ON SEMICONDUCTOR CMOS07 v návrhovém programu Cadence. V práci se lze setkat s… (more)

Subjects/Keywords: digitálně-analogový převodník; CMOS; napěťová nesymetrie; Digital to analog converter; CMOS; offset

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APA (6^th Edition):

Buček, V. (2011). Návrh číslicově-analogového převodníku s vysokým rozlišením . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/1802

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Buček, Vladimír. “Návrh číslicově-analogového převodníku s vysokým rozlišením .” 2011. Thesis, Brno University of Technology. Accessed April 22, 2018. http://hdl.handle.net/11012/1802.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Buček, Vladimír. “Návrh číslicově-analogového převodníku s vysokým rozlišením .” 2011. Web. 22 Apr 2018.

Vancouver:

Buček V. Návrh číslicově-analogového převodníku s vysokým rozlišením . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/11012/1802.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Buček V. Návrh číslicově-analogového převodníku s vysokým rozlišením . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/1802

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Edinburgh

4. Danesh, Seyed Amir Ali. Time interleaved counter analog to digital converters.

Degree: 2011, University of Edinburgh

URL: http://hdl.handle.net/1842/5790

► The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters,… (more)

Subjects/Keywords: 004.19; ADC; analog to digial converter; time interleaved; counter; TIC; CMOS

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APA (6^th Edition):

Danesh, S. A. A. (2011). Time interleaved counter analog to digital converters. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5790

Chicago Manual of Style (16^th Edition):

Danesh, Seyed Amir Ali. “Time interleaved counter analog to digital converters.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed April 22, 2018. http://hdl.handle.net/1842/5790.

MLA Handbook (7^th Edition):

Danesh, Seyed Amir Ali. “Time interleaved counter analog to digital converters.” 2011. Web. 22 Apr 2018.

Vancouver:

Danesh SAA. Time interleaved counter analog to digital converters. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/1842/5790.

Council of Science Editors:

Danesh SAA. Time interleaved counter analog to digital converters. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5790

University of Akron

5. Namburu, Pradeep. A TEMPERATURE-INSENSITIVE GATE-CONTROLLED WEIGHTED CURRENT DIGITAL-TO-ANALOG CONVERTER.

Degree: MS, Electrical Engineering, 2010, University of Akron

URL: http://rave.ohiolink.edu/etdc/view?acc_num=akron1270567830

► The current thesis presents the design of a 10-bit Digital-to-Analog Converter (DAC) to be used in a Successive Approximation Register Analog-to-Digital converter (SAR ADC).… (more)

Subjects/Keywords: Electrical Engineering; CMOS gate driver; Current source; Digital-to-Analog Converter

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APA (6^th Edition):

Namburu, P. (2010). A TEMPERATURE-INSENSITIVE GATE-CONTROLLED WEIGHTED CURRENT DIGITAL-TO-ANALOG CONVERTER. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1270567830

Chicago Manual of Style (16^th Edition):

Namburu, Pradeep. “A TEMPERATURE-INSENSITIVE GATE-CONTROLLED WEIGHTED CURRENT DIGITAL-TO-ANALOG CONVERTER.” 2010. Masters Thesis, University of Akron. Accessed April 22, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1270567830.

MLA Handbook (7^th Edition):

Namburu, Pradeep. “A TEMPERATURE-INSENSITIVE GATE-CONTROLLED WEIGHTED CURRENT DIGITAL-TO-ANALOG CONVERTER.” 2010. Web. 22 Apr 2018.

Vancouver:

Namburu P. A TEMPERATURE-INSENSITIVE GATE-CONTROLLED WEIGHTED CURRENT DIGITAL-TO-ANALOG CONVERTER. [Internet] [Masters thesis]. University of Akron; 2010. [cited 2018 Apr 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1270567830.

Council of Science Editors:

Namburu P. A TEMPERATURE-INSENSITIVE GATE-CONTROLLED WEIGHTED CURRENT DIGITAL-TO-ANALOG CONVERTER. [Masters Thesis]. University of Akron; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1270567830

University of Waterloo

6. Ali, Areeb. CMOS Impedance Measurement Array for Cell Sensing.

Degree: 2015, University of Waterloo

URL: http://hdl.handle.net/10012/9097

► Impedance measurement plays a vital role in determining the physical and chemical properties of live cells under different environmental conditions and aids in the development… (more)

Subjects/Keywords: CMOS Impedance Measurement Array Cell Sensor Impedance-to-Digital Converter

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APA (6^th Edition):

Ali, A. (2015). CMOS Impedance Measurement Array for Cell Sensing. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/9097

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ali, Areeb. “CMOS Impedance Measurement Array for Cell Sensing.” 2015. Thesis, University of Waterloo. Accessed April 22, 2018. http://hdl.handle.net/10012/9097.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ali, Areeb. “CMOS Impedance Measurement Array for Cell Sensing.” 2015. Web. 22 Apr 2018.

Vancouver:

Ali A. CMOS Impedance Measurement Array for Cell Sensing. [Internet] [Thesis]. University of Waterloo; 2015. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/10012/9097.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ali A. CMOS Impedance Measurement Array for Cell Sensing. [Thesis]. University of Waterloo; 2015. Available from: http://hdl.handle.net/10012/9097

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

McMaster University

7. Palubiak, Dariusz. CMOS SINGLE PHOTON AVALANCHE DIODES AND TIME-TO-DIGITAL CONVERTERS FOR TIME-RESOLVED FLUORESCENCE ANALYSIS.

Degree: PhD, 2016, McMaster University

URL: http://hdl.handle.net/11375/18695

►

Fluorescence lifetime imaging (FLIM) has the potential to provide rapid screening and detection of diseases. However, time-resolved fluorescence measurements require high-performance detectors with single-photon sensitivity… (more)

▼

Fluorescence lifetime imaging (FLIM) has the potential to provide rapid screening and detection of diseases. However, time-resolved fluorescence measurements require high-performance detectors with single-photon sensitivity and sub-nanosecond time resolution. These systems should also be compact, reliable, inexpensive, and easily deployable for laboratory and clinical applications. It is with these applications in mind that the development of single photon avalanche diodes (SPAD) and time-to-digital converter (TDC) prototype integrated circuits (IC) in standard digital CMOS have been pursued in this thesis. SPAD and TDC ICs were designed and fabricated in 130 nm IBM CMOS technology and then intensively studied. Several different SPAD pixels were modeled and designed, and the electro-optical performance was characterized and comparatively studied. By repurposing existing design layers of a standard CMOS process, the fabricated SPAD pixel test structures achieved up to 20× improvement of dark count rate (DCR) compared to previous designs. Optical measurements also showed up to 10× improvement in the detection limits for low-level light. Detailed dark noise characterization was performed at various temperatures using free-running and time-gated modes of operation. Optimal operating conditions were found for minimal afterpulsing effects. The SPAD’s capability to accurately measure fast fluorescence decays was also demonstrated in a practical setting with the lifetime measurements of two fluorophores, Rhodamine 6G and Ruby crystal, which have fluorescence lifetimes of approximately 4 ns and 3 ms, respectively. A fast and accurate TDC prototype circuit for time-correlated single-photon counting (TCSPC) applications was designed, fabricated and characterized. With a coarse-fine delay line architecture, the TDC size was reduced without compromising its linearity and jitter performance. Extensive characterization of the fabricated SPAD and TDC ICs shows that the measured performance met the stated design goals.

Thesis

Doctor of Philosophy (PhD)

Advisors/Committee Members: Deen, Jamal, Electrical and Computer Engineering.

Subjects/Keywords: CMOS; Single photon detector; fluorescence lifetime; Time to Digital Converter

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APA (6^th Edition):

Palubiak, D. (2016). CMOS SINGLE PHOTON AVALANCHE DIODES AND TIME-TO-DIGITAL CONVERTERS FOR TIME-RESOLVED FLUORESCENCE ANALYSIS. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/18695

Chicago Manual of Style (16^th Edition):

Palubiak, Dariusz. “CMOS SINGLE PHOTON AVALANCHE DIODES AND TIME-TO-DIGITAL CONVERTERS FOR TIME-RESOLVED FLUORESCENCE ANALYSIS.” 2016. Doctoral Dissertation, McMaster University. Accessed April 22, 2018. http://hdl.handle.net/11375/18695.

MLA Handbook (7^th Edition):

Palubiak, Dariusz. “CMOS SINGLE PHOTON AVALANCHE DIODES AND TIME-TO-DIGITAL CONVERTERS FOR TIME-RESOLVED FLUORESCENCE ANALYSIS.” 2016. Web. 22 Apr 2018.

Vancouver:

Palubiak D. CMOS SINGLE PHOTON AVALANCHE DIODES AND TIME-TO-DIGITAL CONVERTERS FOR TIME-RESOLVED FLUORESCENCE ANALYSIS. [Internet] [Doctoral dissertation]. McMaster University; 2016. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/11375/18695.

Council of Science Editors:

Palubiak D. CMOS SINGLE PHOTON AVALANCHE DIODES AND TIME-TO-DIGITAL CONVERTERS FOR TIME-RESOLVED FLUORESCENCE ANALYSIS. [Doctoral Dissertation]. McMaster University; 2016. Available from: http://hdl.handle.net/11375/18695

8. Mello, Israel Sperotto de. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.

Degree: 2015, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/169086

► Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de… (more)

▼ Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de se reduzir o consumo de energia dos circuitos. Partiu-se dos antigos 5 V, padrão estabelecido pela lógica TTL nos anos 70, até os circuitos modernos que operam com alimentação pouco abaixo de 1 V. Entretanto, desde os primeiros anos da década de 2000, a tensão de alimentação está estabilizada neste patamar, devido a limitações tecnológicas que tem se mostrado difíceis de serem transpostas. Tal desafio tem sido estudado por grupos de pesquisa ao redor do mundo, e diversas estratégias tem sido propostas para se chegar a circuitos analógicos e digitais que operem sob tensão de alimentação bem inferior a 1 V. De fato estes grupos têm focado seus estudos em circuitos que operam com tensão de alimentação inferior a 0,5 V, alguns chegando à casa de 200 ou 100 mV, ou até menor. Dentre as diversas classes de circuitos, os conversores de dados dos tipos digital-analógico (DAC) e analógicodigital (ADC) são circuitos fundamentais ao processo de integração entre os módulos que processam sinais analogicamente e os que processam sinais digitalmente, sendo assim essenciais à implementação dos complexos SoCs (System-on-Chips) da atualidade. Este trabalho apresenta um estudo sobre o desempenho da configuração MOSFET em rede M-2M (similar à rede R-2R que emprega resistores), utilizada como circuito conversor digital-analógico, quando dimensionada para operar sob tensão de alimentação muito baixa, da ordem de 200 mV ou inferior. Tal estudo se baseia no emprego de um modelo para os MOSFETs que é contínuo desde a condição de inversão fraca (subthreshold) até a inversão forte, e inclui o uso de um modelo de descasamento entre MOSFETs que é válido para qualquer condição de operação. Com base neste estudo foi desenvolvida uma metodologia de projeto, capaz de estabelecer as relações de compromisso entre “tensão de alimentação”, “resolução efetiva” e “área ocupada em silício”, fundamentais para se atingir um circuito otimizado. Resultados de simulação elétrica são apresentados e confrontados com os resultados analíticos, visando a comprovação da metodologia. O circuito já foi enviado para fabricação, e deve começar a ser testado em breve. Advisors/Committee Members: Klimach, Hamilton Duarte.

Subjects/Keywords: Microeletrônica; CMOS analog design; Circuitos digitais; Low voltage design; Digital to analog converter; Mismatch

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APA (6^th Edition):

Mello, I. S. d. (2015). All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/169086

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mello, Israel Sperotto de. “All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed April 22, 2018. http://hdl.handle.net/10183/169086.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mello, Israel Sperotto de. “All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.” 2015. Web. 22 Apr 2018.

Vancouver:

Mello ISd. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/10183/169086.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mello ISd. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/169086

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Louisiana State University

9. Sathiaraj, Josephine Ratna. Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS.

Degree: MS, Electrical and Computer Engineering, 2009, Louisiana State University

URL: etd-11072009-170319 ; https://digitalcommons.lsu.edu/gradschool_theses/3963

► In this work, a ternary to binary converter circuit is designed in 0.5μm n-well CMOS technology. The circuit takes two inputs corresponding to the ternary… (more)

Subjects/Keywords: multivalued logic; multiple input CMOS; ternary to binary converter; floating gate MOSFET

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APA (6^th Edition):

Sathiaraj, J. R. (2009). Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS. (Masters Thesis). Louisiana State University. Retrieved from etd-11072009-170319 ; https://digitalcommons.lsu.edu/gradschool_theses/3963

Chicago Manual of Style (16^th Edition):

Sathiaraj, Josephine Ratna. “Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS.” 2009. Masters Thesis, Louisiana State University. Accessed April 22, 2018. etd-11072009-170319 ; https://digitalcommons.lsu.edu/gradschool_theses/3963.

MLA Handbook (7^th Edition):

Sathiaraj, Josephine Ratna. “Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS.” 2009. Web. 22 Apr 2018.

Vancouver:

Sathiaraj JR. Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS. [Internet] [Masters thesis]. Louisiana State University; 2009. [cited 2018 Apr 22]. Available from: etd-11072009-170319 ; https://digitalcommons.lsu.edu/gradschool_theses/3963.

Council of Science Editors:

Sathiaraj JR. Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS. [Masters Thesis]. Louisiana State University; 2009. Available from: etd-11072009-170319 ; https://digitalcommons.lsu.edu/gradschool_theses/3963

Delft University of Technology

10. Luo, Y. A High-Resolution, Resistor-Based Temperature Sensor:.

Degree: 2015, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:9654be35-8148-41d5-8ac3-b8124d71e55e

► This thesis focuses on developing a high-resolution, energy-efficient smart temperature sensor. A resistor-based temperature-sensing structure is chosen as the core of the sensor. To digitize… (more)

Subjects/Keywords: CMOS; temperature sensor; sensor interface; thermistor; Wien Bridge; delta-sigma; analog-to-digital converter

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APA (6^th Edition):

Luo, Y. (2015). A High-Resolution, Resistor-Based Temperature Sensor:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:9654be35-8148-41d5-8ac3-b8124d71e55e

Chicago Manual of Style (16^th Edition):

Luo, Y. “A High-Resolution, Resistor-Based Temperature Sensor:.” 2015. Masters Thesis, Delft University of Technology. Accessed April 22, 2018. http://resolver.tudelft.nl/uuid:9654be35-8148-41d5-8ac3-b8124d71e55e.

MLA Handbook (7^th Edition):

Luo, Y. “A High-Resolution, Resistor-Based Temperature Sensor:.” 2015. Web. 22 Apr 2018.

Vancouver:

Luo Y. A High-Resolution, Resistor-Based Temperature Sensor:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2018 Apr 22]. Available from: http://resolver.tudelft.nl/uuid:9654be35-8148-41d5-8ac3-b8124d71e55e.

Council of Science Editors:

Luo Y. A High-Resolution, Resistor-Based Temperature Sensor:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:9654be35-8148-41d5-8ac3-b8124d71e55e

University of Toronto

11. Shahramian, Shahriar. Millimeter-wave Analog to Digital Converters: Technology Challenges and Architectures.

Degree: 2011, University of Toronto

URL: http://hdl.handle.net/1807/30039

►

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was… (more)

Subjects/Keywords: Analog to Digital Converter; mm-Wave Circuit; Track and Hold Amplifier; SiGe; CMOS; Data Converter; TIALA; Retimer; 0544

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APA (6^th Edition):

Shahramian, S. (2011). Millimeter-wave Analog to Digital Converters: Technology Challenges and Architectures. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/30039

Chicago Manual of Style (16^th Edition):

Shahramian, Shahriar. “Millimeter-wave Analog to Digital Converters: Technology Challenges and Architectures.” 2011. Doctoral Dissertation, University of Toronto. Accessed April 22, 2018. http://hdl.handle.net/1807/30039.

MLA Handbook (7^th Edition):

Shahramian, Shahriar. “Millimeter-wave Analog to Digital Converters: Technology Challenges and Architectures.” 2011. Web. 22 Apr 2018.

Vancouver:

Shahramian S. Millimeter-wave Analog to Digital Converters: Technology Challenges and Architectures. [Internet] [Doctoral dissertation]. University of Toronto; 2011. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/1807/30039.

Council of Science Editors:

Shahramian S. Millimeter-wave Analog to Digital Converters: Technology Challenges and Architectures. [Doctoral Dissertation]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/30039

Indian Institute of Science

12. Harish, C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.

Degree: 2011, Indian Institute of Science

URL: http://hdl.handle.net/2005/2049

► This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of… (more)

▼ This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB. Advisors/Committee Members: Jamadagni, H S.

Subjects/Keywords: Analog to Digital Converter (ADC); CMOS Technologies; Analog to Digital Signal Processing; Sigma Delta ADC; Wireless Applications; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Harish, C. (2011). Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Thesis, Indian Institute of Science. Accessed April 22, 2018. http://hdl.handle.net/2005/2049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Web. 22 Apr 2018.

Vancouver:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/2005/2049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Thesis]. Indian Institute of Science; 2011. Available from: http://hdl.handle.net/2005/2049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

13. Harish, C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.

Degree: 2011, Indian Institute of Science

URL: http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf

► This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of… (more)

▼ This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB. Advisors/Committee Members: Jamadagni, H S.

Subjects/Keywords: Analog to Digital Converter (ADC); CMOS Technologies; Analog to Digital Signal Processing; Sigma Delta ADC; Wireless Applications; Communication Engineering

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Harish, C. (2011). Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Thesis, Indian Institute of Science. Accessed April 22, 2018. http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Web. 22 Apr 2018.

Vancouver:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2018 Apr 22]. Available from: http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Université Catholique de Louvain

14. Couniot, Numa. Highly-sensitive CMOS capacitive biosensors towards detection of single bacterial cell in electrolyte solutions.

Degree: 2015, Université Catholique de Louvain

URL: http://hdl.handle.net/2078.1/165272

►

For centuries, bacterial cells have been one of the major causes of human diseases, and are still responsible for several millions of deaths every year.… (more)

▼

For centuries, bacterial cells have been one of the major causes of human diseases, and are still responsible for several millions of deaths every year. Rapid detection and identification of pathogens in clinical, food or water samples is an important prerequisite step to establish a diagnosis and prevent the disease propagation. This thesis investigates how capacitive biosensors can be used for rapid, selective and sensitive pathogen detec- tion in various biological buffers. Their integration with microfluidics, electrokinetics and CMOS technology is provided towards miniaturized and affordable lab-on-chips for point-of-care diagnosis tools. The first part of the thesis studies the capacitive transduction, based on Al/Al2O3 interdigitated microelectrodes (IDEs). Real-time detection of Staphylococcus epidermidis in low-conductive solutions is experimentally shown, and explained by a comprehensive analytical model of the transducer. An innovative selectivity principle using lytic enzymes is then presented and shown to selectively detect of S. epidermidis among Enterococcus faecium cells in synthetic urine. Thanks to numerical simulations using Poisson-Nernst-Planck equations, the capacitive biosensor parameters are eventually optimized towards the maximal sensitivity. The second part of the thesis investigates the use of electrokinetic effects to attract bacterial cells on the surface of capacitive biosensors. By using an annular ring macroelectrode encompassing the IDEs, short and long-range trapping of S. epidermidis were observed and attributed to contactless dielectrophoresis and electrothermal flow, respectively. At 63 MHz precisely, a resonance effect related to device connectors was found to dramatically increase the trapping of S. epidermidis lowering the detection limit by two orders of magnitude. Analytical models and numerical simulations are provided to explain the observed phenomena. The last part of the thesis focuses on the design of two analog circuits to interface on-chip capacitive biosensors in a 0.25-μm CMOS technology. The first is a capacitance-to-frequency converter working up to 575 MHz which demonstrates sensitivity to bacterial cells in high-conductive solutions. The second is a 16 × 16 capacitive biosensor array featuring micrometer-sized pixels to lower the absolute number of detectable bacteria to ca. 7. The innovative pixel architecture uses a capacitance-to-voltage converter followed by a gain stage to boost the sensitivity. In conclusion, capacitive biosensors towards bacteria detection have extensively been studied in this thesis, first starting from the transduction principles and then integrating them into advanced electrokinetic and electronic systems. The innovations provided in this thesis offer interesting perspectives for the next generations of capacitive biosensors targeting point-of-care diagnosis of bacterial cells.

(FSA - Sciences de l'ingénieur) – UCL, 2015

Advisors/Committee Members: UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique, UCL - Ecole Polytechnique de Louvain, Flandre, Denis, Francis, Laurent, Bol, David, Afzalian, Aryan, Sawan, Mohamad, Ingebrandt, Sven.

Subjects/Keywords: Biosensor; Electrokinetic; Capacitance-to-Frequency converter; Bacteria detection; Impedance spectroscopy; CMOS; Capacitive biosensors; Dielectrophoresis; Electroosmosis; Biosensor array

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Couniot, N. (2015). Highly-sensitive CMOS capacitive biosensors towards detection of single bacterial cell in electrolyte solutions. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/165272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Couniot, Numa. “Highly-sensitive CMOS capacitive biosensors towards detection of single bacterial cell in electrolyte solutions.” 2015. Thesis, Université Catholique de Louvain. Accessed April 22, 2018. http://hdl.handle.net/2078.1/165272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Couniot, Numa. “Highly-sensitive CMOS capacitive biosensors towards detection of single bacterial cell in electrolyte solutions.” 2015. Web. 22 Apr 2018.

Vancouver:

Couniot N. Highly-sensitive CMOS capacitive biosensors towards detection of single bacterial cell in electrolyte solutions. [Internet] [Thesis]. Université Catholique de Louvain; 2015. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/2078.1/165272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Couniot N. Highly-sensitive CMOS capacitive biosensors towards detection of single bacterial cell in electrolyte solutions. [Thesis]. Université Catholique de Louvain; 2015. Available from: http://hdl.handle.net/2078.1/165272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Rochester

15. Song, Yu (1980 - ). CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques.

Degree: PhD, 2011, University of Rochester

URL: http://hdl.handle.net/1802/16887

► We propose and verify the design of low-power, high-performance CMOS Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In low-cost CMOS semiconductor processes, SC… (more)

Subjects/Keywords: Analog-to-digital converter; CMOS integrated circuits; Delta-sigma modulation; Phase-locked loop; Switched-capacitor circuit

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APA (6^th Edition):

Song, Y. (. -. ). (2011). CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/16887

Chicago Manual of Style (16^th Edition):

Song, Yu (1980 - ). “CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques.” 2011. Doctoral Dissertation, University of Rochester. Accessed April 22, 2018. http://hdl.handle.net/1802/16887.

MLA Handbook (7^th Edition):

Song, Yu (1980 - ). “CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques.” 2011. Web. 22 Apr 2018.

Vancouver:

Song Y(-). CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques. [Internet] [Doctoral dissertation]. University of Rochester; 2011. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/1802/16887.

Council of Science Editors:

Song Y(-). CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques. [Doctoral Dissertation]. University of Rochester; 2011. Available from: http://hdl.handle.net/1802/16887

Universidade Nova

16. Silva, Alexandre Herculano Mendes. Pipelined analog-to-digital conversion using current-mode reference shifting.

Degree: 2012, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265

►

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Pipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high… (more)

Subjects/Keywords: Analog-to-Digital Converter (ADC),; Current-mode reference shifting; Switched-capacitor; CMOS current reference; pipelined A/D conversion

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APA (6^th Edition):

Silva, A. H. M. (2012). Pipelined analog-to-digital conversion using current-mode reference shifting. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Silva, Alexandre Herculano Mendes. “Pipelined analog-to-digital conversion using current-mode reference shifting.” 2012. Thesis, Universidade Nova. Accessed April 22, 2018. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Silva, Alexandre Herculano Mendes. “Pipelined analog-to-digital conversion using current-mode reference shifting.” 2012. Web. 22 Apr 2018.

Vancouver:

Silva AHM. Pipelined analog-to-digital conversion using current-mode reference shifting. [Internet] [Thesis]. Universidade Nova; 2012. [cited 2018 Apr 22]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Silva AHM. Pipelined analog-to-digital conversion using current-mode reference shifting. [Thesis]. Universidade Nova; 2012. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Linköping University

17. Zhang, Dai. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.

Degree: Electrical Engineering, 2009, Linköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

► Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system.… (more)

Subjects/Keywords: Analog-to-digital converter (ADC); charge redistribution; CMOS; low power; low supply voltage; successive approximation; latched comparator; Electrical engineering; Elektroteknik

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APA (6^th Edition):

Zhang, D. (2009). Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Thesis, Linköping University. Accessed April 22, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Web. 22 Apr 2018.

Vancouver:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Internet] [Thesis]. Linköping University; 2009. [cited 2018 Apr 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Thesis]. Linköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Michigan

18. Ansari Ogholbeik, Elnaz. Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies.

Degree: PhD, Electrical Engineering, 2016, University of Michigan

URL: http://hdl.handle.net/2027.42/133177

► Today’s integrated system on chips (SoCs) usually consist of billions of transistors accounting for both digital and analog blocks. Integrating such massive blocks on a… (more)

Subjects/Keywords: Design Automation; Very Large Scale Analog (VLSA); Digital to Analog Converter (DAC); Beyond CMOS; Internet of Things (IoT); Electrical Engineering; Engineering

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APA (6^th Edition):

Ansari Ogholbeik, E. (2016). Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/133177

Chicago Manual of Style (16^th Edition):

Ansari Ogholbeik, Elnaz. “Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies.” 2016. Doctoral Dissertation, University of Michigan. Accessed April 22, 2018. http://hdl.handle.net/2027.42/133177.

MLA Handbook (7^th Edition):

Ansari Ogholbeik, Elnaz. “Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies.” 2016. Web. 22 Apr 2018.

Vancouver:

Ansari Ogholbeik E. Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies. [Internet] [Doctoral dissertation]. University of Michigan; 2016. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/2027.42/133177.

Council of Science Editors:

Ansari Ogholbeik E. Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies. [Doctoral Dissertation]. University of Michigan; 2016. Available from: http://hdl.handle.net/2027.42/133177

INP Toulouse

19. Perbet, Lucas. Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial : Optimization of building blocks of a pipeline ADC in CMOS 0.18µm technology for space applications.

Degree: Docteur es, Micro Nano Systèmes, 2017, INP Toulouse

URL: http://www.theses.fr/2017INPT0037

►

L’imagerie constitue un axe majeur de l’exploration de l’univers et de la Terre depuis l’espace, que l’on se trouve dans le domaine du visible ou… (more)

▼

L’imagerie constitue un axe majeur de l’exploration de l’univers et de la Terre depuis l’espace, que l’on se trouve dans le domaine du visible ou non. Ainsi dans le domaine spatial, les données sont le plus souvent récupérées par un capteur CCD (Charge-Coupled Device, ou Dispositif à Transfert de Charge (DTC)) qui fournit des tensions analogiques vers un convertisseur analogique-numérique (CAN), dont la sortie sera transmise à une chaîne de traitement, puis envoyée sur terre. Ainsi, les CAN sont des éléments clés dans l’imagerie par satellite. De leur précision et de leur vitesse va dépendre la qualité de la représentativité de la chaîne de signaux binaires. Il est donc crucial de réaliser une conversion de données de grande qualité (vitesse, précision) tout en s’assurant de la résistance du CAN à l’environnement radiatif. L’objectif de cette thèse est d’améliorer la robustesse à l’environnement spatial, tout en optimisant les performances, de plusieurs fonctions élémentaires d’un convertisseur analogique-numérique de type pipeline 14bits,5MS/s, réalisées en technologie XFAB 0,18µm. Les trois fonctions ciblées sont les interrupteurs (notamment la résolution des problèmes liés au phénomène d’injection de charges en environnement spatial), les comparateurs (durcissement) et l’amplificateur à capacités commutées (amélioration du gain par une technique prédictive sans pénaliser la puissance consommée).

Imaging is a major issue in the observation of the Universe and the Earth from space, whether in the visible domain or not. Thus, in the spatial field, data is often gathered by a CCD (charge-Coupled Device) sensor, that supplies analog voltages to an Analog-to-Digital Converter (ADC), which outputs will be delivered to a processing chain, and then sent to earth. Consequently, ADCs are key elements in satellite imaging. Their precision and speed will indeed define the quality and the representativeness of the binary signal. It is then crucial to perform a high quality (speed & precision) conversion of the data, while making sure that the ADC can cope with the harsh irradiative environment. The purpose of this thesis is to improve the robustness to the space environment (hardening), while optimizing the performances, of several elementary devices that compose a 14 bits, 5MS/s pipeline ADC, made with the XFAB 180nm technology. The three targeted functions are the switches (especially the problems linked to coping with the charge injection problems in a space environment), the comparators (hardening) and the switched-capacitor amplifier (gain boosting through a predictive architecture with no penalty on the power consumption).

Advisors/Committee Members: Tap-Béteille, Hélène (thesis director).

Subjects/Keywords: Convertisseur analogique-numérique; Interrupteur; Comparateur; Amplificateur; Environnement spatial; CMOS; ASIC; Analog-to-Digital converter; Switch; Comparator; Amplifier; Space environment; CMOS; ASIC; 621.381

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Perbet, L. (2017). Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial : Optimization of building blocks of a pipeline ADC in CMOS 0.18µm technology for space applications. (Doctoral Dissertation). INP Toulouse. Retrieved from http://www.theses.fr/2017INPT0037

Chicago Manual of Style (16^th Edition):

Perbet, Lucas. “Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial : Optimization of building blocks of a pipeline ADC in CMOS 0.18µm technology for space applications.” 2017. Doctoral Dissertation, INP Toulouse. Accessed April 22, 2018. http://www.theses.fr/2017INPT0037.

MLA Handbook (7^th Edition):

Perbet, Lucas. “Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial : Optimization of building blocks of a pipeline ADC in CMOS 0.18µm technology for space applications.” 2017. Web. 22 Apr 2018.

Vancouver:

Perbet L. Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial : Optimization of building blocks of a pipeline ADC in CMOS 0.18µm technology for space applications. [Internet] [Doctoral dissertation]. INP Toulouse; 2017. [cited 2018 Apr 22]. Available from: http://www.theses.fr/2017INPT0037.

Council of Science Editors:

Perbet L. Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial : Optimization of building blocks of a pipeline ADC in CMOS 0.18µm technology for space applications. [Doctoral Dissertation]. INP Toulouse; 2017. Available from: http://www.theses.fr/2017INPT0037

Georgia Tech

20. Chuang, Kevin. Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

URL: http://hdl.handle.net/1853/47814

► The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology.… (more)

Subjects/Keywords: Analog-to-digital converter; Mixed-signal; Demodulator; Multi-gigabit; CMOS; Analog-to-digital converters; Metal oxide semiconductors, Complementary; Radio detectors; Millimeter wave communication systems

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APA (6^th Edition):

Chuang, K. (2011). Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47814

Chicago Manual of Style (16^th Edition):

Chuang, Kevin. “Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems.” 2011. Doctoral Dissertation, Georgia Tech. Accessed April 22, 2018. http://hdl.handle.net/1853/47814.

MLA Handbook (7^th Edition):

Chuang, Kevin. “Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems.” 2011. Web. 22 Apr 2018.

Vancouver:

Chuang K. Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/1853/47814.

Council of Science Editors:

Chuang K. Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/47814

California State University – Sacramento

21. Morgan, Jeffrey. Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

URL: http://hdl.handle.net/10211.3/190177

► The design and simulation of a phase frequency detector and a charge pump for a low-jitter, high-frequency phase-locked loop in 0.18??m CMOS are explored. The… (more)

Subjects/Keywords: CMOS; Analog/Mixed-signal; Integrated circuit; CML; Current-mode logic; Operational amplifier; Microelectronics

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APA (6^th Edition):

Morgan, J. (2017). Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/190177

Chicago Manual of Style (16^th Edition):

Morgan, Jeffrey. “Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS.” 2017. Masters Thesis, California State University – Sacramento. Accessed April 22, 2018. http://hdl.handle.net/10211.3/190177.

MLA Handbook (7^th Edition):

Morgan, Jeffrey. “Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS.” 2017. Web. 22 Apr 2018.

Vancouver:

Morgan J. Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/10211.3/190177.

Council of Science Editors:

Morgan J. Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/190177

University of Lund

22. Andersson, Mattias. Continuous-Time Delta-Sigma Modulators for Wireless Communication.

Degree: 2014, University of Lund

URL: http://lup.lub.lu.se/record/4302214 ; http://portal.research.lu.se/ws/files/3333980/4302260.pdf

► The ever increasing data rates in wireless communication require analog to digital converters (ADCs) with greater requirements on speed and accuracy, while being power efficient… (more)

▼ The ever increasing data rates in wireless communication require analog to digital converters (ADCs) with greater requirements on speed and accuracy, while being power efficient to prolong battery life. This dissertation contains an introduction to the field and five papers that focus on the continuous-time (CT) Delta-Sigma modulator (DSM) as ADC. Paper I analyses the performance degradation of dynamic nonlinearity in the feedback DAC of the DSM, caused by Vth mismatch in the current-switching (differential) pair of a current-steering DAC. A model is developed to study return-to-zero (RZ) and non-return-to-zero (NRZ) feedback DACs, with and without data-weighted averaging (DWA), where an RZ DAC with DWA recovers the performance. Paper II and III presents a feedback scheme for improved robustness against variations in loop delay. An RZ pulse, centered in the clock period, is used in the innermost feedback path which has the highest sensitivity to loop delay, while NRZ pulses are adopted in the outer feedback paths to reduce the sensitivity to clock jitter and lower the integrator slew rate requirements. Furthermore, the otherwise obligatory loop delay compensation path (e.g. an additional DAC and adder) could be omitted to reduce hardware complexity. A discrete-time model of the feedback scheme confirms a negligible loss in performance. The 3rd-order CT DSM in 65nm CMOS with 9MHz LTE bandwidth achieves 69/71dB SNDR/SNR and consumes 7.5mW from a 1.2V supply. Measurements with OFDM signals verify an improved tolerance to blockers outside the signal band of the DSM. Paper IV and V present two filtering ADCs, where the DSM is merged into the channel select filter to suppress the noise from the DSM. The first and second prototypes provide a 2nd- and 3rd-order channel select filtering and improve the SNDR of the DSM by 14dB and 20dB, respectively, which in theory can be exploited to reduce the DSM power consumption by four to eight times. The first prototype has a 288MHz clock frequency, a 9MHz LTE bandwidth, a 2nd-order Butterworth filter response with 12dB gain, an input-referred noise of 8.1nV/sqrt(Hz), an in/out-of-band IIP3 of 11.5/27dBVrms, and a power consumption of 11.3mW. The second prototype is clocked at 576/288MHz with an 18.5/9MHz LTE bandwidth, a Chebyshev filter response with 26dB gain, a low input-referred noise of 5nV/sqrt(Hz), and an in/out-of-band IIP3 of -8.5/20dBVrms, with a power consumption of 7.9/5.4mW for 2xLTE20/LTE20 mode. The prototype was characterized for OFDM modulated blockers and essentially meets the cellular standard LTE Rel. 11. A delay, introduced by the feedback DAC, is compensated by adjusting the filter coefficients to restore the original Chebyshev filter function. Both prototypes have state-of-the-art power efficiency compared to other filtering ADCs and are comparable or better than a stand-alone filter. Furthermore, the filtering ADC provides both filtering and A/D conversion, which suggests that the A/D conversion is included in a power efficient manner, broadly speaking "for…

Subjects/Keywords: Elektroteknik och elektronik; return-to-zero; A/D converter; loop delay; delta-sigma; ADC; CMOS; STF; continuous-time; sigma; delta; filtering; CT; RZ

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Andersson, M. (2014). Continuous-Time Delta-Sigma Modulators for Wireless Communication. (Doctoral Dissertation). University of Lund. Retrieved from http://lup.lub.lu.se/record/4302214 ; http://portal.research.lu.se/ws/files/3333980/4302260.pdf

Chicago Manual of Style (16^th Edition):

Andersson, Mattias. “Continuous-Time Delta-Sigma Modulators for Wireless Communication.” 2014. Doctoral Dissertation, University of Lund. Accessed April 22, 2018. http://lup.lub.lu.se/record/4302214 ; http://portal.research.lu.se/ws/files/3333980/4302260.pdf.

MLA Handbook (7^th Edition):

Andersson, Mattias. “Continuous-Time Delta-Sigma Modulators for Wireless Communication.” 2014. Web. 22 Apr 2018.

Vancouver:

Andersson M. Continuous-Time Delta-Sigma Modulators for Wireless Communication. [Internet] [Doctoral dissertation]. University of Lund; 2014. [cited 2018 Apr 22]. Available from: http://lup.lub.lu.se/record/4302214 ; http://portal.research.lu.se/ws/files/3333980/4302260.pdf.

Council of Science Editors:

Andersson M. Continuous-Time Delta-Sigma Modulators for Wireless Communication. [Doctoral Dissertation]. University of Lund; 2014. Available from: http://lup.lub.lu.se/record/4302214 ; http://portal.research.lu.se/ws/files/3333980/4302260.pdf

23. Zhang, Liang. Development of a CMOS pixel sensor for the outer layers of the ILC vertex detector : Développement d'un capteur de pixels CMOS pour les couches externes du détecteur de vertex ILC.

Degree: Docteur es, Instrumentation et microélectronique, 2013, Université de Strasbourg

URL: http://www.theses.fr/2013STRAE036

►

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International… (more)

▼

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs.

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Advisors/Committee Members: Hu, Yann (thesis director).

Subjects/Keywords: Capteur à pixel CMOS; International Linear Collider (ILC); Détecteur vertex; MIMOSA 31; CMOS pixel sensors (CPS); Monolithic active pixel sensors (MAPS); International Linear Collider (ILC); Vertex detector; Correlated double sampling (CDS); Analog to digital converter (ADC); Column-level; Self-triggered; Multi-bit/step approximation; 539.7; 621.38

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APA (6^th Edition):

Zhang, L. (2013). Development of a CMOS pixel sensor for the outer layers of the ILC vertex detector : Développement d'un capteur de pixels CMOS pour les couches externes du détecteur de vertex ILC. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2013STRAE036

Chicago Manual of Style (16^th Edition):

Zhang, Liang. “Development of a CMOS pixel sensor for the outer layers of the ILC vertex detector : Développement d'un capteur de pixels CMOS pour les couches externes du détecteur de vertex ILC.” 2013. Doctoral Dissertation, Université de Strasbourg. Accessed April 22, 2018. http://www.theses.fr/2013STRAE036.

MLA Handbook (7^th Edition):

Zhang, Liang. “Development of a CMOS pixel sensor for the outer layers of the ILC vertex detector : Développement d'un capteur de pixels CMOS pour les couches externes du détecteur de vertex ILC.” 2013. Web. 22 Apr 2018.

Vancouver:

Zhang L. Development of a CMOS pixel sensor for the outer layers of the ILC vertex detector : Développement d'un capteur de pixels CMOS pour les couches externes du détecteur de vertex ILC. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2013. [cited 2018 Apr 22]. Available from: http://www.theses.fr/2013STRAE036.

Council of Science Editors:

Zhang L. Development of a CMOS pixel sensor for the outer layers of the ILC vertex detector : Développement d'un capteur de pixels CMOS pour les couches externes du détecteur de vertex ILC. [Doctoral Dissertation]. Université de Strasbourg; 2013. Available from: http://www.theses.fr/2013STRAE036

24. Branca, Xavier. Etude et conception d'un convertisseur de tension mono-inductance double-sortie bipolaires pour la téléphonie mobile : Study and realisation of a single inductor bipolar output converter for mobile platforms.

Degree: Docteur es, Electrotechnique, 2012, INSA Lyon

URL: http://www.theses.fr/2012ISAL0059

►

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application… (more)

▼

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales.

The objectives of this thesis were the optimization of the power efficiency and the minimization of the…

Advisors/Committee Members: Lin-Shi, Xuefang (thesis director), Allard, Bruno (thesis director).

Subjects/Keywords: Télécommunications; Téléphonie mobile; Communication mobile; Amplificateur audio; Convertisseur DC-DC; Electronique analogique; Microélectronique; Technologie CMOS; Telecommunications; Mobile communication; Audio amplifier; DC-to-DC converter; Analog Electronics; Microelectronics; CMOS Technology; 621.381 044 072

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Branca, X. (2012). Etude et conception d'un convertisseur de tension mono-inductance double-sortie bipolaires pour la téléphonie mobile : Study and realisation of a single inductor bipolar output converter for mobile platforms. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2012ISAL0059

Chicago Manual of Style (16^th Edition):

Branca, Xavier. “Etude et conception d'un convertisseur de tension mono-inductance double-sortie bipolaires pour la téléphonie mobile : Study and realisation of a single inductor bipolar output converter for mobile platforms.” 2012. Doctoral Dissertation, INSA Lyon. Accessed April 22, 2018. http://www.theses.fr/2012ISAL0059.

MLA Handbook (7^th Edition):

Branca, Xavier. “Etude et conception d'un convertisseur de tension mono-inductance double-sortie bipolaires pour la téléphonie mobile : Study and realisation of a single inductor bipolar output converter for mobile platforms.” 2012. Web. 22 Apr 2018.

Vancouver:

Branca X. Etude et conception d'un convertisseur de tension mono-inductance double-sortie bipolaires pour la téléphonie mobile : Study and realisation of a single inductor bipolar output converter for mobile platforms. [Internet] [Doctoral dissertation]. INSA Lyon; 2012. [cited 2018 Apr 22]. Available from: http://www.theses.fr/2012ISAL0059.

Council of Science Editors:

Branca X. Etude et conception d'un convertisseur de tension mono-inductance double-sortie bipolaires pour la téléphonie mobile : Study and realisation of a single inductor bipolar output converter for mobile platforms. [Doctoral Dissertation]. INSA Lyon; 2012. Available from: http://www.theses.fr/2012ISAL0059

Brno University of Technology

25. Dušek, Petr. Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS .

Degree: 2015, Brno University of Technology

URL: http://hdl.handle.net/11012/39890

► Tato práce se zabývá návrhem přesného digitálně analogového převodníku, dále jen DAC. Práce poskytuje podklady pro pochopení principu převodu digitálního signálu na signál analogový. V… (more)

Subjects/Keywords: Technologie CMOS; převodník DA; nízkonapěťové aplikace; CMOS technology; DA converter; low voltage applications

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APA (6^th Edition):

Dušek, P. (2015). Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/39890

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Dušek, Petr. “Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS .” 2015. Thesis, Brno University of Technology. Accessed April 22, 2018. http://hdl.handle.net/11012/39890.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Dušek, Petr. “Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS .” 2015. Web. 22 Apr 2018.

Vancouver:

Dušek P. Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS . [Internet] [Thesis]. Brno University of Technology; 2015. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/11012/39890.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dušek P. Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS . [Thesis]. Brno University of Technology; 2015. Available from: http://hdl.handle.net/11012/39890

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

26. Javed, Gaggatur Syed. Integrated Interfaces for Sensing Applications.

Degree: 2016, Indian Institute of Science

URL: http://hdl.handle.net/2005/2914

► Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy,… (more)

▼ Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area eﬃcient, integrated sensor interface for applications like capacitance, temperature and dielectric-constant measurement. In addition, potential applica-tions for this work are in Cognitive Radios, Software Deﬁned Radios, Capacitance Sensors, and location monitoring. The key contributions in the thesis are: 1 High Sensitivity Frequency-domain CMOS Capacitance Interface: A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period diﬀerence of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. It exhibits a maximum sensitivity of 8.1 mV/fF across a 300 fF capacitance range. 2 Sensitivity Enhancement for capacitance sensor: The sensitivity of an oscillator-based diﬀerential capacitance sensor has been improved by proposing a novel frequency domain capacitance-to-voltage (FDC) measurement technique. The capacitance sensor interface system is fabricated in a 130-nm CMOS technology with an active area of 0.17mm2 . It exhibits a maximum sensitivity of 244.8 mV/fF and a measurement resolution of 13 aF in a 10-100 fF measurement range, with a 10 pF nominal sensor capacitance and an 8-bit ADC. 3 Frequency to Digital Converter for Time/Distance measurement: A new architecture for a Vernier-based frequency-to-digital converter (VFDC) for location monitoring is pre¬sented, in which, a time interval measurement is performed with a frequency domain approach. Location monitoring is a common problem for many mobile robotic applica¬tions covering various domains, such as industrial automation, manipulation in diﬃcult areas, rescue operations, environment exploration and monitoring, smart environments and buildings, robotic home appliances, space exploration and probing. The proposed architecture employs a new injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital convert¬ers. It consumes 14.4 µW and 1.15 mW from 0.4 V and 1.2 V supplies, respectively. The proposed VFDC thus achieves a large detectable range, ﬁne time resolution, small die size and… Advisors/Committee Members: Banerjee, Gaurab.

Subjects/Keywords: Sensing Applications;

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APA (6^th Edition):

Javed, G. S. (2016). Integrated Interfaces for Sensing Applications. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2914

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Javed, Gaggatur Syed. “Integrated Interfaces for Sensing Applications.” 2016. Thesis, Indian Institute of Science. Accessed April 22, 2018. http://hdl.handle.net/2005/2914.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Javed, Gaggatur Syed. “Integrated Interfaces for Sensing Applications.” 2016. Web. 22 Apr 2018.

Vancouver:

Javed GS. Integrated Interfaces for Sensing Applications. [Internet] [Thesis]. Indian Institute of Science; 2016. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/2005/2914.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Javed GS. Integrated Interfaces for Sensing Applications. [Thesis]. Indian Institute of Science; 2016. Available from: http://hdl.handle.net/2005/2914

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Georgia Tech

27. Kim, Suhwan. Mixed-source charger-supply CMOS IC.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

URL: http://hdl.handle.net/1853/52210

► The proposed research objective is to develop, test, and evaluate a mixer and charger-supply CMOS IC that derives and mixes energy and power from mixed… (more)

Subjects/Keywords: DC-DC converter; CMOS; Power supply; Hybrid source

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APA (6^th Edition):

Kim, S. (2014). Mixed-source charger-supply CMOS IC. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52210

Chicago Manual of Style (16^th Edition):

Kim, Suhwan. “Mixed-source charger-supply CMOS IC.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 22, 2018. http://hdl.handle.net/1853/52210.

MLA Handbook (7^th Edition):

Kim, Suhwan. “Mixed-source charger-supply CMOS IC.” 2014. Web. 22 Apr 2018.

Vancouver:

Kim S. Mixed-source charger-supply CMOS IC. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/1853/52210.

Council of Science Editors:

Kim S. Mixed-source charger-supply CMOS IC. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52210

University of Texas – Austin

28. Jung, Woo Young. Time-based oversampled analog-to-digital converters in nano-scale integrated circuits.

Degree: Electrical and Computer Engineering, 2014, University of Texas – Austin

URL: http://hdl.handle.net/2152/29195

► In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable… (more)

Subjects/Keywords: Analog-to-digital converter; Delta-sigma modulation; Time-to-digital converter; Pulse-width modulation; Digital-to-time converter

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APA (6^th Edition):

Jung, W. Y. (2014). Time-based oversampled analog-to-digital converters in nano-scale integrated circuits. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/29195

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jung, Woo Young. “Time-based oversampled analog-to-digital converters in nano-scale integrated circuits.” 2014. Thesis, University of Texas – Austin. Accessed April 22, 2018. http://hdl.handle.net/2152/29195.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jung, Woo Young. “Time-based oversampled analog-to-digital converters in nano-scale integrated circuits.” 2014. Web. 22 Apr 2018.

Vancouver:

Jung WY. Time-based oversampled analog-to-digital converters in nano-scale integrated circuits. [Internet] [Thesis]. University of Texas – Austin; 2014. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/2152/29195.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jung WY. Time-based oversampled analog-to-digital converters in nano-scale integrated circuits. [Thesis]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/29195

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

29. Buček, Vladimír. Operacni zesilovač CMOS pracující v rozsahu napájecích napětí .

Degree: 2009, Brno University of Technology

URL: http://hdl.handle.net/11012/7330

► Cílem této práce bylo seznámit se s návrhem operačního zesilovače technologií CMOS. Nejdříve byla analyzována struktura tranzistorů PMOS a NMOS, díky kterým jsme mohli postupně… (more)

Subjects/Keywords: operační zesilovač; CMOS; rail-to-rail; operational amplifier; CMOS; rail-to-rail

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APA (6^th Edition):

Buček, V. (2009). Operacni zesilovač CMOS pracující v rozsahu napájecích napětí . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/7330

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Buček, Vladimír. “Operacni zesilovač CMOS pracující v rozsahu napájecích napětí .” 2009. Thesis, Brno University of Technology. Accessed April 22, 2018. http://hdl.handle.net/11012/7330.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Buček, Vladimír. “Operacni zesilovač CMOS pracující v rozsahu napájecích napětí .” 2009. Web. 22 Apr 2018.

Vancouver:

Buček V. Operacni zesilovač CMOS pracující v rozsahu napájecích napětí . [Internet] [Thesis]. Brno University of Technology; 2009. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/11012/7330.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Buček V. Operacni zesilovač CMOS pracující v rozsahu napájecích napětí . [Thesis]. Brno University of Technology; 2009. Available from: http://hdl.handle.net/11012/7330

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Georgia Tech

30. Miri Lavasani, Seyed Hossein. Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

URL: http://hdl.handle.net/1853/41096

► Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky… (more)

▼ Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible. Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy. The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived. Advisors/Committee Members: Dr. Farrokh Ayazi (Committee Chair), Dr. Deepak Divan (Committee Member), Dr. Joy Laskar (Committee Member), Dr. Kevin Kornegay (Committee Member), Dr. Olivier Pierron (Committee Member).

Subjects/Keywords: Phase-noise modeling; Phase-noise; Oscillator; VCO; Micromechanical oscillator; Capacitance cancellation; Negative capacitance; Negative impedance converter; Temperature compensation; Linear CMOS voltage to current converter; Piezoelectric resonator; Capacitive resonator; Tuning enhancement; TIA; Transimpedance amplifier; MEMS; Frequency tuning; Oscillators, Electric; Oscillators, Crystal; Radio frequency oscillators; Microelectromechanical systems; Oscillators, Audio-frequency Noise

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APA (6^th Edition):

Miri Lavasani, S. H. (2010). Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41096

Chicago Manual of Style (16^th Edition):

Miri Lavasani, Seyed Hossein. “Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators.” 2010. Doctoral Dissertation, Georgia Tech. Accessed April 22, 2018. http://hdl.handle.net/1853/41096.

MLA Handbook (7^th Edition):

Miri Lavasani, Seyed Hossein. “Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators.” 2010. Web. 22 Apr 2018.

Vancouver:

Miri Lavasani SH. Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2018 Apr 22]. Available from: http://hdl.handle.net/1853/41096.

Council of Science Editors:

Miri Lavasani SH. Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/41096

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