Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(CML Buffer). Showing records 1 – 2 of 2 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


California State University – Sacramento

1. Penmetsa, Sruthi. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2016, California State University – Sacramento

A phase-locked loop (PLL) is an important mixed-signal circuit that is used on almost every integrated circuit. A frequency divider is needed in the PLL loop to allow the use of a low frequency reference clock that is typically provided by a highly accurate off-chip crystal oscillator. This project is focused on the design of a current-mode logic (CML) frequency divider in 0.18um CMOS for an all digital phase-locked loop. Current-mode logic is used for the first few stages of the overall frequency divider, where the frequency of operation is too high for standard CMOS logic to operate properly. For this project, a CML frequency divider was designed in 0.18um CMOS and simulations were performed to verify performance for typical as well as worst case conditions. Advisors/Committee Members: Heedley, Perry.

Subjects/Keywords: CML; CML Buffer; Current-mode logic; All-digital phase-locked loop; Design of CML toggle flip-flop; CML to CMOS converter

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Penmetsa, S. (2016). A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/182788

Chicago Manual of Style (16th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Masters Thesis, California State University – Sacramento. Accessed January 23, 2017. http://hdl.handle.net/10211.3/182788.

MLA Handbook (7th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Web. 23 Jan 2017.

Vancouver:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2016. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/10211.3/182788.

Council of Science Editors:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2016. Available from: http://hdl.handle.net/10211.3/182788

2. Zimmermann, Jonathan Thomas. Frequency Constraints on D.C. Biasing in Deep Submicron Technologies.

Degree: MS, Electrical Engineering, 2015, Rochester Institute of Technology

The progression of technology has required smaller devices to achieve faster circuits and more power-efficient systems. However, with supply voltage and device intrinsic gain decreasing, device biasing in deep sub-micron technologies can be challenging. A low-voltage current source is analyzed in a 28 nm CMOS, 0.85 V supply, technology to take into account undesirable effects introduced by aggressively scaled technologies. The analysis includes intrinsic gain degradation as well as short-channel effects to create a more accurate design methodology. Amplifier design challenges in deep sub-micron technologies are discussed along with a DAC bias correction technique. Frequency dependence of output resistance for a simple and a proposed current source is presented. For the proposed current source the frequency dependence of output resistance was found to be dictated by the frequency response of the amplifier. To demonstrate the relevance of current source resistance bandwidth a common-mode logic circuit is considered, and fabrication plans are discussed along with future work. Advisors/Committee Members: P. R. Mukund, James Moon, Jing Zhang.

Subjects/Keywords: 28nm; Biasing; CML buffer; Current source; Frequency response; Submicron

…comparison of derived and simplified expressions. . . . . . . . . . . . . 26 CML buffer with… …representative current source. . . . . . . . 27 3.7 CML buffer with split equivalent current source… …46 4.11 Comparison of simple and designed biasing on CML buffer CMRR. (tttt corner… …source and the impact it has on key CML buffer properties. The second chapter provides a… …GHz CML buffer. The analysis of the CML circuit performance specifically focuses on… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zimmermann, J. T. (2015). Frequency Constraints on D.C. Biasing in Deep Submicron Technologies. (Masters Thesis). Rochester Institute of Technology. Retrieved from http://scholarworks.rit.edu/theses/8636

Chicago Manual of Style (16th Edition):

Zimmermann, Jonathan Thomas. “Frequency Constraints on D.C. Biasing in Deep Submicron Technologies.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed January 23, 2017. http://scholarworks.rit.edu/theses/8636.

MLA Handbook (7th Edition):

Zimmermann, Jonathan Thomas. “Frequency Constraints on D.C. Biasing in Deep Submicron Technologies.” 2015. Web. 23 Jan 2017.

Vancouver:

Zimmermann JT. Frequency Constraints on D.C. Biasing in Deep Submicron Technologies. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2017 Jan 23]. Available from: http://scholarworks.rit.edu/theses/8636.

Council of Science Editors:

Zimmermann JT. Frequency Constraints on D.C. Biasing in Deep Submicron Technologies. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: http://scholarworks.rit.edu/theses/8636

.