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You searched for subject:(CGRA). Showing records 1 – 20 of 20 total matches.

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1. Inagaki, Yoshikazu. Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators : 分散メモリアレイアクセラレータ向け3次元ステンシルライブラリの性能評価; ブンサン メモリアレイ アクセラレータ ムケ 3ジゲン ステンシル ライブラリ ノ セイノウ ヒョウカ.

Degree: 博士(工学), Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: CGRA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Inagaki, Y. (n.d.). Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators : 分散メモリアレイアクセラレータ向け3次元ステンシルライブラリの性能評価; ブンサン メモリアレイ アクセラレータ ムケ 3ジゲン ステンシル ライブラリ ノ セイノウ ヒョウカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/10450

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Inagaki, Yoshikazu. “Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators : 分散メモリアレイアクセラレータ向け3次元ステンシルライブラリの性能評価; ブンサン メモリアレイ アクセラレータ ムケ 3ジゲン ステンシル ライブラリ ノ セイノウ ヒョウカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed August 13, 2020. http://hdl.handle.net/10061/10450.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Inagaki, Yoshikazu. “Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators : 分散メモリアレイアクセラレータ向け3次元ステンシルライブラリの性能評価; ブンサン メモリアレイ アクセラレータ ムケ 3ジゲン ステンシル ライブラリ ノ セイノウ ヒョウカ.” Web. 13 Aug 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Inagaki Y. Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators : 分散メモリアレイアクセラレータ向け3次元ステンシルライブラリの性能評価; ブンサン メモリアレイ アクセラレータ ムケ 3ジゲン ステンシル ライブラリ ノ セイノウ ヒョウカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10061/10450.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Inagaki Y. Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators : 分散メモリアレイアクセラレータ向け3次元ステンシルライブラリの性能評価; ブンサン メモリアレイ アクセラレータ ムケ 3ジゲン ステンシル ライブラリ ノ セイノウ ヒョウカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/10450

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

2. 山野, 龍佑. マルチスレッド化によるシストリックリングアクセラレータの面積削減手法 : Area Reduction Method of systolic ring Accelerator by multithreading; マルチスレッドカ ニ ヨル シストリックリング アクセラレータ ノ メンセキ サクゲン シュホウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: CGRA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

山野, . (n.d.). マルチスレッド化によるシストリックリングアクセラレータの面積削減手法 : Area Reduction Method of systolic ring Accelerator by multithreading; マルチスレッドカ ニ ヨル シストリックリング アクセラレータ ノ メンセキ サクゲン シュホウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/12469

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

山野, 龍佑. “マルチスレッド化によるシストリックリングアクセラレータの面積削減手法 : Area Reduction Method of systolic ring Accelerator by multithreading; マルチスレッドカ ニ ヨル シストリックリング アクセラレータ ノ メンセキ サクゲン シュホウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed August 13, 2020. http://hdl.handle.net/10061/12469.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

山野, 龍佑. “マルチスレッド化によるシストリックリングアクセラレータの面積削減手法 : Area Reduction Method of systolic ring Accelerator by multithreading; マルチスレッドカ ニ ヨル シストリックリング アクセラレータ ノ メンセキ サクゲン シュホウ.” Web. 13 Aug 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

山野 . マルチスレッド化によるシストリックリングアクセラレータの面積削減手法 : Area Reduction Method of systolic ring Accelerator by multithreading; マルチスレッドカ ニ ヨル シストリックリング アクセラレータ ノ メンセキ サクゲン シュホウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10061/12469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

山野 . マルチスレッド化によるシストリックリングアクセラレータの面積削減手法 : Area Reduction Method of systolic ring Accelerator by multithreading; マルチスレッドカ ニ ヨル シストリックリング アクセラレータ ノ メンセキ サクゲン シュホウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/12469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


University of Toronto

3. Chin, Stephen. Architectures and Tools for Efficient Reconfigurable Computing.

Degree: PhD, 2018, University of Toronto

 Recent decades have seen large growth in the silicon industry with transistor scaling and transistor count approximately doubling every two years. With the continued growth… (more)

Subjects/Keywords: CGRA; FPGA; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chin, S. (2018). Architectures and Tools for Efficient Reconfigurable Computing. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/91881

Chicago Manual of Style (16th Edition):

Chin, Stephen. “Architectures and Tools for Efficient Reconfigurable Computing.” 2018. Doctoral Dissertation, University of Toronto. Accessed August 13, 2020. http://hdl.handle.net/1807/91881.

MLA Handbook (7th Edition):

Chin, Stephen. “Architectures and Tools for Efficient Reconfigurable Computing.” 2018. Web. 13 Aug 2020.

Vancouver:

Chin S. Architectures and Tools for Efficient Reconfigurable Computing. [Internet] [Doctoral dissertation]. University of Toronto; 2018. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/1807/91881.

Council of Science Editors:

Chin S. Architectures and Tools for Efficient Reconfigurable Computing. [Doctoral Dissertation]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/91881


Univerzitet u Beogradu

4. Stojilović, Mirjana, 1983-. A Method for designing domain-specific reconfigurable arrays.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

Tehničke nauke – elektrotehnika - Elektronika / Technical sciences, Electrical engineering - Electronics

Namenski računarski sistemi se najčesće projektuju tako da mogu da podrže izvršavanje… (more)

Subjects/Keywords: CGRA; datapath; domain-specific customization; flexibility; FPGA routing

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APA (6th Edition):

Stojilović, Mirjana, 1. (2016). A Method for designing domain-specific reconfigurable arrays. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Thesis, Univerzitet u Beogradu. Accessed August 13, 2020. https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Web. 13 Aug 2020.

Vancouver:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2020 Aug 13]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

5. Pager, Jared. Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems.

Degree: MS, Computer Science, 2011, Arizona State University

 Performance improvements have largely followed Moore's Law due to the help from technology scaling. In order to continue improving performance, power-efficiency must be reduced. Better… (more)

Subjects/Keywords: Computer science; Computer engineering; algorithms; CGRA; compilers; power-efficiency

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pager, J. (2011). Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/14483

Chicago Manual of Style (16th Edition):

Pager, Jared. “Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems.” 2011. Masters Thesis, Arizona State University. Accessed August 13, 2020. http://repository.asu.edu/items/14483.

MLA Handbook (7th Edition):

Pager, Jared. “Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems.” 2011. Web. 13 Aug 2020.

Vancouver:

Pager J. Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems. [Internet] [Masters thesis]. Arizona State University; 2011. [cited 2020 Aug 13]. Available from: http://repository.asu.edu/items/14483.

Council of Science Editors:

Pager J. Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems. [Masters Thesis]. Arizona State University; 2011. Available from: http://repository.asu.edu/items/14483


Arizona State University

6. Jeyapaul, Reiley. Smart Compilers for Reliable and Power-efficient Embedded Computing.

Degree: PhD, Computer Science, 2012, Arizona State University

 Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use… (more)

Subjects/Keywords: Computer science; cgra; compiler; computer architecture; power efficiency; reliability; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jeyapaul, R. (2012). Smart Compilers for Reliable and Power-efficient Embedded Computing. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/14766

Chicago Manual of Style (16th Edition):

Jeyapaul, Reiley. “Smart Compilers for Reliable and Power-efficient Embedded Computing.” 2012. Doctoral Dissertation, Arizona State University. Accessed August 13, 2020. http://repository.asu.edu/items/14766.

MLA Handbook (7th Edition):

Jeyapaul, Reiley. “Smart Compilers for Reliable and Power-efficient Embedded Computing.” 2012. Web. 13 Aug 2020.

Vancouver:

Jeyapaul R. Smart Compilers for Reliable and Power-efficient Embedded Computing. [Internet] [Doctoral dissertation]. Arizona State University; 2012. [cited 2020 Aug 13]. Available from: http://repository.asu.edu/items/14766.

Council of Science Editors:

Jeyapaul R. Smart Compilers for Reliable and Power-efficient Embedded Computing. [Doctoral Dissertation]. Arizona State University; 2012. Available from: http://repository.asu.edu/items/14766


University of North Texas

7. Ambekar, Kiran. Improving the Gameplay Experience and Guiding Bottom Players in an Interactive Mapping Game.

Degree: 2017, University of North Texas

 In game based learning, motivating the players to learn by providing them a desirable gameplay experience is extremely important. However, it's not an easy task… (more)

Subjects/Keywords: CGRA; Mapping; Benchmarks; Qualitative Comparative Analysis; Clustering; Gameplay Experience

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APA (6th Edition):

Ambekar, K. (2017). Improving the Gameplay Experience and Guiding Bottom Players in an Interactive Mapping Game. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc984203/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ambekar, Kiran. “Improving the Gameplay Experience and Guiding Bottom Players in an Interactive Mapping Game.” 2017. Thesis, University of North Texas. Accessed August 13, 2020. https://digital.library.unt.edu/ark:/67531/metadc984203/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ambekar, Kiran. “Improving the Gameplay Experience and Guiding Bottom Players in an Interactive Mapping Game.” 2017. Web. 13 Aug 2020.

Vancouver:

Ambekar K. Improving the Gameplay Experience and Guiding Bottom Players in an Interactive Mapping Game. [Internet] [Thesis]. University of North Texas; 2017. [cited 2020 Aug 13]. Available from: https://digital.library.unt.edu/ark:/67531/metadc984203/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ambekar K. Improving the Gameplay Experience and Guiding Bottom Players in an Interactive Mapping Game. [Thesis]. University of North Texas; 2017. Available from: https://digital.library.unt.edu/ark:/67531/metadc984203/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

8. Sistla, Anil Kumar. Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing.

Degree: 2014, University of North Texas

 CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced… (more)

Subjects/Keywords: ASIC; FPGA; CGRA; Computer architecture.; Integrated circuits  – Design and construction.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sistla, A. K. (2014). Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc699959/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sistla, Anil Kumar. “Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing.” 2014. Thesis, University of North Texas. Accessed August 13, 2020. https://digital.library.unt.edu/ark:/67531/metadc699959/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sistla, Anil Kumar. “Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing.” 2014. Web. 13 Aug 2020.

Vancouver:

Sistla AK. Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing. [Internet] [Thesis]. University of North Texas; 2014. [cited 2020 Aug 13]. Available from: https://digital.library.unt.edu/ark:/67531/metadc699959/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sistla AK. Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc699959/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

9. Kong, Weijiang. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture.

Degree: Electrical Engineering and Computer Science (EECS), 2019, KTH

Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most… (more)

Subjects/Keywords: LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kong, W. (2019). Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-268761

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kong, Weijiang. “Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture.” 2019. Thesis, KTH. Accessed August 13, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-268761.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kong, Weijiang. “Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture.” 2019. Web. 13 Aug 2020.

Vancouver:

Kong W. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture. [Internet] [Thesis]. KTH; 2019. [cited 2020 Aug 13]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-268761.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kong W. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture. [Thesis]. KTH; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-268761

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

10. Zhou, Peipei. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).

Degree: Electrical Engineering, 2014, UCLA

 Future processor will not be limited by the transistor resources, but will be mainly constrained by energy efficiency. Reconfigurable architecture offers higher energy efficiency than… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Computer science; CGRA; composable architecture; computer architecture; full pipeline; reconfigurable architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, P. (2014). A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9446s3nx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Thesis, UCLA. Accessed August 13, 2020. http://www.escholarship.org/uc/item/9446s3nx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Web. 13 Aug 2020.

Vancouver:

Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Internet] [Thesis]. UCLA; 2014. [cited 2020 Aug 13]. Available from: http://www.escholarship.org/uc/item/9446s3nx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9446s3nx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. DISSANAYAKA MUDIYANSELAGE EMIL MANUPA KARUNARATNE. LOW-POWER COMPILER CONTROLLED PROGRAMMABLE ACCELERATORS FOR NEXT GENERATION WEARABLES.

Degree: 2020, National University of Singapore

Subjects/Keywords: CGRA; Reconfigurable Accelerator; Compiler; Low Power

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APA (6th Edition):

KARUNARATNE, D. M. E. M. (2020). LOW-POWER COMPILER CONTROLLED PROGRAMMABLE ACCELERATORS FOR NEXT GENERATION WEARABLES. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/168792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

KARUNARATNE, DISSANAYAKA MUDIYANSELAGE EMIL MANUPA. “LOW-POWER COMPILER CONTROLLED PROGRAMMABLE ACCELERATORS FOR NEXT GENERATION WEARABLES.” 2020. Thesis, National University of Singapore. Accessed August 13, 2020. https://scholarbank.nus.edu.sg/handle/10635/168792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

KARUNARATNE, DISSANAYAKA MUDIYANSELAGE EMIL MANUPA. “LOW-POWER COMPILER CONTROLLED PROGRAMMABLE ACCELERATORS FOR NEXT GENERATION WEARABLES.” 2020. Web. 13 Aug 2020.

Vancouver:

KARUNARATNE DMEM. LOW-POWER COMPILER CONTROLLED PROGRAMMABLE ACCELERATORS FOR NEXT GENERATION WEARABLES. [Internet] [Thesis]. National University of Singapore; 2020. [cited 2020 Aug 13]. Available from: https://scholarbank.nus.edu.sg/handle/10635/168792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

KARUNARATNE DMEM. LOW-POWER COMPILER CONTROLLED PROGRAMMABLE ACCELERATORS FOR NEXT GENERATION WEARABLES. [Thesis]. National University of Singapore; 2020. Available from: https://scholarbank.nus.edu.sg/handle/10635/168792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Liang, Cao. SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing.

Degree: PhD, 2009, Worcester Polytechnic Institute

 Data streaming applications, such as signal processing, multimedia applications, often require high computing capacity, yet also have stringent power constraints, especially in portable devices. General… (more)

Subjects/Keywords: FPGA; energy efficient; CGRA; ASIC; DSP; stream processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liang, C. (2009). SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing. (Doctoral Dissertation). Worcester Polytechnic Institute. Retrieved from etd-050409-211145 ; https://digitalcommons.wpi.edu/etd-dissertations/263

Chicago Manual of Style (16th Edition):

Liang, Cao. “SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing.” 2009. Doctoral Dissertation, Worcester Polytechnic Institute. Accessed August 13, 2020. etd-050409-211145 ; https://digitalcommons.wpi.edu/etd-dissertations/263.

MLA Handbook (7th Edition):

Liang, Cao. “SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing.” 2009. Web. 13 Aug 2020.

Vancouver:

Liang C. SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing. [Internet] [Doctoral dissertation]. Worcester Polytechnic Institute; 2009. [cited 2020 Aug 13]. Available from: etd-050409-211145 ; https://digitalcommons.wpi.edu/etd-dissertations/263.

Council of Science Editors:

Liang C. SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing. [Doctoral Dissertation]. Worcester Polytechnic Institute; 2009. Available from: etd-050409-211145 ; https://digitalcommons.wpi.edu/etd-dissertations/263

13. SALUJA, Dipal. Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective.

Degree: Computer Science, 2014, Arizona State University

 Coarse-Grained Reconfigurable Architectures (CGRA) are a promising fabric for improving the performance and power-efficiency of computing devices. CGRAs are composed of components that are well-optimized… (more)

Subjects/Keywords: Computer science; CGRA; Mapping; Register File

…LIST OF FIGURES Figure Page 1: 4 x 4 CGRA… …they are programmable. For instance, ADRES CGRA has been shown to achieve performance and… …power efficiency of 60 GOPS/W in 90 nm CMOS technology [3]. A CGRA is a collection… …iterations. Acceleration of loops, 1 \ Figure 1: A 4 x 4 CGRA. A PE consists of an ALU and… …operations from the DFG of Figure 2(a) onto the CGRA of Figure 2 (b). As we can… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SALUJA, D. (2014). Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/25844

Chicago Manual of Style (16th Edition):

SALUJA, Dipal. “Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective.” 2014. Masters Thesis, Arizona State University. Accessed August 13, 2020. http://repository.asu.edu/items/25844.

MLA Handbook (7th Edition):

SALUJA, Dipal. “Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective.” 2014. Web. 13 Aug 2020.

Vancouver:

SALUJA D. Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective. [Internet] [Masters thesis]. Arizona State University; 2014. [cited 2020 Aug 13]. Available from: http://repository.asu.edu/items/25844.

Council of Science Editors:

SALUJA D. Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective. [Masters Thesis]. Arizona State University; 2014. Available from: http://repository.asu.edu/items/25844


University of Arkansas

14. Aklah, Zeyad Tariq. A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs.

Degree: PhD, 2017, University of Arkansas

  The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through… (more)

Subjects/Keywords: Applied sciences; CGRA; FPGA; Overlay; Reconfigurable architectures; System on chip; Virtual architecture; Hardware Systems; Software Engineering

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APA (6th Edition):

Aklah, Z. T. (2017). A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1928

Chicago Manual of Style (16th Edition):

Aklah, Zeyad Tariq. “A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs.” 2017. Doctoral Dissertation, University of Arkansas. Accessed August 13, 2020. https://scholarworks.uark.edu/etd/1928.

MLA Handbook (7th Edition):

Aklah, Zeyad Tariq. “A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs.” 2017. Web. 13 Aug 2020.

Vancouver:

Aklah ZT. A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2020 Aug 13]. Available from: https://scholarworks.uark.edu/etd/1928.

Council of Science Editors:

Aklah ZT. A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1928

15. Liu, Xiaobin. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.

Degree: University of Massachusetts

  With the rapid growth in consumer electronics, people expect thin, smart and powerful devices, e.g. Google Glass and other wearable devices. However, as portable… (more)

Subjects/Keywords: CGRA; MRAM; time-scheduled interconnect; Computer and Systems Architecture; Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, X. (n.d.). ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/159

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Xiaobin. “ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.” Thesis, University of Massachusetts. Accessed August 13, 2020. https://scholarworks.umass.edu/masters_theses_2/159.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Xiaobin. “ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.” Web. 13 Aug 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Liu X. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. [Internet] [Thesis]. University of Massachusetts; [cited 2020 Aug 13]. Available from: https://scholarworks.umass.edu/masters_theses_2/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Liu X. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. [Thesis]. University of Massachusetts; Available from: https://scholarworks.umass.edu/masters_theses_2/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Kyoto University / 京都大学

16. 今川, 隆司. ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法.

Degree: 博士(情報学), 2015, Kyoto University / 京都大学

新制・課程博士

甲第19136号

情博第582号

Subjects/Keywords: CGRA; 信頼性; 設計空間探索; 空間多重化; 時間多重化

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

今川, . (2015). ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/199460 ; http://dx.doi.org/10.14989/doctor.k19136

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

今川, 隆司. “ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法.” 2015. Thesis, Kyoto University / 京都大学. Accessed August 13, 2020. http://hdl.handle.net/2433/199460 ; http://dx.doi.org/10.14989/doctor.k19136.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

今川, 隆司. “ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法.” 2015. Web. 13 Aug 2020.

Vancouver:

今川 . ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法. [Internet] [Thesis]. Kyoto University / 京都大学; 2015. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/2433/199460 ; http://dx.doi.org/10.14989/doctor.k19136.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

今川 . ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法. [Thesis]. Kyoto University / 京都大学; 2015. Available from: http://hdl.handle.net/2433/199460 ; http://dx.doi.org/10.14989/doctor.k19136

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. 今川, 隆司. ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法 .

Degree: 2015, Kyoto University

Subjects/Keywords: CGRA; 信頼性; 設計空間探索; 空間多重化; 時間多重化

Page 1 Page 2 Page 3

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

今川, . (2015). ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法 . (Thesis). Kyoto University. Retrieved from http://hdl.handle.net/2433/199460

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

今川, 隆司. “ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法 .” 2015. Thesis, Kyoto University. Accessed August 13, 2020. http://hdl.handle.net/2433/199460.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

今川, 隆司. “ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法 .” 2015. Web. 13 Aug 2020.

Vancouver:

今川 . ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法 . [Internet] [Thesis]. Kyoto University; 2015. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/2433/199460.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

今川 . ソフトエラー耐性を考慮した粗粒度再構成可能アーキテクチャの設計手法 . [Thesis]. Kyoto University; 2015. Available from: http://hdl.handle.net/2433/199460

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Dogan, Rabia. System Level Exploration of RRAM for SRAM Replacement.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of… (more)

Subjects/Keywords: Resistive RAM(RRAM); Static RAM (SRAM); Non-volatile memory(NVM); Coarse Grained Reconfigurable Array (CGRA)

…state BL Bit line WL Word line VLIW Very long instruction word CGRA Coarse Grained… …of VLIW and CGRA approaches while arbitrating their drawbacks is proposed in [2]… …Reconfigurable Array (CGRA) in the following sections. 4.1 Related Work Flash based… …solutions are more flexible but cannot provide required speed and efficiency. A CGRA is a good… 

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APA (6th Edition):

Dogan, R. (2013). System Level Exploration of RRAM for SRAM Replacement. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dogan, Rabia. “System Level Exploration of RRAM for SRAM Replacement.” 2013. Thesis, Linköping UniversityLinköping University. Accessed August 13, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dogan, Rabia. “System Level Exploration of RRAM for SRAM Replacement.” 2013. Web. 13 Aug 2020.

Vancouver:

Dogan R. System Level Exploration of RRAM for SRAM Replacement. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Aug 13]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dogan R. System Level Exploration of RRAM for SRAM Replacement. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Desai, Digant. Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator.

Degree: MS, Electrical Engineering, 2013, Arizona State University

 With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to… (more)

Subjects/Keywords: Engineering; Electrical engineering; Computer engineering; CGRA framework; Multicore Processor; Power Management; Task Power Profiler

…10.1 Programming CGRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2… …vs CGRA . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11 CONCLUSION… …48 9.2 Specifications of PE op-code and multiplexer selection in CGRA Model . . . . 49… …46 9.2 Architecture overview of CGRA . . . . . . . . . . . . . . . . . . . . . . . . . 48… …9.3 CGRA Hardware-Software Stack . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.4… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Desai, D. (2013). Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/18116

Chicago Manual of Style (16th Edition):

Desai, Digant. “Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator.” 2013. Masters Thesis, Arizona State University. Accessed August 13, 2020. http://repository.asu.edu/items/18116.

MLA Handbook (7th Edition):

Desai, Digant. “Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator.” 2013. Web. 13 Aug 2020.

Vancouver:

Desai D. Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator. [Internet] [Masters thesis]. Arizona State University; 2013. [cited 2020 Aug 13]. Available from: http://repository.asu.edu/items/18116.

Council of Science Editors:

Desai D. Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator. [Masters Thesis]. Arizona State University; 2013. Available from: http://repository.asu.edu/items/18116


University of Florida

20. Coole, James Roderick. FPGA Overlays and Runtime Synthesis for Flexibility and Productivity.

Degree: PhD, Electrical and Computer Engineering, 2016, University of Florida

Subjects/Keywords: abstraction; bpr; cgra; clank; compiler; context; dynamic; fabric; fpga; hls; macroblock; opencl; optimization; overlay; rapid; runtime; speedup; synthesis; virtualization; vpr

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Coole, J. R. (2016). FPGA Overlays and Runtime Synthesis for Flexibility and Productivity. (Doctoral Dissertation). University of Florida. Retrieved from https://ufdc.ufl.edu/UFE0049926

Chicago Manual of Style (16th Edition):

Coole, James Roderick. “FPGA Overlays and Runtime Synthesis for Flexibility and Productivity.” 2016. Doctoral Dissertation, University of Florida. Accessed August 13, 2020. https://ufdc.ufl.edu/UFE0049926.

MLA Handbook (7th Edition):

Coole, James Roderick. “FPGA Overlays and Runtime Synthesis for Flexibility and Productivity.” 2016. Web. 13 Aug 2020.

Vancouver:

Coole JR. FPGA Overlays and Runtime Synthesis for Flexibility and Productivity. [Internet] [Doctoral dissertation]. University of Florida; 2016. [cited 2020 Aug 13]. Available from: https://ufdc.ufl.edu/UFE0049926.

Council of Science Editors:

Coole JR. FPGA Overlays and Runtime Synthesis for Flexibility and Productivity. [Doctoral Dissertation]. University of Florida; 2016. Available from: https://ufdc.ufl.edu/UFE0049926

.