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You searched for subject:(Built in test). Showing records 1 – 30 of 57 total matches.

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1. Sakthivel P. Certain investigations on low Transition test pattern generator Architecture for built in self test BIST;.

Degree: Certain investigations on low Transition test pattern generator Architecture for built in self test BIST, 2015, Anna University

With the advancement in digital VLSI circuit design power newlinedissipation has become a critical concern in recent years driven by the newlineemergence of portable devices… (more)

Subjects/Keywords: Bipartite Technique; Built in self test

Page 1

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APA (6th Edition):

P, S. (2015). Certain investigations on low Transition test pattern generator Architecture for built in self test BIST;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/37827

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Sakthivel. “Certain investigations on low Transition test pattern generator Architecture for built in self test BIST;.” 2015. Thesis, Anna University. Accessed September 16, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/37827.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Sakthivel. “Certain investigations on low Transition test pattern generator Architecture for built in self test BIST;.” 2015. Web. 16 Sep 2019.

Vancouver:

P S. Certain investigations on low Transition test pattern generator Architecture for built in self test BIST;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Sep 16]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/37827.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P S. Certain investigations on low Transition test pattern generator Architecture for built in self test BIST;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/37827

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

2. Gharaibeh, Ammar. A Behavioral Model of a Built-in Current Sensor for IDDQ Testing.

Degree: 2010, Texas A&M University

 IDDQ testing is one of the most effective methods for detecting defects in integrated circuits. Higher leakage currents in more advanced semiconductor technologies have reduced… (more)

Subjects/Keywords: Built-in Current Sensor; Behavioral Model; IDDQ Test

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APA (6th Edition):

Gharaibeh, A. (2010). A Behavioral Model of a Built-in Current Sensor for IDDQ Testing. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7097

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gharaibeh, Ammar. “A Behavioral Model of a Built-in Current Sensor for IDDQ Testing.” 2010. Thesis, Texas A&M University. Accessed September 16, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7097.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gharaibeh, Ammar. “A Behavioral Model of a Built-in Current Sensor for IDDQ Testing.” 2010. Web. 16 Sep 2019.

Vancouver:

Gharaibeh A. A Behavioral Model of a Built-in Current Sensor for IDDQ Testing. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7097.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gharaibeh A. A Behavioral Model of a Built-in Current Sensor for IDDQ Testing. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7097

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Nakamura, Yoshiyuki. Studies on defect level and diagnosis for built-in self test architecture : 組み込み自己テスト方式における不良率および故障診断に関する研究; クミコミ ジコ テスト ホウシキ ニヨル フリョウリツ オヨビ コショウ シンダン ニ カンスル ケンキュウ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: built-in self test

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APA (6th Edition):

Nakamura, Y. (n.d.). Studies on defect level and diagnosis for built-in self test architecture : 組み込み自己テスト方式における不良率および故障診断に関する研究; クミコミ ジコ テスト ホウシキ ニヨル フリョウリツ オヨビ コショウ シンダン ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/2903

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nakamura, Yoshiyuki. “Studies on defect level and diagnosis for built-in self test architecture : 組み込み自己テスト方式における不良率および故障診断に関する研究; クミコミ ジコ テスト ホウシキ ニヨル フリョウリツ オヨビ コショウ シンダン ニ カンスル ケンキュウ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed September 16, 2019. http://hdl.handle.net/10061/2903.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nakamura, Yoshiyuki. “Studies on defect level and diagnosis for built-in self test architecture : 組み込み自己テスト方式における不良率および故障診断に関する研究; クミコミ ジコ テスト ホウシキ ニヨル フリョウリツ オヨビ コショウ シンダン ニ カンスル ケンキュウ.” Web. 16 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nakamura Y. Studies on defect level and diagnosis for built-in self test architecture : 組み込み自己テスト方式における不良率および故障診断に関する研究; クミコミ ジコ テスト ホウシキ ニヨル フリョウリツ オヨビ コショウ シンダン ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2019 Sep 16]. Available from: http://hdl.handle.net/10061/2903.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nakamura Y. Studies on defect level and diagnosis for built-in self test architecture : 組み込み自己テスト方式における不良率および故障診断に関する研究; クミコミ ジコ テスト ホウシキ ニヨル フリョウリツ オヨビ コショウ シンダン ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/2903

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

4. 宮本, 佳治. スキャンBISTに対するLFSRシード生成の高速化 : An Acceleration of LFSR Seed Generation for Scan-Based BIST; スキャン BIST ニ タイスル LFSR シード セイセイ ノ コウソクカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Built-In Self Test (BIST)

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APA (6th Edition):

宮本, . (n.d.). スキャンBISTに対するLFSRシード生成の高速化 : An Acceleration of LFSR Seed Generation for Scan-Based BIST; スキャン BIST ニ タイスル LFSR シード セイセイ ノ コウソクカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/9447

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

宮本, 佳治. “スキャンBISTに対するLFSRシード生成の高速化 : An Acceleration of LFSR Seed Generation for Scan-Based BIST; スキャン BIST ニ タイスル LFSR シード セイセイ ノ コウソクカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed September 16, 2019. http://hdl.handle.net/10061/9447.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

宮本, 佳治. “スキャンBISTに対するLFSRシード生成の高速化 : An Acceleration of LFSR Seed Generation for Scan-Based BIST; スキャン BIST ニ タイスル LFSR シード セイセイ ノ コウソクカ.” Web. 16 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

宮本 . スキャンBISTに対するLFSRシード生成の高速化 : An Acceleration of LFSR Seed Generation for Scan-Based BIST; スキャン BIST ニ タイスル LFSR シード セイセイ ノ コウソクカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2019 Sep 16]. Available from: http://hdl.handle.net/10061/9447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

宮本 . スキャンBISTに対するLFSRシード生成の高速化 : An Acceleration of LFSR Seed Generation for Scan-Based BIST; スキャン BIST ニ タイスル LFSR シード セイセイ ノ コウソクカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/9447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Rochester Institute of Technology

5. Mohan Dass, Manikandan Sriram. Design and Verification of a Dual Port RAM Using UVM Methodology.

Degree: MS, Electrical Engineering, 2018, Rochester Institute of Technology

  Data-intensive applications such as Deep Learning, Big Data, and Computer Vision have resulted in more demand for on-chip memory storage. Hence, state of the… (more)

Subjects/Keywords: UVM; SystemVerilog; Reusability; Memory architecture; Circuit faults; Built-in self-test

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APA (6th Edition):

Mohan Dass, M. S. (2018). Design and Verification of a Dual Port RAM Using UVM Methodology. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9792

Chicago Manual of Style (16th Edition):

Mohan Dass, Manikandan Sriram. “Design and Verification of a Dual Port RAM Using UVM Methodology.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed September 16, 2019. https://scholarworks.rit.edu/theses/9792.

MLA Handbook (7th Edition):

Mohan Dass, Manikandan Sriram. “Design and Verification of a Dual Port RAM Using UVM Methodology.” 2018. Web. 16 Sep 2019.

Vancouver:

Mohan Dass MS. Design and Verification of a Dual Port RAM Using UVM Methodology. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2019 Sep 16]. Available from: https://scholarworks.rit.edu/theses/9792.

Council of Science Editors:

Mohan Dass MS. Design and Verification of a Dual Port RAM Using UVM Methodology. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9792


Université de Grenoble

6. Abdallah, Louay. Capteurs embarqués non-intrusifs pour le test des circuits RF : Non-intrusif built-in sensors for RF circuit testing.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

Cette thèse vise l’étude de techniques de type BIST pour un front-end RF, considérant des nouveaux types des capteurs intégrés très simples pour l’extraction de… (more)

Subjects/Keywords: RF; Test; Test intégré; BIST; Apprentissage automatique; BIST : Built in self test; Machine learning; DFT : Design for test

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APA (6th Edition):

Abdallah, L. (2012). Capteurs embarqués non-intrusifs pour le test des circuits RF : Non-intrusif built-in sensors for RF circuit testing. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT104

Chicago Manual of Style (16th Edition):

Abdallah, Louay. “Capteurs embarqués non-intrusifs pour le test des circuits RF : Non-intrusif built-in sensors for RF circuit testing.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed September 16, 2019. http://www.theses.fr/2012GRENT104.

MLA Handbook (7th Edition):

Abdallah, Louay. “Capteurs embarqués non-intrusifs pour le test des circuits RF : Non-intrusif built-in sensors for RF circuit testing.” 2012. Web. 16 Sep 2019.

Vancouver:

Abdallah L. Capteurs embarqués non-intrusifs pour le test des circuits RF : Non-intrusif built-in sensors for RF circuit testing. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2019 Sep 16]. Available from: http://www.theses.fr/2012GRENT104.

Council of Science Editors:

Abdallah L. Capteurs embarqués non-intrusifs pour le test des circuits RF : Non-intrusif built-in sensors for RF circuit testing. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT104

7. Renaud, Guillaume. Auto test de convertisseurs de signal de type pipeline : Pipeline ADC Built-In Self Test.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2016, Grenoble Alpes

Cette thèse vise l’étude de nouvelles architectures d’auto test pour les convertisseurs de type pipeline. En production, les convertisseurs sont testés en fonctionnement statique et… (more)

Subjects/Keywords: Convertisseur pipeline; Conception en vue du test; Auto test; Pipeline converter; Design for test; Built-In-Self-Test; 620

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APA (6th Edition):

Renaud, G. (2016). Auto test de convertisseurs de signal de type pipeline : Pipeline ADC Built-In Self Test. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2016GREAT064

Chicago Manual of Style (16th Edition):

Renaud, Guillaume. “Auto test de convertisseurs de signal de type pipeline : Pipeline ADC Built-In Self Test.” 2016. Doctoral Dissertation, Grenoble Alpes. Accessed September 16, 2019. http://www.theses.fr/2016GREAT064.

MLA Handbook (7th Edition):

Renaud, Guillaume. “Auto test de convertisseurs de signal de type pipeline : Pipeline ADC Built-In Self Test.” 2016. Web. 16 Sep 2019.

Vancouver:

Renaud G. Auto test de convertisseurs de signal de type pipeline : Pipeline ADC Built-In Self Test. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2016. [cited 2019 Sep 16]. Available from: http://www.theses.fr/2016GREAT064.

Council of Science Editors:

Renaud G. Auto test de convertisseurs de signal de type pipeline : Pipeline ADC Built-In Self Test. [Doctoral Dissertation]. Grenoble Alpes; 2016. Available from: http://www.theses.fr/2016GREAT064


University of California – San Diego

8. Kanar, Tumay. Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications.

Degree: Electrical Engineering (Electronic Circuits and Systems), 2015, University of California – San Diego

 The thesis presents wide-band built-in self-test circuits (BIST) for phased array systems and high performance circuits for millimeter-wave radiometry and low-noise applications. The 2-15 GHz… (more)

Subjects/Keywords: Electrical engineering; built-in self-test; low noise amplifiers; millimeter wave imaging; phased arrays; radiometer

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APA (6th Edition):

Kanar, T. (2015). Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/2sj4j7jg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kanar, Tumay. “Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications.” 2015. Thesis, University of California – San Diego. Accessed September 16, 2019. http://www.escholarship.org/uc/item/2sj4j7jg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kanar, Tumay. “Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications.” 2015. Web. 16 Sep 2019.

Vancouver:

Kanar T. Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications. [Internet] [Thesis]. University of California – San Diego; 2015. [cited 2019 Sep 16]. Available from: http://www.escholarship.org/uc/item/2sj4j7jg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kanar T. Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications. [Thesis]. University of California – San Diego; 2015. Available from: http://www.escholarship.org/uc/item/2sj4j7jg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. KU, CHIA-CHI. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With the shrinking of the feature size of transistors, chips become more sensible to manufacturing defects and/or external noises, which may cause low manufacturing yield.… (more)

Subjects/Keywords: yield improvement; VLSI testing; error-tolerance; built-in self-test; image enhancement

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APA (6th Edition):

KU, C. (2013). A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Thesis, NSYSU. Accessed September 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Web. 16 Sep 2019.

Vancouver:

KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Sep 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

10. Bakshi, Dhrumeel. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in… (more)

Subjects/Keywords: Satisfiability Modulo Theories (SMT); LFSR Reseeding; Logic Built-In Self Test (LBIST); Integer Linear Programming (ILP); Test-point Insertion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bakshi, D. (2012). Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35474

Chicago Manual of Style (16th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Masters Thesis, Virginia Tech. Accessed September 16, 2019. http://hdl.handle.net/10919/35474.

MLA Handbook (7th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Web. 16 Sep 2019.

Vancouver:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/10919/35474.

Council of Science Editors:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/35474


Virginia Tech

11. Rahagude, Nikhil Prakash. Integrated Enhancement of Testability and Diagnosability for Digital Circuits.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best… (more)

Subjects/Keywords: Fault Coverage; Diagnostic Resolution; Weighted Average; Test Point Insertion; Design for Testability; Design for Diagnosability; Built-in Self Test

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APA (6th Edition):

Rahagude, N. P. (2010). Integrated Enhancement of Testability and Diagnosability for Digital Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35609

Chicago Manual of Style (16th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Masters Thesis, Virginia Tech. Accessed September 16, 2019. http://hdl.handle.net/10919/35609.

MLA Handbook (7th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Web. 16 Sep 2019.

Vancouver:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/10919/35609.

Council of Science Editors:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35609

12. Rehman, Saif Ur. Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh : Development of test and diagnosis techniques for hierarchical mesh-based FPGAs.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Grenoble Alpes

L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui… (more)

Subjects/Keywords: Built-in self-test; FPGA hiérarchique de type mesh; Multilevel interconnect; Off-line test et diagnostic; Logic et interconnect BIST; Built-in self-test; Hierarchical mesh of clusters FPGA; Multilevel interconnect; Off-line test and diagnosis; Logic and interconnect BIST; 620

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APA (6th Edition):

Rehman, S. U. (2015). Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh : Development of test and diagnosis techniques for hierarchical mesh-based FPGAs. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT110

Chicago Manual of Style (16th Edition):

Rehman, Saif Ur. “Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh : Development of test and diagnosis techniques for hierarchical mesh-based FPGAs.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed September 16, 2019. http://www.theses.fr/2015GREAT110.

MLA Handbook (7th Edition):

Rehman, Saif Ur. “Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh : Development of test and diagnosis techniques for hierarchical mesh-based FPGAs.” 2015. Web. 16 Sep 2019.

Vancouver:

Rehman SU. Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh : Development of test and diagnosis techniques for hierarchical mesh-based FPGAs. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2019 Sep 16]. Available from: http://www.theses.fr/2015GREAT110.

Council of Science Editors:

Rehman SU. Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh : Development of test and diagnosis techniques for hierarchical mesh-based FPGAs. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT110


Indian Institute of Science

13. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: 2013, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA (6th Edition):

Vasudevamurthy, R. (2013). Time-based All-Digital Technique for Analog Built-in Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Thesis, Indian Institute of Science. Accessed September 16, 2019. http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Web. 16 Sep 2019.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

14. Onabajo, Marvin Olufemi. Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique.

Degree: 2009, Texas A&M University

 Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost… (more)

Subjects/Keywords: Built-in test (BIT); loopback; offset mixer; RF front-end testing; RF current injection; low-noise amplifier (LNA); integrated transceiver

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APA (6th Edition):

Onabajo, M. O. (2009). Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Onabajo, Marvin Olufemi. “Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique.” 2009. Thesis, Texas A&M University. Accessed September 16, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Onabajo, Marvin Olufemi. “Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique.” 2009. Web. 16 Sep 2019.

Vancouver:

Onabajo MO. Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Onabajo MO. Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Yan, Wenjian. A wideband frequency synthesizer for built-in self testing of analog integrated circuits.

Degree: 2004, Texas A&M University

 The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple.… (more)

Subjects/Keywords: wideband; frequency synthesizer; built-in self test; BIST; PLL

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APA (6th Edition):

Yan, W. (2004). A wideband frequency synthesizer for built-in self testing of analog integrated circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/1059

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yan, Wenjian. “A wideband frequency synthesizer for built-in self testing of analog integrated circuits.” 2004. Thesis, Texas A&M University. Accessed September 16, 2019. http://hdl.handle.net/1969.1/1059.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yan, Wenjian. “A wideband frequency synthesizer for built-in self testing of analog integrated circuits.” 2004. Web. 16 Sep 2019.

Vancouver:

Yan W. A wideband frequency synthesizer for built-in self testing of analog integrated circuits. [Internet] [Thesis]. Texas A&M University; 2004. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/1969.1/1059.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yan W. A wideband frequency synthesizer for built-in self testing of analog integrated circuits. [Thesis]. Texas A&M University; 2004. Available from: http://hdl.handle.net/1969.1/1059

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toledo

16. Gadde, Priyanka. A BIST Architecture for Testing LUTs in a Virtex-4 FPGA.

Degree: MSin Electrical Engineering, College of Engineering, 2013, University of Toledo

 Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement a given digital design. Built-In Self-Test (BIST) is a testing… (more)

Subjects/Keywords: Electrical Engineering; BIST; SRAM; Faults; Memory; Virtex-4 FPGA; Read Faults; Write Faults; Built in Self-Test

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APA (6th Edition):

Gadde, P. (2013). A BIST Architecture for Testing LUTs in a Virtex-4 FPGA. (Masters Thesis). University of Toledo. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199

Chicago Manual of Style (16th Edition):

Gadde, Priyanka. “A BIST Architecture for Testing LUTs in a Virtex-4 FPGA.” 2013. Masters Thesis, University of Toledo. Accessed September 16, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.

MLA Handbook (7th Edition):

Gadde, Priyanka. “A BIST Architecture for Testing LUTs in a Virtex-4 FPGA.” 2013. Web. 16 Sep 2019.

Vancouver:

Gadde P. A BIST Architecture for Testing LUTs in a Virtex-4 FPGA. [Internet] [Masters thesis]. University of Toledo; 2013. [cited 2019 Sep 16]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.

Council of Science Editors:

Gadde P. A BIST Architecture for Testing LUTs in a Virtex-4 FPGA. [Masters Thesis]. University of Toledo; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199


Georgia Tech

17. Bhattacharya, Soumendu. Alternate Testing of Analog and RF Systems using Extracted Test Response Features.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Testing is an integral part of modern semiconductor industry. The necessity of test is evident, especially for low-yielding processes, to ensure Quality of Service (QoS)… (more)

Subjects/Keywords: Wireless systems; Optimization; Production testing; Sensors; Built-in-test

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APA (6th Edition):

Bhattacharya, S. (2005). Alternate Testing of Analog and RF Systems using Extracted Test Response Features. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/7200

Chicago Manual of Style (16th Edition):

Bhattacharya, Soumendu. “Alternate Testing of Analog and RF Systems using Extracted Test Response Features.” 2005. Doctoral Dissertation, Georgia Tech. Accessed September 16, 2019. http://hdl.handle.net/1853/7200.

MLA Handbook (7th Edition):

Bhattacharya, Soumendu. “Alternate Testing of Analog and RF Systems using Extracted Test Response Features.” 2005. Web. 16 Sep 2019.

Vancouver:

Bhattacharya S. Alternate Testing of Analog and RF Systems using Extracted Test Response Features. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/1853/7200.

Council of Science Editors:

Bhattacharya S. Alternate Testing of Analog and RF Systems using Extracted Test Response Features. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/7200


Louisiana State University

18. Alli, Pavan K. Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods.

Degree: MS, Electrical and Computer Engineering, 2004, Louisiana State University

 This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage… (more)

Subjects/Keywords: operational amplifier; iddq; built-in current sensor; oscillation test

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APA (6th Edition):

Alli, P. K. (2004). Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods. (Masters Thesis). Louisiana State University. Retrieved from etd-05272004-164455 ; https://digitalcommons.lsu.edu/gradschool_theses/1786

Chicago Manual of Style (16th Edition):

Alli, Pavan K. “Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods.” 2004. Masters Thesis, Louisiana State University. Accessed September 16, 2019. etd-05272004-164455 ; https://digitalcommons.lsu.edu/gradschool_theses/1786.

MLA Handbook (7th Edition):

Alli, Pavan K. “Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods.” 2004. Web. 16 Sep 2019.

Vancouver:

Alli PK. Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods. [Internet] [Masters thesis]. Louisiana State University; 2004. [cited 2019 Sep 16]. Available from: etd-05272004-164455 ; https://digitalcommons.lsu.edu/gradschool_theses/1786.

Council of Science Editors:

Alli PK. Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods. [Masters Thesis]. Louisiana State University; 2004. Available from: etd-05272004-164455 ; https://digitalcommons.lsu.edu/gradschool_theses/1786

19. Eatinger, Ryan Joseph. Built-in self-test in integrated circuits - ESD event mitigation and detection.

Degree: MS, Department of Electrical Engineering, 2011, Kansas State University

 When enough charges accumulate on two objects, the air dielectric between them breaks down to create a phenomenon known as electrostatic discharge (ESD). ESD is… (more)

Subjects/Keywords: ESD; Integrated circuit; Charged device model; Built-in self test; Fuse; Human body model; Electrical Engineering (0544)

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APA (6th Edition):

Eatinger, R. J. (2011). Built-in self-test in integrated circuits - ESD event mitigation and detection. (Masters Thesis). Kansas State University. Retrieved from http://hdl.handle.net/2097/13538

Chicago Manual of Style (16th Edition):

Eatinger, Ryan Joseph. “Built-in self-test in integrated circuits - ESD event mitigation and detection.” 2011. Masters Thesis, Kansas State University. Accessed September 16, 2019. http://hdl.handle.net/2097/13538.

MLA Handbook (7th Edition):

Eatinger, Ryan Joseph. “Built-in self-test in integrated circuits - ESD event mitigation and detection.” 2011. Web. 16 Sep 2019.

Vancouver:

Eatinger RJ. Built-in self-test in integrated circuits - ESD event mitigation and detection. [Internet] [Masters thesis]. Kansas State University; 2011. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/2097/13538.

Council of Science Editors:

Eatinger RJ. Built-in self-test in integrated circuits - ESD event mitigation and detection. [Masters Thesis]. Kansas State University; 2011. Available from: http://hdl.handle.net/2097/13538


University of Western Ontario

20. McCarthy, Madison. Design, Implementation and Evaluation of a Redundancy Management System for Fault-Tolerant Wireless Devices in Harsh Environments.

Degree: 2019, University of Western Ontario

 Wireless sensor networks (WSNs), when deployed in harsh environments, can fail prematurely due to elevated rates of component failures. To counteract this problem, fault-tolerant techniques,… (more)

Subjects/Keywords: Wireless Sensor Network; Fault-Tolerant; Built-in Test; Redundancy Management System; Common-Cause Failure; Fault Coverage; Electrical and Electronics

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APA (6th Edition):

McCarthy, M. (2019). Design, Implementation and Evaluation of a Redundancy Management System for Fault-Tolerant Wireless Devices in Harsh Environments. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/6149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

McCarthy, Madison. “Design, Implementation and Evaluation of a Redundancy Management System for Fault-Tolerant Wireless Devices in Harsh Environments.” 2019. Thesis, University of Western Ontario. Accessed September 16, 2019. https://ir.lib.uwo.ca/etd/6149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

McCarthy, Madison. “Design, Implementation and Evaluation of a Redundancy Management System for Fault-Tolerant Wireless Devices in Harsh Environments.” 2019. Web. 16 Sep 2019.

Vancouver:

McCarthy M. Design, Implementation and Evaluation of a Redundancy Management System for Fault-Tolerant Wireless Devices in Harsh Environments. [Internet] [Thesis]. University of Western Ontario; 2019. [cited 2019 Sep 16]. Available from: https://ir.lib.uwo.ca/etd/6149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

McCarthy M. Design, Implementation and Evaluation of a Redundancy Management System for Fault-Tolerant Wireless Devices in Harsh Environments. [Thesis]. University of Western Ontario; 2019. Available from: https://ir.lib.uwo.ca/etd/6149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

21. Aluthwala, Pasindu. Digital Harmonic-Cancelling Sinusoidal Signal Synthesis.

Degree: Computer Science & Engineering, 2017, University of New South Wales

 Sinusoidal signal synthesizers are essential modules in a variety of electronic applications, such as communication systems, calibration and verification of analog/mixed-signal integrated circuits (ICs), and… (more)

Subjects/Keywords: digital to analog converter; on chip signal generator; harmonic cancelling; PSK modulation; built in self test

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APA (6th Edition):

Aluthwala, P. (2017). Digital Harmonic-Cancelling Sinusoidal Signal Synthesis. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Aluthwala, Pasindu. “Digital Harmonic-Cancelling Sinusoidal Signal Synthesis.” 2017. Doctoral Dissertation, University of New South Wales. Accessed September 16, 2019. http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true.

MLA Handbook (7th Edition):

Aluthwala, Pasindu. “Digital Harmonic-Cancelling Sinusoidal Signal Synthesis.” 2017. Web. 16 Sep 2019.

Vancouver:

Aluthwala P. Digital Harmonic-Cancelling Sinusoidal Signal Synthesis. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2019 Sep 16]. Available from: http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true.

Council of Science Editors:

Aluthwala P. Digital Harmonic-Cancelling Sinusoidal Signal Synthesis. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true


Northeastern University

22. Feng, Junpeng. Amplifier design for differential temperature sensors in built-in testing applications.

Degree: MS, Department of Electrical and Computer Engineering, 2013, Northeastern University

 Low-cost radio frequency (RF) communication circuits are frequently fabricated in complementary metal-oxide-semiconductor (CMOS) technology. As system-on-chip and system-in-package designs are becoming increasingly complicated, the manufacturing… (more)

Subjects/Keywords: amplifier design; Built-In Test; dynamic range; non-intrusive; Power dissipation; temperature sensor; Electrical and Computer Engineering; Electrical and Electronics; Engineering

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APA (6th Edition):

Feng, J. (2013). Amplifier design for differential temperature sensors in built-in testing applications. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20004850

Chicago Manual of Style (16th Edition):

Feng, Junpeng. “Amplifier design for differential temperature sensors in built-in testing applications.” 2013. Masters Thesis, Northeastern University. Accessed September 16, 2019. http://hdl.handle.net/2047/d20004850.

MLA Handbook (7th Edition):

Feng, Junpeng. “Amplifier design for differential temperature sensors in built-in testing applications.” 2013. Web. 16 Sep 2019.

Vancouver:

Feng J. Amplifier design for differential temperature sensors in built-in testing applications. [Internet] [Masters thesis]. Northeastern University; 2013. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/2047/d20004850.

Council of Science Editors:

Feng J. Amplifier design for differential temperature sensors in built-in testing applications. [Masters Thesis]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20004850


Arizona State University

23. Jeong, Jae Woong. Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures.

Degree: Electrical Engineering, 2015, Arizona State University

Subjects/Keywords: Electrical engineering; Built-In Self-Test; RF Transceiver

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APA (6th Edition):

Jeong, J. W. (2015). Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/36447

Chicago Manual of Style (16th Edition):

Jeong, Jae Woong. “Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures.” 2015. Doctoral Dissertation, Arizona State University. Accessed September 16, 2019. http://repository.asu.edu/items/36447.

MLA Handbook (7th Edition):

Jeong, Jae Woong. “Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures.” 2015. Web. 16 Sep 2019.

Vancouver:

Jeong JW. Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures. [Internet] [Doctoral dissertation]. Arizona State University; 2015. [cited 2019 Sep 16]. Available from: http://repository.asu.edu/items/36447.

Council of Science Editors:

Jeong JW. Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures. [Doctoral Dissertation]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/36447

24. Haj kacem, Mohamed Amine. Contribution au développement d'une méthodologie de diagnostic des systèmes Cyber-Physique : Contribution to the development of methodology for diagnosis of Cyber physical systems.

Degree: Docteur es, Automatique - productique, 2018, Grenoble Alpes

Les systèmes industriels recouvrent de nombreuses formes. Aujourd'hui, ils sont le plus souvent organisés en réseaux. Les nouvelles technologies de l'information et de la communication… (more)

Subjects/Keywords: Modélisation; Diagnostic; Systèmes cyber-Physique; Tests embarqués; Modeling; Diagnostic; Cyber physical systems; Built-In Test; 004; 620

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APA (6th Edition):

Haj kacem, M. A. (2018). Contribution au développement d'une méthodologie de diagnostic des systèmes Cyber-Physique : Contribution to the development of methodology for diagnosis of Cyber physical systems. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT119

Chicago Manual of Style (16th Edition):

Haj kacem, Mohamed Amine. “Contribution au développement d'une méthodologie de diagnostic des systèmes Cyber-Physique : Contribution to the development of methodology for diagnosis of Cyber physical systems.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed September 16, 2019. http://www.theses.fr/2018GREAT119.

MLA Handbook (7th Edition):

Haj kacem, Mohamed Amine. “Contribution au développement d'une méthodologie de diagnostic des systèmes Cyber-Physique : Contribution to the development of methodology for diagnosis of Cyber physical systems.” 2018. Web. 16 Sep 2019.

Vancouver:

Haj kacem MA. Contribution au développement d'une méthodologie de diagnostic des systèmes Cyber-Physique : Contribution to the development of methodology for diagnosis of Cyber physical systems. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2019 Sep 16]. Available from: http://www.theses.fr/2018GREAT119.

Council of Science Editors:

Haj kacem MA. Contribution au développement d'une méthodologie de diagnostic des systèmes Cyber-Physique : Contribution to the development of methodology for diagnosis of Cyber physical systems. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT119


Université de Grenoble

25. Dubois, Matthieu. Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA : Methodology for test metrics estimation built-in design flow of hard-to-simulate analog/mixed-signal circuits.

Degree: Docteur es, Sciences et technologie industrielles, 2011, Université de Grenoble

L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en… (more)

Subjects/Keywords: Métriques de test; Convertisseur sigma-delta; Circuits mixtes et analogiques; Estimation statistique; Conception en vue du test; Auto-test; Test metrics; Sigma-delta converter; Analog/mixed-signal circuit; Statistical estimation; Design-for-test; Built-In Self-Test

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APA (6th Edition):

Dubois, M. (2011). Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA : Methodology for test metrics estimation built-in design flow of hard-to-simulate analog/mixed-signal circuits. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENT033

Chicago Manual of Style (16th Edition):

Dubois, Matthieu. “Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA : Methodology for test metrics estimation built-in design flow of hard-to-simulate analog/mixed-signal circuits.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed September 16, 2019. http://www.theses.fr/2011GRENT033.

MLA Handbook (7th Edition):

Dubois, Matthieu. “Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA : Methodology for test metrics estimation built-in design flow of hard-to-simulate analog/mixed-signal circuits.” 2011. Web. 16 Sep 2019.

Vancouver:

Dubois M. Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA : Methodology for test metrics estimation built-in design flow of hard-to-simulate analog/mixed-signal circuits. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2019 Sep 16]. Available from: http://www.theses.fr/2011GRENT033.

Council of Science Editors:

Dubois M. Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA : Methodology for test metrics estimation built-in design flow of hard-to-simulate analog/mixed-signal circuits. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENT033

26. Fei, Richun. Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS : Alternative solution to improve the production test of optical sensors in CMOS technology.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Grenoble Alpes

Le test de production des imageurs CMOS est une étape clé du flot de fabrication afin de garantir des produits répondant aux critères de qualité… (more)

Subjects/Keywords: Imageur CMOS; Auto-test incorporé; Bruit spacial fixe; DFT analogique; CMOS imager; Built in self test; Fixed pattern noise; DFT analog; 620

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APA (6th Edition):

Fei, R. (2015). Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS : Alternative solution to improve the production test of optical sensors in CMOS technology. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT117

Chicago Manual of Style (16th Edition):

Fei, Richun. “Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS : Alternative solution to improve the production test of optical sensors in CMOS technology.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed September 16, 2019. http://www.theses.fr/2015GREAT117.

MLA Handbook (7th Edition):

Fei, Richun. “Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS : Alternative solution to improve the production test of optical sensors in CMOS technology.” 2015. Web. 16 Sep 2019.

Vancouver:

Fei R. Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS : Alternative solution to improve the production test of optical sensors in CMOS technology. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2019 Sep 16]. Available from: http://www.theses.fr/2015GREAT117.

Council of Science Editors:

Fei R. Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS : Alternative solution to improve the production test of optical sensors in CMOS technology. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT117


Indian Institute of Science

27. Varaprasad, B K S V L. Testing Of Analog Circuits - Built In Self Test.

Degree: 2006, Indian Institute of Science

 On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals… (more)

Subjects/Keywords: Electronic Circuits - Testing And Measurements; Analog Circuits - Testing; Analog Built-In-Self-Test; Analog Fault Diagnosis; MultiDetect; Expo Tan; MultiDiag; Analog Testing; ATPG Technique; Analog Fault Modeling; Built In Self Test (BIST); Electronic Engineering

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APA (6th Edition):

Varaprasad, B. K. S. V. L. (2006). Testing Of Analog Circuits - Built In Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varaprasad, B K S V L. “Testing Of Analog Circuits - Built In Self Test.” 2006. Thesis, Indian Institute of Science. Accessed September 16, 2019. http://hdl.handle.net/2005/434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varaprasad, B K S V L. “Testing Of Analog Circuits - Built In Self Test.” 2006. Web. 16 Sep 2019.

Vancouver:

Varaprasad BKSVL. Testing Of Analog Circuits - Built In Self Test. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/2005/434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varaprasad BKSVL. Testing Of Analog Circuits - Built In Self Test. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidad de Cantabria

28. Mozuelos García, Román. Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales).

Degree: Departamento de Tecnología Electrónica e Ingeniería de Sistemas y Automática, 2009, Universidad de Cantabria

 This thesis describes a design-for-test method for embedded mixed signal circuits. It is based on the analysis of the dynamic current consumption (IDDX), both quiescent… (more)

Subjects/Keywords: dynamic current test; built-in current sensor; design for test; mixed-signal circuit; test de corriente dinámica; sensor de corriente interno; diseño para test; circuito de señal mixta; Tecnología Electrónica; 62; 621.3

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APA (6th Edition):

Mozuelos García, R. (2009). Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales). (Thesis). Universidad de Cantabria. Retrieved from http://hdl.handle.net/10803/10708

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mozuelos García, Román. “Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales).” 2009. Thesis, Universidad de Cantabria. Accessed September 16, 2019. http://hdl.handle.net/10803/10708.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mozuelos García, Román. “Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales).” 2009. Web. 16 Sep 2019.

Vancouver:

Mozuelos García R. Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales). [Internet] [Thesis]. Universidad de Cantabria; 2009. [cited 2019 Sep 16]. Available from: http://hdl.handle.net/10803/10708.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mozuelos García R. Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales). [Thesis]. Universidad de Cantabria; 2009. Available from: http://hdl.handle.net/10803/10708

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

29. XIONG, XINGGUO. BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES.

Degree: PhD, Engineering : Computer Engineering, 2005, University of Cincinnati

 With the rapid development of MEMS (microelectromechanical system) and its increasing applications to safety-critical applications, MEMS testing and fault-tolerant MEMS design are becoming more and… (more)

Subjects/Keywords: Microelectromechanical System (MEMS); Built-in Self-test (BIST); Built-in Self-repair (BISR); Yield Analysis; Reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

XIONG, X. (2005). BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236

Chicago Manual of Style (16th Edition):

XIONG, XINGGUO. “BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed September 16, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.

MLA Handbook (7th Edition):

XIONG, XINGGUO. “BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES.” 2005. Web. 16 Sep 2019.

Vancouver:

XIONG X. BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2019 Sep 16]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.

Council of Science Editors:

XIONG X. BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236


Anna University

30. Hariharan K. Design and implementation of novel methods for testing static and dynamic errors in mixed signal circuits.

Degree: 2013, Anna University

Integrated Circuits (IC) with analog and digital functions have become increasingly prevalent in the semiconductor industry. Complex digital circuits are now commonly combined with analog… (more)

Subjects/Keywords: Novel methods; testing static and dynamic errors; mixed signal circuits; analog to digital converters; integrated circuits; built in self test; time tick BIST

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

K, H. (2013). Design and implementation of novel methods for testing static and dynamic errors in mixed signal circuits. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

K, Hariharan. “Design and implementation of novel methods for testing static and dynamic errors in mixed signal circuits.” 2013. Thesis, Anna University. Accessed September 16, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/11689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

K, Hariharan. “Design and implementation of novel methods for testing static and dynamic errors in mixed signal circuits.” 2013. Web. 16 Sep 2019.

Vancouver:

K H. Design and implementation of novel methods for testing static and dynamic errors in mixed signal circuits. [Internet] [Thesis]. Anna University; 2013. [cited 2019 Sep 16]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

K H. Design and implementation of novel methods for testing static and dynamic errors in mixed signal circuits. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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