Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Asynchronous circuits). Showing records 1 – 30 of 81 total matches.

[1] [2] [3]

Search Limiters

Last 2 Years | English Only

Levels

▼ Search Limiters


University of Utah

1. Sai, Santosh Varanasi Naga. Performance analysis of four-phase untimed asynchronous handshake protocols.

Degree: MS;, Electrical & Computer Engineering;, 2009, University of Utah

 This thesis presents the trade-offs between concurrency reduction, energy and performance across a four-phase untimed asynchronous protocol family. The formal understanding of the handshake protocols… (more)

Subjects/Keywords: Asynchronous circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sai, S. V. N. (2009). Performance analysis of four-phase untimed asynchronous handshake protocols. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873

Chicago Manual of Style (16th Edition):

Sai, Santosh Varanasi Naga. “Performance analysis of four-phase untimed asynchronous handshake protocols.” 2009. Masters Thesis, University of Utah. Accessed May 08, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873.

MLA Handbook (7th Edition):

Sai, Santosh Varanasi Naga. “Performance analysis of four-phase untimed asynchronous handshake protocols.” 2009. Web. 08 May 2021.

Vancouver:

Sai SVN. Performance analysis of four-phase untimed asynchronous handshake protocols. [Internet] [Masters thesis]. University of Utah; 2009. [cited 2021 May 08]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873.

Council of Science Editors:

Sai SVN. Performance analysis of four-phase untimed asynchronous handshake protocols. [Masters Thesis]. University of Utah; 2009. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873


Oregon State University

2. Janik, Kenneth J. A microarchitecture study of the counterflow pipeline principle.

Degree: PhD, Electrical and Computer Engineering, 1998, Oregon State University

 The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture… (more)

Subjects/Keywords: Asynchronous circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janik, K. J. (1998). A microarchitecture study of the counterflow pipeline principle. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/33905

Chicago Manual of Style (16th Edition):

Janik, Kenneth J. “A microarchitecture study of the counterflow pipeline principle.” 1998. Doctoral Dissertation, Oregon State University. Accessed May 08, 2021. http://hdl.handle.net/1957/33905.

MLA Handbook (7th Edition):

Janik, Kenneth J. “A microarchitecture study of the counterflow pipeline principle.” 1998. Web. 08 May 2021.

Vancouver:

Janik KJ. A microarchitecture study of the counterflow pipeline principle. [Internet] [Doctoral dissertation]. Oregon State University; 1998. [cited 2021 May 08]. Available from: http://hdl.handle.net/1957/33905.

Council of Science Editors:

Janik KJ. A microarchitecture study of the counterflow pipeline principle. [Doctoral Dissertation]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33905


Oregon State University

3. Chang, Chih-ming, 1964-. Performance modeling and analysis of asynchronous pipelines for designers.

Degree: PhD, Electrical and Computer Engineering, 1997, Oregon State University

 Better performance has been one of the main motivations behind the recent resurgence of interest in asynchronous circuits (no matter whether this is always true… (more)

Subjects/Keywords: Asynchronous circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, Chih-ming, 1. (1997). Performance modeling and analysis of asynchronous pipelines for designers. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/34214

Chicago Manual of Style (16th Edition):

Chang, Chih-ming, 1964-. “Performance modeling and analysis of asynchronous pipelines for designers.” 1997. Doctoral Dissertation, Oregon State University. Accessed May 08, 2021. http://hdl.handle.net/1957/34214.

MLA Handbook (7th Edition):

Chang, Chih-ming, 1964-. “Performance modeling and analysis of asynchronous pipelines for designers.” 1997. Web. 08 May 2021.

Vancouver:

Chang, Chih-ming 1. Performance modeling and analysis of asynchronous pipelines for designers. [Internet] [Doctoral dissertation]. Oregon State University; 1997. [cited 2021 May 08]. Available from: http://hdl.handle.net/1957/34214.

Council of Science Editors:

Chang, Chih-ming 1. Performance modeling and analysis of asynchronous pipelines for designers. [Doctoral Dissertation]. Oregon State University; 1997. Available from: http://hdl.handle.net/1957/34214


University of Utah

4. Xu, Yang. Algorithms for automatic generation of relative timing constraints.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

Asynchronous circuits exhibit impressive power and performance benefits over its synchronous counterpart. Asynchronous system design, however, is not widely adopted due to the fact that… (more)

Subjects/Keywords: Asynchronous circuits; Formal verification; Relative timing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, Y. (2011). Algorithms for automatic generation of relative timing constraints. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/197/rec/177

Chicago Manual of Style (16th Edition):

Xu, Yang. “Algorithms for automatic generation of relative timing constraints.” 2011. Doctoral Dissertation, University of Utah. Accessed May 08, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/197/rec/177.

MLA Handbook (7th Edition):

Xu, Yang. “Algorithms for automatic generation of relative timing constraints.” 2011. Web. 08 May 2021.

Vancouver:

Xu Y. Algorithms for automatic generation of relative timing constraints. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 May 08]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/197/rec/177.

Council of Science Editors:

Xu Y. Algorithms for automatic generation of relative timing constraints. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/197/rec/177


Cornell University

5. Ortega Otero, Carlos. Static Power Reduction Techniques For Asynchronous Circuits.

Degree: M.S., Electrical Engineering, Electrical Engineering, 2012, Cornell University

 Power gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two… (more)

Subjects/Keywords: Asynchronous; static power; vlsi; Integrated Circuits; leakage

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ortega Otero, C. (2012). Static Power Reduction Techniques For Asynchronous Circuits. (Masters Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/31005

Chicago Manual of Style (16th Edition):

Ortega Otero, Carlos. “Static Power Reduction Techniques For Asynchronous Circuits.” 2012. Masters Thesis, Cornell University. Accessed May 08, 2021. http://hdl.handle.net/1813/31005.

MLA Handbook (7th Edition):

Ortega Otero, Carlos. “Static Power Reduction Techniques For Asynchronous Circuits.” 2012. Web. 08 May 2021.

Vancouver:

Ortega Otero C. Static Power Reduction Techniques For Asynchronous Circuits. [Internet] [Masters thesis]. Cornell University; 2012. [cited 2021 May 08]. Available from: http://hdl.handle.net/1813/31005.

Council of Science Editors:

Ortega Otero C. Static Power Reduction Techniques For Asynchronous Circuits. [Masters Thesis]. Cornell University; 2012. Available from: http://hdl.handle.net/1813/31005


Oregon State University

6. Chew, Oonpin. Failure analysis of Muller-C-element.

Degree: MS, Electrical and Computer Engineering, 1996, Oregon State University

Asynchronous circuits have recently been a breakthrough in many high performance computers. The concept of asynchronous circuits which started a long time ago has slowly… (more)

Subjects/Keywords: Asynchronous circuits  – Evaluation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chew, O. (1996). Failure analysis of Muller-C-element. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34314

Chicago Manual of Style (16th Edition):

Chew, Oonpin. “Failure analysis of Muller-C-element.” 1996. Masters Thesis, Oregon State University. Accessed May 08, 2021. http://hdl.handle.net/1957/34314.

MLA Handbook (7th Edition):

Chew, Oonpin. “Failure analysis of Muller-C-element.” 1996. Web. 08 May 2021.

Vancouver:

Chew O. Failure analysis of Muller-C-element. [Internet] [Masters thesis]. Oregon State University; 1996. [cited 2021 May 08]. Available from: http://hdl.handle.net/1957/34314.

Council of Science Editors:

Chew O. Failure analysis of Muller-C-element. [Masters Thesis]. Oregon State University; 1996. Available from: http://hdl.handle.net/1957/34314


University of New South Wales

7. Nagalla, Radhakrishna. Synthesis of asynchronous circuits from signal transition graph specifications.

Degree: Computer Science & Engineering, 1997, University of New South Wales

Subjects/Keywords: Computer circuits; Asynchronous circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nagalla, R. (1997). Synthesis of asynchronous circuits from signal transition graph specifications. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/55496 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:37860/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Nagalla, Radhakrishna. “Synthesis of asynchronous circuits from signal transition graph specifications.” 1997. Doctoral Dissertation, University of New South Wales. Accessed May 08, 2021. http://handle.unsw.edu.au/1959.4/55496 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:37860/SOURCE01?view=true.

MLA Handbook (7th Edition):

Nagalla, Radhakrishna. “Synthesis of asynchronous circuits from signal transition graph specifications.” 1997. Web. 08 May 2021.

Vancouver:

Nagalla R. Synthesis of asynchronous circuits from signal transition graph specifications. [Internet] [Doctoral dissertation]. University of New South Wales; 1997. [cited 2021 May 08]. Available from: http://handle.unsw.edu.au/1959.4/55496 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:37860/SOURCE01?view=true.

Council of Science Editors:

Nagalla R. Synthesis of asynchronous circuits from signal transition graph specifications. [Doctoral Dissertation]. University of New South Wales; 1997. Available from: http://handle.unsw.edu.au/1959.4/55496 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:37860/SOURCE01?view=true


Portland State University

8. Cowan, Christopher Lee. Drafting in Self-Timed Circuits.

Degree: PhD, Electrical and Computer Engineering, 2019, Portland State University

  Intervals between data items propagating in self-timed circuits are controlled by handshake signals rather than by a clock. In many self-timed designs, a trailing… (more)

Subjects/Keywords: Asynchronous circuits; Integrated circuits; Electrical and Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cowan, C. L. (2019). Drafting in Self-Timed Circuits. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/5099

Chicago Manual of Style (16th Edition):

Cowan, Christopher Lee. “Drafting in Self-Timed Circuits.” 2019. Doctoral Dissertation, Portland State University. Accessed May 08, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/5099.

MLA Handbook (7th Edition):

Cowan, Christopher Lee. “Drafting in Self-Timed Circuits.” 2019. Web. 08 May 2021.

Vancouver:

Cowan CL. Drafting in Self-Timed Circuits. [Internet] [Doctoral dissertation]. Portland State University; 2019. [cited 2021 May 08]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/5099.

Council of Science Editors:

Cowan CL. Drafting in Self-Timed Circuits. [Doctoral Dissertation]. Portland State University; 2019. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/5099

9. Tan, Zhou. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.

Degree: 2011, North Dakota State University

 This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create… (more)

Subjects/Keywords: Cellular automata.; Asynchronous circuits.; Pulse circuits.; Field programmable gate arrays.; Gate array circuits.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tan, Z. (2011). Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. (Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/29176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Thesis, North Dakota State University. Accessed May 08, 2021. http://hdl.handle.net/10365/29176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Web. 08 May 2021.

Vancouver:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Internet] [Thesis]. North Dakota State University; 2011. [cited 2021 May 08]. Available from: http://hdl.handle.net/10365/29176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Thesis]. North Dakota State University; 2011. Available from: http://hdl.handle.net/10365/29176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Mettala Gilla, Swetha. Silicon Compilation and Test for Dataflow Implementations in GasP and Click.

Degree: PhD, Electrical and Computer Engineering, 2018, Portland State University

  Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the… (more)

Subjects/Keywords: Data flow computing; Electrical engineering; Integrated circuits; Asynchronous circuits; Digital Circuits; Electrical and Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mettala Gilla, S. (2018). Silicon Compilation and Test for Dataflow Implementations in GasP and Click. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4237

Chicago Manual of Style (16th Edition):

Mettala Gilla, Swetha. “Silicon Compilation and Test for Dataflow Implementations in GasP and Click.” 2018. Doctoral Dissertation, Portland State University. Accessed May 08, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/4237.

MLA Handbook (7th Edition):

Mettala Gilla, Swetha. “Silicon Compilation and Test for Dataflow Implementations in GasP and Click.” 2018. Web. 08 May 2021.

Vancouver:

Mettala Gilla S. Silicon Compilation and Test for Dataflow Implementations in GasP and Click. [Internet] [Doctoral dissertation]. Portland State University; 2018. [cited 2021 May 08]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4237.

Council of Science Editors:

Mettala Gilla S. Silicon Compilation and Test for Dataflow Implementations in GasP and Click. [Doctoral Dissertation]. Portland State University; 2018. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4237


Rochester Institute of Technology

11. Levitan, Sabrina Rose. Investigation of the Benefits of Interlocked Synchronous Pipelines.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  The majority of today’s digital circuits use synchronous pipelines. As the technology nodes get smaller, these pipelines are facing problems with area, power, and… (more)

Subjects/Keywords: asynchronous circuits; CMOS logic circuits; current-mode logic; low-power electronics; pipeline arithmetic; Pipelines

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Levitan, S. R. (2019). Investigation of the Benefits of Interlocked Synchronous Pipelines. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10068

Chicago Manual of Style (16th Edition):

Levitan, Sabrina Rose. “Investigation of the Benefits of Interlocked Synchronous Pipelines.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed May 08, 2021. https://scholarworks.rit.edu/theses/10068.

MLA Handbook (7th Edition):

Levitan, Sabrina Rose. “Investigation of the Benefits of Interlocked Synchronous Pipelines.” 2019. Web. 08 May 2021.

Vancouver:

Levitan SR. Investigation of the Benefits of Interlocked Synchronous Pipelines. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2021 May 08]. Available from: https://scholarworks.rit.edu/theses/10068.

Council of Science Editors:

Levitan SR. Investigation of the Benefits of Interlocked Synchronous Pipelines. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10068

12. Germain, Sophie. Contrôle du spectre électromagnétique d’un circuit numérique asynchrone : Electromagnetic spectrum control of asynchronous digital circuits.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2019, Université Grenoble Alpes (ComUE)

La compatibilité électromagnétique des circuits est devenue un enjeu majeur en conception numérique. Des méthodes de conception existent déjà pour réduire de manière qualitative le… (more)

Subjects/Keywords: Circuits asynchrones; Compatibilité électromagnétique; Flot de conception; Asynchronous circuits; Electromagnetic compatibility; Design flow; 620

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Germain, S. (2019). Contrôle du spectre électromagnétique d’un circuit numérique asynchrone : Electromagnetic spectrum control of asynchronous digital circuits. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2019GREAT053

Chicago Manual of Style (16th Edition):

Germain, Sophie. “Contrôle du spectre électromagnétique d’un circuit numérique asynchrone : Electromagnetic spectrum control of asynchronous digital circuits.” 2019. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed May 08, 2021. http://www.theses.fr/2019GREAT053.

MLA Handbook (7th Edition):

Germain, Sophie. “Contrôle du spectre électromagnétique d’un circuit numérique asynchrone : Electromagnetic spectrum control of asynchronous digital circuits.” 2019. Web. 08 May 2021.

Vancouver:

Germain S. Contrôle du spectre électromagnétique d’un circuit numérique asynchrone : Electromagnetic spectrum control of asynchronous digital circuits. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2019. [cited 2021 May 08]. Available from: http://www.theses.fr/2019GREAT053.

Council of Science Editors:

Germain S. Contrôle du spectre électromagnétique d’un circuit numérique asynchrone : Electromagnetic spectrum control of asynchronous digital circuits. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2019. Available from: http://www.theses.fr/2019GREAT053

13. Rolloff, Otto. Polarisation de substrat à partir de micro-générateurs distribués pour une gestion de l’énergie pilotée par l’activité dans les technologies FD-SOI : Distributed Body-Bias Micro-Generators for an activity-driven power management in FD-SOI Technologies.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2019, Université Grenoble Alpes (ComUE)

Avec la croissance exponentielle des systèmes embarqués et des objets appelés IoT, le besoin de réduire la consommation d'énergie pour des raisons environnementales et également… (more)

Subjects/Keywords: Circuits Asynchrones; Fdsoi; Polarisation; Contrôle de performances; Asynchronous Circuits; Fdsoi; Biasing; Performance control; 620

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rolloff, O. (2019). Polarisation de substrat à partir de micro-générateurs distribués pour une gestion de l’énergie pilotée par l’activité dans les technologies FD-SOI : Distributed Body-Bias Micro-Generators for an activity-driven power management in FD-SOI Technologies. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2019GREAT081

Chicago Manual of Style (16th Edition):

Rolloff, Otto. “Polarisation de substrat à partir de micro-générateurs distribués pour une gestion de l’énergie pilotée par l’activité dans les technologies FD-SOI : Distributed Body-Bias Micro-Generators for an activity-driven power management in FD-SOI Technologies.” 2019. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed May 08, 2021. http://www.theses.fr/2019GREAT081.

MLA Handbook (7th Edition):

Rolloff, Otto. “Polarisation de substrat à partir de micro-générateurs distribués pour une gestion de l’énergie pilotée par l’activité dans les technologies FD-SOI : Distributed Body-Bias Micro-Generators for an activity-driven power management in FD-SOI Technologies.” 2019. Web. 08 May 2021.

Vancouver:

Rolloff O. Polarisation de substrat à partir de micro-générateurs distribués pour une gestion de l’énergie pilotée par l’activité dans les technologies FD-SOI : Distributed Body-Bias Micro-Generators for an activity-driven power management in FD-SOI Technologies. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2019. [cited 2021 May 08]. Available from: http://www.theses.fr/2019GREAT081.

Council of Science Editors:

Rolloff O. Polarisation de substrat à partir de micro-générateurs distribués pour une gestion de l’énergie pilotée par l’activité dans les technologies FD-SOI : Distributed Body-Bias Micro-Generators for an activity-driven power management in FD-SOI Technologies. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2019. Available from: http://www.theses.fr/2019GREAT081


University of Arkansas

14. Mize, Nicholas Renoudet. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.

Degree: MSCmpE, 2019, University of Arkansas

  As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away… (more)

Subjects/Keywords: Asynchronous; Circuit; Digital; MTNCL; Synthesis; VHDL; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3168

Chicago Manual of Style (16th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Masters Thesis, University of Arkansas. Accessed May 08, 2021. https://scholarworks.uark.edu/etd/3168.

MLA Handbook (7th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Web. 08 May 2021.

Vancouver:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2021 May 08]. Available from: https://scholarworks.uark.edu/etd/3168.

Council of Science Editors:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3168


University of Arkansas

15. Brady, John Davis. Evaluation and Analysis of NULL Convention Logic Circuits.

Degree: PhD, 2019, University of Arkansas

  Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and… (more)

Subjects/Keywords: Asynchronous Energy Consumption; Asynchronous IC Design; Asynchronous Power Consumption; NULL Convention Logic; Static Power Consumption; Voltage Scaling; Digital Circuits; Power and Energy; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Brady, J. D. (2019). Evaluation and Analysis of NULL Convention Logic Circuits. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3466

Chicago Manual of Style (16th Edition):

Brady, John Davis. “Evaluation and Analysis of NULL Convention Logic Circuits.” 2019. Doctoral Dissertation, University of Arkansas. Accessed May 08, 2021. https://scholarworks.uark.edu/etd/3466.

MLA Handbook (7th Edition):

Brady, John Davis. “Evaluation and Analysis of NULL Convention Logic Circuits.” 2019. Web. 08 May 2021.

Vancouver:

Brady JD. Evaluation and Analysis of NULL Convention Logic Circuits. [Internet] [Doctoral dissertation]. University of Arkansas; 2019. [cited 2021 May 08]. Available from: https://scholarworks.uark.edu/etd/3466.

Council of Science Editors:

Brady JD. Evaluation and Analysis of NULL Convention Logic Circuits. [Doctoral Dissertation]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3466


University of Utah

16. Vij, Vikas S. Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows.

Degree: PhD, Electrical & Computer Engineering, 2013, University of Utah

Asynchronous design has a very promising potential even though it has largely receiveda cold reception from industry. Part of this reluctance has been due to… (more)

Subjects/Keywords: Algorithms; Asynchronous circuits; Methodology; Relative timing; Synchronous CAD tools

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vij, V. S. (2013). Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/3490/rec/176

Chicago Manual of Style (16th Edition):

Vij, Vikas S. “Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows.” 2013. Doctoral Dissertation, University of Utah. Accessed May 08, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/3490/rec/176.

MLA Handbook (7th Edition):

Vij, Vikas S. “Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows.” 2013. Web. 08 May 2021.

Vancouver:

Vij VS. Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows. [Internet] [Doctoral dissertation]. University of Utah; 2013. [cited 2021 May 08]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/3490/rec/176.

Council of Science Editors:

Vij VS. Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows. [Doctoral Dissertation]. University of Utah; 2013. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/3490/rec/176


Cornell University

17. Fang, David. Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems.

Degree: 2008, Cornell University

 Designing and optimizing large-scale, asynchronous circuits is often an iterative process that cycles through synthesis, simulating, benchmarking, and program rewriting. Asynchronous circuits are usually specified… (more)

Subjects/Keywords: asynchronous circuits; profiling; trace; analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fang, D. (2008). Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems. (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/11065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fang, David. “Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems.” 2008. Thesis, Cornell University. Accessed May 08, 2021. http://hdl.handle.net/1813/11065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fang, David. “Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems.” 2008. Web. 08 May 2021.

Vancouver:

Fang D. Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems. [Internet] [Thesis]. Cornell University; 2008. [cited 2021 May 08]. Available from: http://hdl.handle.net/1813/11065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fang D. Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems. [Thesis]. Cornell University; 2008. Available from: http://hdl.handle.net/1813/11065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Gao, Yang. An Energy Efficient Asynchronous Time-Domain Comparator.

Degree: MS, Electrical Engineering, 2013, Texas A&M University

 In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long… (more)

Subjects/Keywords: Analog-to-digital converter; asynchronous circuits; comparator; successive approximation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gao, Y. (2013). An Energy Efficient Asynchronous Time-Domain Comparator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149314

Chicago Manual of Style (16th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Masters Thesis, Texas A&M University. Accessed May 08, 2021. http://hdl.handle.net/1969.1/149314.

MLA Handbook (7th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Web. 08 May 2021.

Vancouver:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Internet] [Masters thesis]. Texas A&M University; 2013. [cited 2021 May 08]. Available from: http://hdl.handle.net/1969.1/149314.

Council of Science Editors:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Masters Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149314


Hong Kong University of Science and Technology

19. Lam, Hing-Mo. High performance coarse grain asynchronous circuit design.

Degree: 2002, Hong Kong University of Science and Technology

 Synchronous circuit is currently the most popular implementation method for digital circuit. However, its performance is limited by the worst-case delay of the slowest pipeline… (more)

Subjects/Keywords: Asynchronous circuits  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lam, H. (2002). High performance coarse grain asynchronous circuit design. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-4629 ; https://doi.org/10.14711/thesis-b775098 ; http://repository.ust.hk/ir/bitstream/1783.1-4629/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lam, Hing-Mo. “High performance coarse grain asynchronous circuit design.” 2002. Thesis, Hong Kong University of Science and Technology. Accessed May 08, 2021. http://repository.ust.hk/ir/Record/1783.1-4629 ; https://doi.org/10.14711/thesis-b775098 ; http://repository.ust.hk/ir/bitstream/1783.1-4629/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lam, Hing-Mo. “High performance coarse grain asynchronous circuit design.” 2002. Web. 08 May 2021.

Vancouver:

Lam H. High performance coarse grain asynchronous circuit design. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2002. [cited 2021 May 08]. Available from: http://repository.ust.hk/ir/Record/1783.1-4629 ; https://doi.org/10.14711/thesis-b775098 ; http://repository.ust.hk/ir/bitstream/1783.1-4629/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lam H. High performance coarse grain asynchronous circuit design. [Thesis]. Hong Kong University of Science and Technology; 2002. Available from: http://repository.ust.hk/ir/Record/1783.1-4629 ; https://doi.org/10.14711/thesis-b775098 ; http://repository.ust.hk/ir/bitstream/1783.1-4629/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

20. Najibi, Mehrdad. Average-case performance analysis and optimization of conditional asynchronous circuits.

Degree: PhD, Electrical Engineering (VLSI Design), 2014, University of Southern California

Asynchronous circuits continue to gain interest as an attractive alternative to synchronous design for both low-power and high-performance applications. In both applications, however, providing accurate… (more)

Subjects/Keywords: asynchronous circuits; average performance analysis; pipeline optimization; Petri nets; Markov chain

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Najibi, M. (2014). Average-case performance analysis and optimization of conditional asynchronous circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356419/rec/1010

Chicago Manual of Style (16th Edition):

Najibi, Mehrdad. “Average-case performance analysis and optimization of conditional asynchronous circuits.” 2014. Doctoral Dissertation, University of Southern California. Accessed May 08, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356419/rec/1010.

MLA Handbook (7th Edition):

Najibi, Mehrdad. “Average-case performance analysis and optimization of conditional asynchronous circuits.” 2014. Web. 08 May 2021.

Vancouver:

Najibi M. Average-case performance analysis and optimization of conditional asynchronous circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2014. [cited 2021 May 08]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356419/rec/1010.

Council of Science Editors:

Najibi M. Average-case performance analysis and optimization of conditional asynchronous circuits. [Doctoral Dissertation]. University of Southern California; 2014. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356419/rec/1010


University of Arkansas

21. Brady, John Davis. Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection.

Degree: MSCmpE, 2014, University of Arkansas

  Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials… (more)

Subjects/Keywords: Asynchronous; Radiation Hardening; SEL Protection; SEU Mitigation; Digital Circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Brady, J. D. (2014). Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2299

Chicago Manual of Style (16th Edition):

Brady, John Davis. “Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection.” 2014. Masters Thesis, University of Arkansas. Accessed May 08, 2021. https://scholarworks.uark.edu/etd/2299.

MLA Handbook (7th Edition):

Brady, John Davis. “Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection.” 2014. Web. 08 May 2021.

Vancouver:

Brady JD. Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2021 May 08]. Available from: https://scholarworks.uark.edu/etd/2299.

Council of Science Editors:

Brady JD. Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2299


University of Arkansas

22. Suchanek, Andrew Lloyd. Asynchronous Circuit Stacking for Simplified Power Management.

Degree: PhD, 2018, University of Arkansas

  As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power… (more)

Subjects/Keywords: Asynchronous; Low-power; MTNCL; Voltage Stacking; Digital Circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suchanek, A. L. (2018). Asynchronous Circuit Stacking for Simplified Power Management. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2805

Chicago Manual of Style (16th Edition):

Suchanek, Andrew Lloyd. “Asynchronous Circuit Stacking for Simplified Power Management.” 2018. Doctoral Dissertation, University of Arkansas. Accessed May 08, 2021. https://scholarworks.uark.edu/etd/2805.

MLA Handbook (7th Edition):

Suchanek, Andrew Lloyd. “Asynchronous Circuit Stacking for Simplified Power Management.” 2018. Web. 08 May 2021.

Vancouver:

Suchanek AL. Asynchronous Circuit Stacking for Simplified Power Management. [Internet] [Doctoral dissertation]. University of Arkansas; 2018. [cited 2021 May 08]. Available from: https://scholarworks.uark.edu/etd/2805.

Council of Science Editors:

Suchanek AL. Asynchronous Circuit Stacking for Simplified Power Management. [Doctoral Dissertation]. University of Arkansas; 2018. Available from: https://scholarworks.uark.edu/etd/2805


Portland State University

23. Park, Hoon. Formal Modeling and Verification of Delay-Insensitive Circuits.

Degree: PhD, Electrical and Computer Engineering, 2015, Portland State University

  Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use… (more)

Subjects/Keywords: Asynchronous circuits  – Design and construction; Integrated circuits  – Very large scale integration  – Design and construction; Digital Circuits; Electrical and Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, H. (2015). Formal Modeling and Verification of Delay-Insensitive Circuits. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/2639

Chicago Manual of Style (16th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Doctoral Dissertation, Portland State University. Accessed May 08, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/2639.

MLA Handbook (7th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Web. 08 May 2021.

Vancouver:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Internet] [Doctoral dissertation]. Portland State University; 2015. [cited 2021 May 08]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639.

Council of Science Editors:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Doctoral Dissertation]. Portland State University; 2015. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639


Portland State University

24. Padwal, Prachi Gulab. Just-In-Time Power Gating of GasP Circuits.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2013, Portland State University

  In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle.… (more)

Subjects/Keywords: Low voltage integrated circuits  – Energy consumption; Asynchronous circuits  – Design and construction; Logic circuits; Electrical and Computer Engineering; Other Computer Sciences

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Padwal, P. G. (2013). Just-In-Time Power Gating of GasP Circuits. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/211

Chicago Manual of Style (16th Edition):

Padwal, Prachi Gulab. “Just-In-Time Power Gating of GasP Circuits.” 2013. Masters Thesis, Portland State University. Accessed May 08, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/211.

MLA Handbook (7th Edition):

Padwal, Prachi Gulab. “Just-In-Time Power Gating of GasP Circuits.” 2013. Web. 08 May 2021.

Vancouver:

Padwal PG. Just-In-Time Power Gating of GasP Circuits. [Internet] [Masters thesis]. Portland State University; 2013. [cited 2021 May 08]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/211.

Council of Science Editors:

Padwal PG. Just-In-Time Power Gating of GasP Circuits. [Masters Thesis]. Portland State University; 2013. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/211

25. Silva, Thiago de Oliveira. Elastic circuits in FPGA.

Degree: 2017, Brazil

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área… (more)

Subjects/Keywords: Microeletrônica; Circuitos digitais; Elastic Circuits; Asynchronous Circuits; Synchronous Circuits; ASIC; FPGA; IC Design Methodology; Digital IC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Silva, T. d. O. (2017). Elastic circuits in FPGA. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/174540

Chicago Manual of Style (16th Edition):

Silva, Thiago de Oliveira. “Elastic circuits in FPGA.” 2017. Masters Thesis, Brazil. Accessed May 08, 2021. http://hdl.handle.net/10183/174540.

MLA Handbook (7th Edition):

Silva, Thiago de Oliveira. “Elastic circuits in FPGA.” 2017. Web. 08 May 2021.

Vancouver:

Silva TdO. Elastic circuits in FPGA. [Internet] [Masters thesis]. Brazil; 2017. [cited 2021 May 08]. Available from: http://hdl.handle.net/10183/174540.

Council of Science Editors:

Silva TdO. Elastic circuits in FPGA. [Masters Thesis]. Brazil; 2017. Available from: http://hdl.handle.net/10183/174540


Université de Grenoble

26. Porcher, Alexandre. Synthèse de moniteurs asynchrones à partir d'assertions temporelles pour la surveillance robuste de circuits synchrones : Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

Avec l'avènement des systèmes intégrés complexes, la vérification par assertions(Assertion Based Verification ou ABV) s'est imposée comme une solution pour la vérification semi-formelle des circuits.… (more)

Subjects/Keywords: Circuits asynchrones; Vérification basée sur les assertions; Property Specification Language; Moniteurs asynchrones; Quasi Insensibilité au Delais; Robustesse; Asynchronous circuits; Assertion Based Verification; PSL; Asynchronous monitors; Quasi Delay Insensitivity; Robustness

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Porcher, A. (2012). Synthèse de moniteurs asynchrones à partir d'assertions temporelles pour la surveillance robuste de circuits synchrones : Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT004

Chicago Manual of Style (16th Edition):

Porcher, Alexandre. “Synthèse de moniteurs asynchrones à partir d'assertions temporelles pour la surveillance robuste de circuits synchrones : Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed May 08, 2021. http://www.theses.fr/2012GRENT004.

MLA Handbook (7th Edition):

Porcher, Alexandre. “Synthèse de moniteurs asynchrones à partir d'assertions temporelles pour la surveillance robuste de circuits synchrones : Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits.” 2012. Web. 08 May 2021.

Vancouver:

Porcher A. Synthèse de moniteurs asynchrones à partir d'assertions temporelles pour la surveillance robuste de circuits synchrones : Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2021 May 08]. Available from: http://www.theses.fr/2012GRENT004.

Council of Science Editors:

Porcher A. Synthèse de moniteurs asynchrones à partir d'assertions temporelles pour la surveillance robuste de circuits synchrones : Asynchronous monitors synthesis from temporal assertions for the robust observation of synchronous circuits. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT004


University of Arkansas

27. Roark, Justin Thomas. Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits.

Degree: MSCmpE, 2013, University of Arkansas

  Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased… (more)

Subjects/Keywords: Applied sciences; asynchronous circuits; Energy efficiency; Integrated circuits; Multi-threshold null convention logic; Null convention logic; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roark, J. T. (2013). Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/862

Chicago Manual of Style (16th Edition):

Roark, Justin Thomas. “Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits.” 2013. Masters Thesis, University of Arkansas. Accessed May 08, 2021. https://scholarworks.uark.edu/etd/862.

MLA Handbook (7th Edition):

Roark, Justin Thomas. “Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits.” 2013. Web. 08 May 2021.

Vancouver:

Roark JT. Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits. [Internet] [Masters thesis]. University of Arkansas; 2013. [cited 2021 May 08]. Available from: https://scholarworks.uark.edu/etd/862.

Council of Science Editors:

Roark JT. Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits. [Masters Thesis]. University of Arkansas; 2013. Available from: https://scholarworks.uark.edu/etd/862


Cornell University

28. Sheikh, Basit. Operand-Optimized Asynchronous Floating-Point Arithmetic Circuits.

Degree: PhD, Electrical Engineering, 2012, Cornell University

Subjects/Keywords: Asynchronous logic circuits; Arithmetic circuits; VLSI design

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sheikh, B. (2012). Operand-Optimized Asynchronous Floating-Point Arithmetic Circuits. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/29239

Chicago Manual of Style (16th Edition):

Sheikh, Basit. “Operand-Optimized Asynchronous Floating-Point Arithmetic Circuits.” 2012. Doctoral Dissertation, Cornell University. Accessed May 08, 2021. http://hdl.handle.net/1813/29239.

MLA Handbook (7th Edition):

Sheikh, Basit. “Operand-Optimized Asynchronous Floating-Point Arithmetic Circuits.” 2012. Web. 08 May 2021.

Vancouver:

Sheikh B. Operand-Optimized Asynchronous Floating-Point Arithmetic Circuits. [Internet] [Doctoral dissertation]. Cornell University; 2012. [cited 2021 May 08]. Available from: http://hdl.handle.net/1813/29239.

Council of Science Editors:

Sheikh B. Operand-Optimized Asynchronous Floating-Point Arithmetic Circuits. [Doctoral Dissertation]. Cornell University; 2012. Available from: http://hdl.handle.net/1813/29239


Portland State University

29. Scheiblauer, Kristopher S. Quadded GasP: a Fault Tolerant Asynchronous Design.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2017, Portland State University

  As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making… (more)

Subjects/Keywords: Fault tolerance (Engineering); Asynchronous circuits; Electrical and Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Scheiblauer, K. S. (2017). Quadded GasP: a Fault Tolerant Asynchronous Design. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/3475

Chicago Manual of Style (16th Edition):

Scheiblauer, Kristopher S. “Quadded GasP: a Fault Tolerant Asynchronous Design.” 2017. Masters Thesis, Portland State University. Accessed May 08, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/3475.

MLA Handbook (7th Edition):

Scheiblauer, Kristopher S. “Quadded GasP: a Fault Tolerant Asynchronous Design.” 2017. Web. 08 May 2021.

Vancouver:

Scheiblauer KS. Quadded GasP: a Fault Tolerant Asynchronous Design. [Internet] [Masters thesis]. Portland State University; 2017. [cited 2021 May 08]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/3475.

Council of Science Editors:

Scheiblauer KS. Quadded GasP: a Fault Tolerant Asynchronous Design. [Masters Thesis]. Portland State University; 2017. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/3475


University of Arkansas

30. Bell, Brent. Efficacy of Multi-Threshold NULL Convention Logic in Low-Power Applications.

Degree: PhD, 2018, University of Arkansas

  In order for an asynchronous design paradigm such as Multi-Threshold NULL Convention Logic (MTNCL) to be adopted by industry, it is important for circuit… (more)

Subjects/Keywords: Asynchronous; Clockless; Digital; MTNCL; Power; Digital Circuits; Power and Energy; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bell, B. (2018). Efficacy of Multi-Threshold NULL Convention Logic in Low-Power Applications. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2909

Chicago Manual of Style (16th Edition):

Bell, Brent. “Efficacy of Multi-Threshold NULL Convention Logic in Low-Power Applications.” 2018. Doctoral Dissertation, University of Arkansas. Accessed May 08, 2021. https://scholarworks.uark.edu/etd/2909.

MLA Handbook (7th Edition):

Bell, Brent. “Efficacy of Multi-Threshold NULL Convention Logic in Low-Power Applications.” 2018. Web. 08 May 2021.

Vancouver:

Bell B. Efficacy of Multi-Threshold NULL Convention Logic in Low-Power Applications. [Internet] [Doctoral dissertation]. University of Arkansas; 2018. [cited 2021 May 08]. Available from: https://scholarworks.uark.edu/etd/2909.

Council of Science Editors:

Bell B. Efficacy of Multi-Threshold NULL Convention Logic in Low-Power Applications. [Doctoral Dissertation]. University of Arkansas; 2018. Available from: https://scholarworks.uark.edu/etd/2909

[1] [2] [3]

.