subject:(Application specific integrated circuit ASIC )

University of Illinois – Urbana-Champaign

1. Assem, Pourya. In-sensor information processing for resource-limited platforms on flexible epidermal substrates.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

► Moving towards the age of big data, the demand for embedded processing has been drastically increasing to make inference and intelligent decisions at lower architectural… (more)

Subjects/Keywords: Application-specific integrated circuit (ASIC); Integrated circuit (IC); Near-field communication (NFC); Pan-Tompkins Algorithm (PTA); Photoplethysmogram (PPG); Epidermal electronics

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APA (6^th Edition):

Assem, P. (2016). In-sensor information processing for resource-limited platforms on flexible epidermal substrates. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Assem, Pourya. “In-sensor information processing for resource-limited platforms on flexible epidermal substrates.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/95628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Assem, Pourya. “In-sensor information processing for resource-limited platforms on flexible epidermal substrates.” 2016. Web. 04 Mar 2021.

Vancouver:

Assem P. In-sensor information processing for resource-limited platforms on flexible epidermal substrates. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/95628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Assem P. In-sensor information processing for resource-limited platforms on flexible epidermal substrates. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

2. Chuang, Sheng-Chih. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.

Degree: Master, Electrical Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

► This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a… (more)

Subjects/Keywords: Nerve cuff recording; Electroneurogram; Sample-and-hold circuit; Application-specific integrated circuit (ASIC); Low power circuit; Velocity selective recording

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APA (6^th Edition):

Chuang, S. (2015). Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Web. 04 Mar 2021.

Vancouver:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Lin, Sheng-En. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

► The analog-to-digital converter (ADC) is an essential component in modern mixed-signal system applications. This thesis presents the design and evaluation of a single-slope integrating ADC… (more)

Subjects/Keywords: single-slope integrating ADC; voltage-to-time converter; low power circuit design; application-specific integrated circuit (ASIC); biological-signal recording system

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APA (6^th Edition):

Lin, S. (2017). Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Web. 04 Mar 2021.

Vancouver:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Zhou, Yang. Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale.

Degree: Docteur es, Instrumentation et microélectronique, 2014, Université de Strasbourg

URL: http://www.theses.fr/2014STRAE021

►

Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux… (more)

▼

Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux élevé. Un nouveauconcept pour l’identification de l’espèce des particules proposé dans la présente étude, est basésur l'analyse des amas de particules déclenchés. Pour valider ce nouveau concept, un capteur detaille complet, qui comprend la matrice de pixel sensible aux particules ionisés signal, une chaînede traitement du signal analogique, un convertisseur analogue numérique de 3 bits, et untraitement du signal numérique a été conçu dans un processus de 0.35 μm. Le capteur sortiedirectement des informations de flux à travers 4 canaux avec un débit de données très faible(80 bps) et dissipation d’énergie minimale (~ 100 mW). Chaque canal représente particules avecdifférentes espèces et les énergies. La densité maximum de flux mesurable est jusqu'à 108particules/cm2/s (coups s'accumulent < 5%). Un prototype à échelle réduite a été fabriqué et testéavec trois types d'illumination de rayonnement (rayons X, les électrons et laser infrarouge). Tousles résultats obtenus valident le nouveau concept proposé. Un moniteur de rayonnement spatialtrès miniaturisé basé sur un capteur de pixel CMOS peut être prévu. Le moniteur peut présente lesmêmes performances que les compteurs actuels, mais avec une dissipation de puissance réduited'un ordre de grandeur qu'un poids, un volume d'encombrement et un coût moindre. En outre, enraison de ses sorties de haut niveau et faible débit de données, aucune traitement supplémentairedu signal dehors du capteur est nécessaire, ce qui le rend particulièrement attrayant pour desapplications dan les petits satellitaires.

This thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0.35μm process. The sensor directly output particles flux information through 4 channels with a verylow data rate (80 bps) and minimal power dissipation (~ 100mW). Each channel representsparticles with different species and energies. The highest measurable flux density is up to 108particles/cm2/s (hits pile up < 5%). A reduced scale prototype was fabricated and tested with 3types of radiation illumination (X-ray, electrons and infrared laser). All the results obtained validatethe proposed new concept and a highly miniaturized space radiation monitor based on a singleCMOS pixel sensor could be foreseen. The monitor could provide measurements of comparable orbetter quality than existing instruments, but at around an order of magnitude lower powerconsumption, mass and volume and a lower unit cost. Moreover, due to its high…

Advisors/Committee Members: Hu, Yann (thesis director), Baudot, Jérôme (thesis director).

Subjects/Keywords: Très miniaturisé moniteur de rayonnement dans l'espace; CPS (CMOS pixel sensor); ASIC (Application Specific Integrated Circuit); Highly miniaturized space radiation monitor; CMOS pixel sensor (CPS); Application Specific Integrated Circuit (ASIC); Partical identification and counting; 621.38; 539.7

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhou, Y. (2014). Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2014STRAE021

Chicago Manual of Style (16^th Edition):

Zhou, Yang. “Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale.” 2014. Doctoral Dissertation, Université de Strasbourg. Accessed March 04, 2021. http://www.theses.fr/2014STRAE021.

MLA Handbook (7^th Edition):

Zhou, Yang. “Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale.” 2014. Web. 04 Mar 2021.

Vancouver:

Zhou Y. Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2014. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2014STRAE021.

Council of Science Editors:

Zhou Y. Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale. [Doctoral Dissertation]. Université de Strasbourg; 2014. Available from: http://www.theses.fr/2014STRAE021

5. Tinguy, Pierre. Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator.

Degree: Docteur es, Sciences pour l'ingénieur, 2011, Besançon

URL: http://www.theses.fr/2011BESA2017

►

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à… (more)

▼

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d’entretien de type Colpitts,la mise en forme et jusqu’à l’adaptation du signal à sa charge d’utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s’orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del’architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l’avons reportée par flip chip sur une interfacespécifique pour

The increasing demand for high-performance devices featuring compact, lighter-weight designs with low-power consumptionalso impacts quartz crystal oscillators used in metrological applications (time bases, sensors), telephony or navigation. Inthis context, we have developed an ASIC (Application Specific Integrated Circuit) in 0.35 μm SiGe BiCMOS technology(Austriamicrosystems®) supplied by 3.3 V (±10%) to realize a miniaturized quartz crystal oscillator operating in the 10 MHzto 100 MHz frequency range. The fabricated die hosts several RF cells in a 4 mm2 area, including a sustaining amplifier(Colpitts topology), a signal shaping circuit and an output buffer dedicated to a specific load (50 W or HCMOS). These cellsare biased by a fully integrated CMOS bandgap voltage reference. The die power consumption remains lower than 100 mWfor a targeted phase noise floor as low as −150 dBc/Hz at a 40 MHz carrier frequency. A thermal control loop has in additionbeen partially integrated to the ASIC, in order to reduce the quartz resonator thermal sensitivity as well as to extend thepotential application field of the developed die to oven applications (OCXO). The thermal control, that is strongly dependanton the mechanical design, has been designed and tested by using electrical analogy modeling on Spectre® simulator. Finallyour integrated circuit has been connected to a specific substrate using flip chip technology to realize a miniaturized quartzcrystal oscillator packaged on a…

Advisors/Committee Members: Dulmet, Bernard (thesis director).

Subjects/Keywords: Oscillateur à quartz; Intégration; ASIC Application specific integrated circuit; Topologie Colpitts; Régulation en température; Modélisation; Flip chip; Quartz crystal oscillator; Integration; ASIC Application specific integrated circuit; Colpitts topology; Thermal control; Modeling; Flip chip; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tinguy, P. (2011). Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator. (Doctoral Dissertation). Besançon. Retrieved from http://www.theses.fr/2011BESA2017

Chicago Manual of Style (16^th Edition):

Tinguy, Pierre. “Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator.” 2011. Doctoral Dissertation, Besançon. Accessed March 04, 2021. http://www.theses.fr/2011BESA2017.

MLA Handbook (7^th Edition):

Tinguy, Pierre. “Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator.” 2011. Web. 04 Mar 2021.

Vancouver:

Tinguy P. Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator. [Internet] [Doctoral dissertation]. Besançon; 2011. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2011BESA2017.

Council of Science Editors:

Tinguy P. Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator. [Doctoral Dissertation]. Besançon; 2011. Available from: http://www.theses.fr/2011BESA2017

Université de Sherbrooke

6. Arpin, Louis. Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels.

Degree: 2012, Université de Sherbrooke

URL: http://hdl.handle.net/11143/6148

► Des développements technologiques récents concernant les photodiodes à effet avalanche (PDA) ont mené à la conception et la fabrication d'un tout nouveau module de détection… (more)

▼ Des développements technologiques récents concernant les photodiodes à effet avalanche (PDA) ont mené à la conception et la fabrication d'un tout nouveau module de détection de radiation TEP (tomographie d'émission par positrons) destiné à l'imagerie moléculaire préclinique. Il est basé sur une matrice de 8 par 8 scintillateurs LYSO (ortho-silicate de lutétium dopé au cérium, cerium-doped lutetium yttrium orthosilicate ) individuellement couplés aux pixels de deux matrices monolithiques de 4 par 8 PDA. Cette avancée, pouvant amener la résolution spatiale d'un scanner à passer sous la barrière du mm, exige la conception d'un tout nouveau système d'acquisition de données. En effet, il faut adapter le système de lecture individuelle de chacun des pixels du bloc de détection de façon à satisfaire la multiplication par ~8, relativement à une version antérieure (le LabPET[indice supérieur TM] I), de la densité de pixels du futur scanner LabPET[indice supérieur TM] II. Conséquemment, le traitement de signal numérique ne peut être exclusivement embarqué dans les matrices de portes logiques programmable (field-programmable gate array , FPGA) du système d'acquisition, en considérant les aspects monétaires, d'espace occupé et de puissance consommée de l'ensemble du projet LabPET[indice supérieur TM] II. De façon à s'adapter à cette nouvelle réalité, un nouveau circuit intégré à application spécifique (application specific integrated circuit, ASIC) à signaux mixtes avec 64 canaux d'acquisition, fabriqué avec la technologie TSMC CMOS 0,18 [micromètre], a été conçu. L'ASIC utilise la méthode de temps au-dessus d'un seuil (time over threshold , ToT), déjà implantée dans des applications de physique des hautes-énergies, de manière à extraire numériquement l'information relative à un rayonnement interagissant avec la matrice de détection (l'énergie, le temps et le numéro de pixel de l'événement). Dans le cadre de ce projet, une architecture complexe de machines à états-finis, cadencée par une horloge de 100 MHz, a été implantée et elle permet à l'ASIC d'identifier le taux anticipé de 3 000 événements par seconde par canal. Ceci est réalisé en calculant en temps réel le paramètre ToT tout en assurant la calibration adéquate de chacune des chaînes d'acquisition. Le circuit intégré peut caractériser jusqu'à 2 Mévénements/s malgré son unique lien différentiel à bas voltage (low-voltage differential signaling, LVDS) de transfert de données et consomme environ 600 mW. L'ASIC a été développé en suivant un processus de conception de circuits intégrés à signaux mixtes. Il permet notamment de minimiser et de vérifier l'impact des indésirables effets parasites sur la circuiterie analogique et numérique de l'ensemble avant que les dessins de masques ne soient envoyés vers la fonderie pour fabriquer le circuit désiré. Advisors/Committee Members: Fontaine, Réjean (advisor).

Subjects/Keywords: Lien différentiel à bas voltage (low-voltage differential signaling, LVDS); Machines à états-finis; Temps au-dessus d'un seuil (time over threshold, ToT); Circuit intégré à application spécifique (application specific integrated circuit, ASIC) à signaux mixtes; Imagerie moléculaire préclinique; LabPET[indice supérieur TM]; Tomographie d'émission par positrons (TEP); Photodiode à effet avalanche (PDA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Arpin, L. (2012). Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels. (Masters Thesis). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/6148

Chicago Manual of Style (16^th Edition):

Arpin, Louis. “Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels.” 2012. Masters Thesis, Université de Sherbrooke. Accessed March 04, 2021. http://hdl.handle.net/11143/6148.

MLA Handbook (7^th Edition):

Arpin, Louis. “Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels.” 2012. Web. 04 Mar 2021.

Vancouver:

Arpin L. Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels. [Internet] [Masters thesis]. Université de Sherbrooke; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11143/6148.

Council of Science Editors:

Arpin L. Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels. [Masters Thesis]. Université de Sherbrooke; 2012. Available from: http://hdl.handle.net/11143/6148

California State University – Northridge

7. Pandya, Parth. Backend design and testability of a digital ASIC.

Degree: MS, Electrical and Computer Engineering, 2, California State University – Northridge

URL: http://hdl.handle.net/10211.3/199956

► Very Large Scale Integration (VLSI) Design is an important and complex area of Electrical and Computer Engineering field. It uses many Computer Aided Design (CAD)… (more)

Subjects/Keywords: Application Specific Integrated Circuit (ASIC) design flow; Dissertations, Academic – CSUN – Engineering – Electrical and Computer Engineering.

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APA (6^th Edition):

Pandya, P. (2). Backend design and testability of a digital ASIC. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.3/199956

Chicago Manual of Style (16^th Edition):

Pandya, Parth. “Backend design and testability of a digital ASIC.” 2. Masters Thesis, California State University – Northridge. Accessed March 04, 2021. http://hdl.handle.net/10211.3/199956.

MLA Handbook (7^th Edition):

Pandya, Parth. “Backend design and testability of a digital ASIC.” 2. Web. 04 Mar 2021.

Vancouver:

Pandya P. Backend design and testability of a digital ASIC. [Internet] [Masters thesis]. California State University – Northridge; 2. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10211.3/199956.

Council of Science Editors:

Pandya P. Backend design and testability of a digital ASIC. [Masters Thesis]. California State University – Northridge; 2. Available from: http://hdl.handle.net/10211.3/199956

Ohio University

8. Gunawardena, Sanjeev. Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays.

Degree: MS, Electrical Engineering & Computer Science (Engineering and Technology), 2000, Ohio University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779

► The Global Positioning System represents the pinnacle of navigation technology for the 21st century. As new technologies integrate GPS services, the limited availability of… (more)

▼ The Global Positioning System represents the pinnacle of navigation technology for the 21st century. As new technologies integrate GPS services, the limited availability of GPS in environments where the signal is severely attenuated, subject to strong multipath or high dynamics becomes an obstacle to a rapidly growing industry. A novel scheme for processing the GPS signal, namely a software radio employing block-processing techniques similar to those used for image processing has proven to enhance the usability of GPS in such environments. However, these techniques have huge computational requirements that are impossible to meet with a microprocessor. Custom designed hardware, such as an application specific integrated circuit (ASIC) would handle the processing requirement, but defeats the philosophy of a software radio since the algorithms cannot be changed. Field programmable gate arrays (FPGAs) are beginning to replace ASICs in certain applications since they feature software-like re-programmability while approaching ASIC-like performance. FPGAs are excellent candidates for research since they lack the NRE costs associated with ASICs. Hence, FPGAs are the most attractive implementation platform for developing a real-time block-processing GPS receiver. This work lays the groundwork for the implementation of a real-time block-processing GPS receiver in FPGA hardware. It is a feasibility study since the problem is approached at a high-level of abstraction. The original block-processing approach is re-analyzed for implementation in FPGA hardware. Implementing the 5000-point FFTs in finite-precision hardware represents one of the biggest challenges in this work. This requires analysis of the FFT error bound to determine the minimum precision required that would yield acceptable results while minimizing hardware cost. Even though the analytical error bound for finite-precision FFTs is well documented in past literature, its direct application to the block-processing problem becomes too complex. This work employs statistical results of simulations to deduce the optimum hardware architecture and concludes that real-time capability can be achieved with currently available technology. Advisors/Committee Members: Starzyk, Janusz (Advisor).

Subjects/Keywords: Global Positioning System; GPS; block-processing technique; application specific integrated circuit; ASIC; FFT; Field programmable gate arrays; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Gunawardena, S. (2000). Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779

Chicago Manual of Style (16^th Edition):

Gunawardena, Sanjeev. “Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays.” 2000. Masters Thesis, Ohio University. Accessed March 04, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779.

MLA Handbook (7^th Edition):

Gunawardena, Sanjeev. “Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays.” 2000. Web. 04 Mar 2021.

Vancouver:

Gunawardena S. Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays. [Internet] [Masters thesis]. Ohio University; 2000. [cited 2021 Mar 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779.

Council of Science Editors:

Gunawardena S. Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays. [Masters Thesis]. Ohio University; 2000. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779

9. Zhao, Wei. Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex.

Degree: Docteur es, Instrumentation et microélectronique, 2015, Université de Strasbourg

URL: http://www.theses.fr/2015STRAE004

►

La thèse présente le développement de CPS (CMOS Pixel Sensors) intégré avec CAN au niveau du pixel pour les couches externes du détecteur de vertex… (more)

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La thèse présente le développement de CPS (CMOS Pixel Sensors) intégré avec CAN au niveau du pixel pour les couches externes du détecteur de vertex de l’ILD (International Large Detector). Motivé par la physique dans l’ILC (International Linear Collider), une précision élevée est nécessaire pour les détecteurs. La priorité des capteurs qui montre sur les couches externes est une faible consommation d’énergie en raison du rapport élevé de couverture de la surface sensible (~90%) dans le détecteur de vertex. Le CPS intégré avec CAN est un choix approprié pour cette application. L’architecture de CAN de niveau colonne ne fournit pas une performance optimisée en termes de bruit et la consommation d’énergie. La conception de CAN au niveau du pixel a été proposée. Bénéficiant des sorties de pixels tout-numérique, CAN au niveau des pixels présentent les mérites évidents sur le bruit, la vitesse, la zone sensible et la consommation d’énergie. Un prototype de capteur, appelé MIMADC, a été implémenté par un processus de 0.18 μm CIS (CMOS Image Sensor). L’objectif de ce capteur est de vérifier la faisabilité du CPS intégré avec les CAN au niveau des pixels. Trois matrices sont incluses dans ce prototype, mais avec deux types différents de CAN au niveau de pixel: une avec des CAN à registre à approximations successives (SAR), et les deux autres avec des CAN à une seule pente (Single-Slope, SS) CAN. Toutes les trois possédant les pixels de la même taille de 35×35 μm2 et une résolution de 3-bit. Dans ce texte, des analyses théoriques et le prototype sont présentés, ainsi que la conception détaille des circuits.

This thesis presents the development of CMOS pixel sensors (CPS) integrated with pixel-level ADCs for the outer layers of the ILD (International Large Detector) vertex detector. Driven by physics in the ILC (International Linear Collider), an unprecedented precision is required for the detectors. The priority of the sensors mounted on the outer layers is low power consumption due to the large coverage ratio of the sensitive area (~90%) in the vertex detector. The CPS integrated with ADCs is a promising candidate for this application. The architecture of column-level ADCs, exists but do not provide an optimized performance in terms of noise and power consumption. The concept of pixel-level ADCs has been proposed. Benefiting from the all-digital pixel outputs, pixel-level ADCs exhibit the obvious merits on noise, speed, insensitive area, and power consumption. In this thesis, a prototype sensor, called MIMADC, has been implemented by a 0.18 μm CIS (CMOS Image Sensor) process. The target of this sensor is to verify the feasibility of the CPS integrated with pixel-level ADCs. Three matrices are included in this prototype but with two different types of pixel-level ADCs: one with successive approximation register (SAR) ADCs, and the other two with single-slope (SS) ADCs. All of them feature a same pixel size of 35×35 μm2 and a resolution of 3-bit. In this thesis, the prototype is presented for both theoretical analyses and…

Advisors/Committee Members: Hu, Yann (thesis director).

Subjects/Keywords: Détection de particules de charge; CPS (CMOS Pixel Sensors); CAN (Convertisseur Analogique-Numérique) au niveau du pixel; ASIC; ILC; ILD; VTX; DPS; Charge particle detection; CPS (CMOS Pixel Sensors),; Pixel-level ADCs (Analog-to-Digital Converters); ASIC (Application Specific Integrated Circuit); ILC (International Linear Collider); ILD (International Large Detector); VTX (Vertex Detector); DPS (Digital Pixel Sensors); 621.38; 539.7

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APA (6^th Edition):

Zhao, W. (2015). Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2015STRAE004

Chicago Manual of Style (16^th Edition):

Zhao, Wei. “Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex.” 2015. Doctoral Dissertation, Université de Strasbourg. Accessed March 04, 2021. http://www.theses.fr/2015STRAE004.

MLA Handbook (7^th Edition):

Zhao, Wei. “Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex.” 2015. Web. 04 Mar 2021.

Vancouver:

Zhao W. Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2015. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2015STRAE004.

Council of Science Editors:

Zhao W. Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex. [Doctoral Dissertation]. Université de Strasbourg; 2015. Available from: http://www.theses.fr/2015STRAE004

10. Petura, Oto. True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation.

Degree: Docteur es, Microélectronique, 2019, Lyon

URL: http://www.theses.fr/2019LYSES053

►

Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour… (more)

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Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour la protection contre les attaques par canaux cachés. Dans cette thèse, nous traitons des générateurs de nombres aléatoires dans les circuits logiques (FPGA et ASIC). Nous présentons les méthodes fondamentales de génération de nombres aléatoires dans des circuits logiques. Ensuite, nous discutons de différents types de TRNG en utilisant le jitter d’horloge comme source d’aléa. Nous faisons une évaluation rigoureuse de divers noyaux TRNG conformes à la norme AIS-20/31 et mis en œuvre dans trois familles de FPGA différentes: Intel Cyclone V, Xilinx Spartan-6 et Microsemi SmartFusion2. Puis, nous présentons l’implémentation des noyaux TRNG sélectionnés dans des ASIC et leur évaluation. Ensuite, nous étudions en profondeur PLL-TRNG afin de fournir une conception sécurisée de ce TRNG ainsi que des tests intégrés. Enfin, nous étudions les TRNG basés sur les oscillateurs. Nous comparons de différentes méthodes d'extraction d’aléa ainsi que de différents types d'oscillateurs et le comportement du jitter d'horloge à l'intérieur de chacun d'eux. Nous proposons également des méthodes de mesure du jitter intégrée pour le test en ligne des TRNG basés sur les oscillateurs.

Random numbers are essential for modern cryptographic systems. They are used as cryptographic keys, nonces, initialization vectors and random masks for protection against side channel attacks. In this thesis, we deal with random number generators in logic devices (Field Programmable Gate Arrays – FPGAs and Application Specific Integrated Circuits – ASICs). We present fundamental methods of generation of random numbers in logic devices. Then, we discuss different types of TRNGs using clock jitter as a source of randomness. We provide a rigorous evaluation of various AIS-20/31 compliant TRNG cores implemented in three different FPGA families : Intel Cyclone V, Xilinx Spartan-6 and Microsemi SmartFusion2. We then present the implementation of selected TRNG cores in custom ASIC and we evaluate them. Next, we study PLL-TRNG in depth in order to provide a secure design of this TRNG together with embedded tests. Finally, we study oscillator based TRNGs. We compare different randomness extraction methods as well as different oscillator types and the behavior of the clock jitter inside each of them. We also propose methods of embedded jitter measurement for online testing of oscillator based TRNGs.

Advisors/Committee Members: Fischer, Viktor (thesis director), Aubert, Alain (thesis director).

Subjects/Keywords: TRNG; Générateur de nombres aléatoires; Tests embarqués; FPGA; ASIC; PLL-TRNG; Gigue; Mesure de la gigue; Réseaux logiques programmables; Clock jitter; Jitter measurement; True Random Number Generator; TRNG; Random number generator; Embedded tests; FPGA; Field Programmable Gate Arrays; ASIC; Application Specific Integrated Circuit; PLL-TRNG; Phase locked-loops - True random number generators

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APA (6^th Edition):

Petura, O. (2019). True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2019LYSES053

Chicago Manual of Style (16^th Edition):

Petura, Oto. “True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation.” 2019. Doctoral Dissertation, Lyon. Accessed March 04, 2021. http://www.theses.fr/2019LYSES053.

MLA Handbook (7^th Edition):

Petura, Oto. “True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation.” 2019. Web. 04 Mar 2021.

Vancouver:

Petura O. True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation. [Internet] [Doctoral dissertation]. Lyon; 2019. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2019LYSES053.

Council of Science Editors:

Petura O. True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation. [Doctoral Dissertation]. Lyon; 2019. Available from: http://www.theses.fr/2019LYSES053

NSYSU

11. Shi, Po-Xu. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.

Degree: Master, Electrical Engineering, 2018, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

► This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference… (more)

Subjects/Keywords: quasi floating gate memory; clock generator; adjustable frequency; application-specific integrated circuit; oscillator

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APA (6^th Edition):

Shi, P. (2018). Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Shi, Po-Xu. “Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.” 2018. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Shi, Po-Xu. “Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.” 2018. Web. 04 Mar 2021.

Vancouver:

Shi P. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi P. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

12. Adarsha Rao, S J. Polymorphic ASIC : For Video Decoding.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/3291

► Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video… (more)

▼ Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a speciﬁc application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degree of reconﬁgurability to accommodate rapid evolution in applications features. In addition, low power consumption requirement is also very stringent for many video applications. The conventional custom hardware implementations of video applications deliver high performance at low power consumption while the recent MPSoC implementations enable high degree of interoperability and are useful to support application evolution. In this thesis, we combine the best features of custom hardware and MPSoC approaches to design a Polymorphic ASIC. A Polymorphic ASIC is an integrated circuit designed to meet the requirements of several applications belonging to a particular domain. A polymorphic ASIC consists of a fabric of computation, storage and communication resources, using which applications are composed dynamically. Although different video applications differ widely in the internal de-tails of operation, at the heart of almost every video application is a video codec (encoder and decoder). The requirements of scalability, high performance and low power consumption are very stringent for video decoding. Therefore this thesis focuses mainly on the architectural design of a Polymorphic ASIC for video decoding. We present an uniﬁed software and hardware architecture (USHA) for Polymorphic ASIC. USHA is a tiled architecture which uses loosely coupled processor and hardware tiles that are software programmable and hardware reconﬁgurable respectively. The distinctive feature of Polymorphic ASIC is the static partitioning of the application and dynamic mapping of ap-plication processes onto the computational tiles. Depending on the application scenarios, a process may be mapped onto one of the hardware or processor tiles. Polymorphic ASIC incor-porates a network–on–chip (NoC) to achieve ﬂexible communication across different tiles. Formulation of a programming framework for Polymorphic ASIC requires an implementation model that captures the structure of video decoder applications as well as the properties of the Polymorphic ASIC architecture. We derive an implementation model based on a combination of parametric polyhedral process networks, stream based functions and windowed dataﬂow models of computation. The implementation model leads to a process network oriented compilation ﬂow that achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi–processor, semi hardware and full… Advisors/Committee Members: Nandy, S K (advisor).

Subjects/Keywords: Application Specific Integrated Circuits (ASIC); Polymorphic ASIC (Applicaion Specific Integrated Circuits); Unified Software and Hardware Architecture (USHA); Video Decoding; Polymorphic ASIC Architecture; Multiprocessor System-On-Chip (MPSoC); H.264 Decoder; Video Encoding; H.264 Decoders; H.264 Decoding; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Adarsha Rao, S. J. (2018). Polymorphic ASIC : For Video Decoding. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3291

Chicago Manual of Style (16^th Edition):

Adarsha Rao, S J. “Polymorphic ASIC : For Video Decoding.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed March 04, 2021. http://etd.iisc.ac.in/handle/2005/3291.

MLA Handbook (7^th Edition):

Adarsha Rao, S J. “Polymorphic ASIC : For Video Decoding.” 2018. Web. 04 Mar 2021.

Vancouver:

Adarsha Rao SJ. Polymorphic ASIC : For Video Decoding. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Mar 04]. Available from: http://etd.iisc.ac.in/handle/2005/3291.

Council of Science Editors:

Adarsha Rao SJ. Polymorphic ASIC : For Video Decoding. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3291

Macquarie University

13. Hossain, Md Selim. High performance hardware implementation of elliptic curve cryptography.

Degree: 2017, Macquarie University

URL: http://hdl.handle.net/1959.14/1261356

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Empirical thesis.

Bibliography: pages 339-362.

1. Introduction – 2. Background – 3. Efficient hardware implementation of finite field arithmetic for elliptic curve cryptography – 4.… (more)

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Empirical thesis.

Bibliography: pages 339-362.

1. Introduction – 2. Background – 3. Efficient hardware implementation of finite field arithmetic for elliptic curve cryptography – 4. High performance FPGA implementation of elliptic curve cryptography processor over binary field GF (2 163) – 5. High-speed area-efficient FGPA-based elliptic curve cryptographic processor over NIST binary fields – 6. Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications – 7. Efficient hardware implementation of elliptic curve cryptography processor over NIST binary fields – 8. FPGA-based efficient modular multiplication for elliptic curve cryptography – 9. High performance FPGA implementation of modular inversion over F256 for elliptic curve cryptography – 10. High performance elliptic curve cryptography processor over NIST prime fields – 11. Energy efficient ASIC-based elliptic curve cryptography processor – 12. Conclusions and future work – appendices – Bibliography.

Elliptic curve cryptography (ECC), a public-key cryptography (PKC) encryption technique, has gained much interest among cryptography researchers because of its advantages over other commonly used PKC algorithms, such as the Rivest,Shamir and Adleman (RSA) cryptosystem. It offers equivalent security to RSA,but with significantly shorter key lengths. This attractive feature makes ECC very popular for resource-constrained applications such as smart cards, creditcards, pagers, personal digital assistants (PDAs), and cellular phones. ECC is considered to be more efficient in terms of speed, area, and power consumption.

This dissertation introduces several hardware implementations of an efficient ECC cryptosystem both on a field-programmable gate array (FPGA) and on an application-specific integrated circuit (ASIC) using VHDL. The first half of this dissertation discusses the high-performance hardware implementation of an ECC over the binary field F2m and the second half describes an efficient implementation of an ECC over the prime field Fp. These are implemented both in affine and Jacobian coordinates using the binary method (i.e. the double-and-add method) and the National Institute of Standards and Technology (NIST) recommended standard. The performance or efficiency of an ECC processor (ECP) is based on elliptic curve scalar (or point) multiplication (ECSM or ECPM) which is the most time and resource consuming operation in either a binary field or a prime field.The aim of this dissertation is to implement an efficient ECPM with a tradeoff between speed, energy, and area complexities, required for modern security applications. Various techniques are introduced to improve the performance of the ECPM, such as parallelisation, pre-computations, algorithm or architectural optimisation, and improved finite-field (or modular) arithmetic architectures. Although there is a substantial amount of work on separate point doubling (PD) and point addition (PA) implementations to compute elliptic…

Advisors/Committee Members: Macquarie University. School of Engineering.

Subjects/Keywords: Public key cryptography; Curves, Elliptic – Industrial applications; elliptic curve cryptography (ECC); finite field arithmetic (FFA); point doubling (PD); point addition (PA); point doubling and point addition (PDPA); elliptic curve point multiplication (ECPM); ECC processor (ECP); application-specific integrated circuit (ASIC); field-programmable gate array (FPGA); Natonal Institute of Standards and Technology (NIST)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hossain, M. S. (2017). High performance hardware implementation of elliptic curve cryptography. (Doctoral Dissertation). Macquarie University. Retrieved from http://hdl.handle.net/1959.14/1261356

Chicago Manual of Style (16^th Edition):

Hossain, Md Selim. “High performance hardware implementation of elliptic curve cryptography.” 2017. Doctoral Dissertation, Macquarie University. Accessed March 04, 2021. http://hdl.handle.net/1959.14/1261356.

MLA Handbook (7^th Edition):

Hossain, Md Selim. “High performance hardware implementation of elliptic curve cryptography.” 2017. Web. 04 Mar 2021.

Vancouver:

Hossain MS. High performance hardware implementation of elliptic curve cryptography. [Internet] [Doctoral dissertation]. Macquarie University; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1959.14/1261356.

Council of Science Editors:

Hossain MS. High performance hardware implementation of elliptic curve cryptography. [Doctoral Dissertation]. Macquarie University; 2017. Available from: http://hdl.handle.net/1959.14/1261356

University of Cincinnati

14. Chadha, Vishal. Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.

Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992

► One limitation of current FPGAs is that the user is limited to strictly digital electronic designs and are not suitable for multi-technology applications. In 2002,… (more)

Subjects/Keywords: ASIC; Application specific integrated circuit; CMOS; Complementary Metal Oxide Semiconductor. Technology used to manufacture silicon; integrated circuits; Delay flip-flop or D-flop; The input is copied to the output delayed by one clock cycle; FPGA

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APA (6^th Edition):

Chadha, V. (2005). Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992

Chicago Manual of Style (16^th Edition):

Chadha, Vishal. “Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.” 2005. Masters Thesis, University of Cincinnati. Accessed March 04, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

MLA Handbook (7^th Edition):

Chadha, Vishal. “Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.” 2005. Web. 04 Mar 2021.

Vancouver:

Chadha V. Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays. [Internet] [Masters thesis]. University of Cincinnati; 2005. [cited 2021 Mar 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

Council of Science Editors:

Chadha V. Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays. [Masters Thesis]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992

15. Li, Bo. Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies.

Degree: Docteur es, Génie électrique, 2012, INSA Lyon

URL: http://www.theses.fr/2012ISAL0036

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Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de… (more)

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Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35µm: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.

Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple…

Advisors/Committee Members: Allard, Bruno (thesis director), Lin-Shi, Xuefang (thesis director).

Subjects/Keywords: Électronique de puissance; Convertisseur à découpage; Convertisseur DC-DC; Commande électronique; Contrôle logique digital; Contrôleur numérique; SMPS - switching-mode power supply; Commande prédictive; DPWM - Digital pulse-width modulator; PwrSoC - Power supply-on-chip; Abaisseur de tension; Contrôleur PID linéaire; Commande par modes glissants; Prototype ASIC; Processeur ASIC; Power Electronics; Cutting Converter; Switched-mode power Converter; DC-to-DC Converter; Electronic Control; Digital Logic Monitoring; SMPS - switching-mode power supply; Feed Forward Control; DPWM - Digital pulse-width modulator; PwrSoC - Power supply-on-chip; ASIC - Application Specific Integrated Circuit - Processor; 621.381 044 072

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, B. (2012). Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2012ISAL0036

Chicago Manual of Style (16^th Edition):

Li, Bo. “Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies.” 2012. Doctoral Dissertation, INSA Lyon. Accessed March 04, 2021. http://www.theses.fr/2012ISAL0036.

MLA Handbook (7^th Edition):

Li, Bo. “Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies.” 2012. Web. 04 Mar 2021.

Vancouver:

Li B. Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies. [Internet] [Doctoral dissertation]. INSA Lyon; 2012. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2012ISAL0036.

Council of Science Editors:

Li B. Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies. [Doctoral Dissertation]. INSA Lyon; 2012. Available from: http://www.theses.fr/2012ISAL0036

16. Yang, Gangqiang. Optimized Hardware Implementations of Lightweight Cryptography.

Degree: 2017, University of Waterloo

URL: http://hdl.handle.net/10012/11237

► Radio frequency identification (RFID) is a key technology for the Internet of Things era. One important advantage of RFID over barcodes is that line-of-sight is… (more)

▼ Radio frequency identification (RFID) is a key technology for the Internet of Things era. One important advantage of RFID over barcodes is that line-of-sight is not required between readers and tags. Therefore, it is widely used to perform automatic and unique identification of objects in various applications, such as product tracking, supply chain management, and animal identification. Due to the vulnerabilities of wireless communication between RFID readers and tags, security and privacy issues are significant challenges. The most popular passive RFID protocol is the Electronic Product Code (EPC) standard. EPC tags have many constraints on power consumption, memory, and computing capability. The field of lightweight cryptography was created to provide secure, compact, and flexible algorithms and protocols suitable for applications where the traditional cryptographic primitives, such as AES, are impractical. In these lightweight algorithms, tradeoffs are made between security, area/power consumption, and throughput. In this thesis, we focus on the hardware implementations and optimizations of lightweight cryptography and present the Simeck block cipher family, the WG-8 stream cipher, the Warbler pseudorandom number generator (PRNG), and the WGLCE cryptographic engine. Simeck is a new family of lightweight block ciphers. Simeck takes advantage of the good components and design ideas of the Simon and Speck block ciphers and it has three instances with different block and key sizes. We provide an extensive exploration of different hardware architectures in ASICs and show that Simeck is smaller than Simon in terms of area and power consumption. For the WG-8 stream cipher, we explore four different approaches for the WG transformation module, where one takes advantage of constant arrays and the other three benefit from the tower field constructions of the finite field \F_2⁸ and also efficient basis conversion matrices. The results in FPGA and ASICs show that the constant arrays based method is the best option. We also propose a hybrid design to improve the throughput with a little additional hardware. For the Warbler PRNG, we present the first detailed and smallest hardware implementations and optimizations. The results in ASICs show that the area of Warbler with throughput of 1 bit per 5 clock cycles (1/5 bpc) is smaller than that of other PRNGs and is in fact smaller than that of most of the lightweight primitives. We also optimize and improve the throughput from 1/5 bpc to 1 bpc with a little additional area and power consumption. Finally, we propose a cryptographic engine WGLCE for passive RFID systems. We merge the Warbler PRNG and WG-5 stream cipher together by reusing the finite state machine for both of them. Therefore, WGLCE can provide data confidentiality and generate pseudorandom numbers. After investigating the design rationales and hardware architectures, our results in ASICs show that WGLCE meets the constraints of passive RFID systems.

Subjects/Keywords: Lightweight Cryptography; Hardware Implementations; Hardware Optimizations; Field Programmable Gate Array (FPGA); Application Specific Integrated Circuit (ASIC); Radio Frequency IDentification (RFID); Block Cipher; Stream Cipher; Pseudorandom Number Generator (PRNG)

…smallest available hardware implementation of AES in CMOS 180nm Application Specific Integrated… …Circuit (ASIC) requires 2400 GEs [82]. In order to overcome this challenge… …approaches for cryptographic primitives. 2.4.1 Hardware Implementations Application specific… …Implementations and Results . . . . . . . . . . . . . . . . . . . . 72 4.4.3 ASIC Implementations and… …80 5.2 ASIC Architecture…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, G. (2017). Optimized Hardware Implementations of Lightweight Cryptography. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yang, Gangqiang. “Optimized Hardware Implementations of Lightweight Cryptography.” 2017. Thesis, University of Waterloo. Accessed March 04, 2021. http://hdl.handle.net/10012/11237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yang, Gangqiang. “Optimized Hardware Implementations of Lightweight Cryptography.” 2017. Web. 04 Mar 2021.

Vancouver:

Yang G. Optimized Hardware Implementations of Lightweight Cryptography. [Internet] [Thesis]. University of Waterloo; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10012/11237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang G. Optimized Hardware Implementations of Lightweight Cryptography. [Thesis]. University of Waterloo; 2017. Available from: http://hdl.handle.net/10012/11237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

17. Bagga, Shobi. Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing.

Degree: MSc Engg, Faculty of Engineering, 2009, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/474

► The widespread use of Liquid Petroleum Gas (LPG) for cooking and as fuel for automobile vehicles requires fast and selective detection of LPG to precisely… (more)

▼ The widespread use of Liquid Petroleum Gas (LPG) for cooking and as fuel for automobile vehicles requires fast and selective detection of LPG to precisely measure the leakage of gas for preventing the occurrence of accidental explosions. The adoption of Micro-Electro-Mechanical-System (MEMS) technology for fabricating the gas sensor provides other potential advantages for sensing applications, which includes low power consumption, low fabrication cost, high quality, small size and reliability. MEMS based gas sensor requires a sensitive layer of oxide material like ZnO, SnO2, TiO2, Fe2O3, etc. The tin oxide material used in the present work changes its electrical properties, as it interacts with the reducing gas like LPG. The sensor material becomes active only at high temperature such as 400ºC, thereby realizing the need of a micro heater to reach the desired temperature. To control the temperature of micro heater and to determine the change in electrical properties of the sensor due to its interaction with LPG an Application Specific Integrated Circuit (ASIC) forms an essential constituent of the MEMS based gas sensor. In the present work, an attempt has been made to improve the sensitivity of LPG gas sensor and it is correlated with other properties by different characterization techniques. The work also includes the design as well as testing of ASIC for gas sensor system. Process parameters particularly deposition time and substrate temperature have a profound influence on the microstructure of the tin oxide film, which in turn affects the gas sensing properties. To study the effects of these parameters, RF magnetron sputtering system is used for depositing tin oxide films onto the silicon substrate, which is compatible with CMOS technology. The effects of structural properties, optical properties and the porosity of the films are also studied and correlated with the gas sensing properties. In this direction the deposited films are characterized using X-Ray Diffraction (XRD) to determine the structure orientation. The morphology of the sensor films are analyzed by Scanning Electron Microscope (SEM) while the refractive index, thickness and porosity of the films are determined using ellipsometry studies. The thickness of the deposited films is also confirmed by the surface profilometer. The change in composition of the deposited film along its depth is determined using Secondary Ion Mass Spectrometer (SIMS). Maximum sensitivity 5.5 is obtained for 470 nm thick films, which corresponds to a grain size of 38nm at the operating temperature of 4000C. Following these studies, an ASIC has been designed using Tanner EDA Tools on AMIS 0.7 µm CMOS process, fabricated through Euro practice’s ASIC prototyping service, Belgium and tested successfully after fabrication. The temperature control module of ASIC has been designed using relaxation oscillator technique to control the temperature of the in house developed heater. The resistance to period conversion technique is explored for the design of the sensor read out module of… Advisors/Committee Members: Mohan, S (advisor), Bhat, Navakanta (advisor).

Subjects/Keywords: Electronic Devices; Gas Sensors; Sensor Film Deposition; Tin Oxide Films - Properties; Application Specific Integrated Circuit (ASIC); Tin Oxide Gas Sensor; Tin Oxide Films - Deposition; Gas Sensor System; Instrumentation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bagga, S. (2009). Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/474

Chicago Manual of Style (16^th Edition):

Bagga, Shobi. “Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing.” 2009. Masters Thesis, Indian Institute of Science. Accessed March 04, 2021. http://etd.iisc.ac.in/handle/2005/474.

MLA Handbook (7^th Edition):

Bagga, Shobi. “Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing.” 2009. Web. 04 Mar 2021.

Vancouver:

Bagga S. Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing. [Internet] [Masters thesis]. Indian Institute of Science; 2009. [cited 2021 Mar 04]. Available from: http://etd.iisc.ac.in/handle/2005/474.

Council of Science Editors:

Bagga S. Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing. [Masters Thesis]. Indian Institute of Science; 2009. Available from: http://etd.iisc.ac.in/handle/2005/474

18. York, Johnathan Andrew. Multiple personality integrated circuits and the cost of programmability.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

URL: http://hdl.handle.net/2152/ETD-UT-2011-05-2676

► This dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication… (more)

Subjects/Keywords: Programmability; Integrated circuit; ASIC; FPGA

…Application Details . . . . . . . . . . . . . . . . . . . . . . . . 101 ASIC Implementation… …engineering costs forming a substantial component of device cost for many Application Specific… …outweigh the incremental fabrication costs of large scale integrated circuit fabrication. In… …function circuit implementation of a computation that exceeds a specific set of performance… …102 4.3.1 Input Circuit Baselines . . . . . . . . . . . . . . . . . . . . . 102 4.3.2…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

York, J. A. (2011). Multiple personality integrated circuits and the cost of programmability. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-2676

Chicago Manual of Style (16^th Edition):

York, Johnathan Andrew. “Multiple personality integrated circuits and the cost of programmability.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed March 04, 2021. http://hdl.handle.net/2152/ETD-UT-2011-05-2676.

MLA Handbook (7^th Edition):

York, Johnathan Andrew. “Multiple personality integrated circuits and the cost of programmability.” 2011. Web. 04 Mar 2021.

Vancouver:

York JA. Multiple personality integrated circuits and the cost of programmability. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-2676.

Council of Science Editors:

York JA. Multiple personality integrated circuits and the cost of programmability. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-2676

19. Ranganathan, Lavakumar. Sensor-array chip hybrid for simultaneous multiple analyte detection.

Degree: PhD, 2007, Oregon Health Sciences University

URL: doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154

Subjects/Keywords: Biosensors – Research; Application specific integrated circuits; Lab-on-chip; LOC; E-nose; Sensor array; Hybrid; Asic; Integrated chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ranganathan, L. (2007). Sensor-array chip hybrid for simultaneous multiple analyte detection. (Doctoral Dissertation). Oregon Health Sciences University. Retrieved from doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154

Chicago Manual of Style (16^th Edition):

Ranganathan, Lavakumar. “Sensor-array chip hybrid for simultaneous multiple analyte detection.” 2007. Doctoral Dissertation, Oregon Health Sciences University. Accessed March 04, 2021. doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154.

MLA Handbook (7^th Edition):

Ranganathan, Lavakumar. “Sensor-array chip hybrid for simultaneous multiple analyte detection.” 2007. Web. 04 Mar 2021.

Vancouver:

Ranganathan L. Sensor-array chip hybrid for simultaneous multiple analyte detection. [Internet] [Doctoral dissertation]. Oregon Health Sciences University; 2007. [cited 2021 Mar 04]. Available from: doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154.

Council of Science Editors:

Ranganathan L. Sensor-array chip hybrid for simultaneous multiple analyte detection. [Doctoral Dissertation]. Oregon Health Sciences University; 2007. Available from: doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154

York University

20. Zhao, Yang. Low Power Circuits for Smart Flexible ECG Sensors.

Degree: PhD, Computer Science, 2020, York University

URL: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346

► Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor… (more)

▼ Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W. Advisors/Committee Members: Lian, Yong Peter (advisor).

Subjects/Keywords: Biomedical engineering; Electrocardiogram (ECG); Analog Front-end; QRS detector; Cardiac Arrhythmia Classifier; Low power; Common mode rejection ratio (CMRR); Noise efficiency factor (NEF); Application specific integrated circuits (ASIC); DC-coupled; Patient-specific; Classification accuracy; Low noise; Flexible ECG sensor; Sensor interface circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhao, Y. (2020). Low Power Circuits for Smart Flexible ECG Sensors. (Doctoral Dissertation). York University. Retrieved from https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346

Chicago Manual of Style (16^th Edition):

Zhao, Yang. “Low Power Circuits for Smart Flexible ECG Sensors.” 2020. Doctoral Dissertation, York University. Accessed March 04, 2021. https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346.

MLA Handbook (7^th Edition):

Zhao, Yang. “Low Power Circuits for Smart Flexible ECG Sensors.” 2020. Web. 04 Mar 2021.

Vancouver:

Zhao Y. Low Power Circuits for Smart Flexible ECG Sensors. [Internet] [Doctoral dissertation]. York University; 2020. [cited 2021 Mar 04]. Available from: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346.

Council of Science Editors:

Zhao Y. Low Power Circuits for Smart Flexible ECG Sensors. [Doctoral Dissertation]. York University; 2020. Available from: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346

Brno University of Technology

21. Dvořák, Vojtěch. Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/27112

► The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation… (more)

Subjects/Keywords: Číslicové zpracování signálu; diskrétní Fourierova transformace; rychlá Fourierova transformace; DFT; FFT; VHDL; programovatelné logické obvody; FPGA; zákaznické obvody; ASIC; verifikace; syntéza digitálních obvodů; Digital signal processing; discrete Fourier transform; fast Fourier transform; DFT; FFT; VHDL; programable logic circuits; FPGA; application-specified integrated circuit; ASIC; verification; synthesis of digital circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Dvořák, V. (2019). Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/27112

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Dvořák, Vojtěch. “Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/27112.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Dvořák, Vojtěch. “Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC.” 2019. Web. 04 Mar 2021.

Vancouver:

Dvořák V. Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/27112.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dvořák V. Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/27112

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Sul

22. Bavaresco, Simone. On-silicon testbench for validation of soft logic cell libraries.

Degree: 2008, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/14907

►

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células… (more)

▼

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’.

Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit…

Advisors/Committee Members: Ribas, Renato Perez.

Subjects/Keywords: Integrated circuit; Microeletrônica; ASIC; Testes : Circuitos integrados; Digital design; Standard cell; Library-free technology mapping; Soft library; Test circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bavaresco, S. (2008). On-silicon testbench for validation of soft logic cell libraries. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/14907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Bavaresco, Simone. “On-silicon testbench for validation of soft logic cell libraries.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed March 04, 2021. http://hdl.handle.net/10183/14907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Bavaresco, Simone. “On-silicon testbench for validation of soft logic cell libraries.” 2008. Web. 04 Mar 2021.

Vancouver:

Bavaresco S. On-silicon testbench for validation of soft logic cell libraries. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10183/14907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bavaresco S. On-silicon testbench for validation of soft logic cell libraries. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/14907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

23. Kala, S. ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor.

Degree: MSc Engg, Faculty of Engineering, 2016, Indian Institute of Science

URL: http://etd.iisc.ac.in/handle/2005/2557

► The rapid advancements in semiconductor technology have led to constant shrinking of transistor sizes as per Moore's Law. Wireless communications is one field which has… (more)

▼ The rapid advancements in semiconductor technology have led to constant shrinking of transistor sizes as per Moore's Law. Wireless communications is one field which has seen explosive growth, thanks to the cramming of more transistors into a single chip. Design of these systems involve trade-offs between performance, area and power. Fast Fourier Transform is an important component in most of the wireless communication systems. FFTs are widely used in applications like OFDM transceivers, Spectrum sensing in Cognitive Radio, Image Processing, Radar Signal Processing etc. FFT is the most compute intensive and time consuming operation in most of the above applications. It is always a challenge to develop an architecture which gives high throughput while reducing the latency without much area overhead. Next generation wireless systems demand high transmission efficiency and hence FFT processor should be capable of doing computations much faster. Architectures based on smaller radices for computing longer FFTs are inefficient. In this thesis, a fully parallel unrolled FFT architecture based on novel radix-4 engine is proposed which is catered for wide range of applications. The radix-4 butterfly unit takes all four inputs in parallel and can selectively produce one out of the four outputs. The proposed architecture uses Radix-4³ and Radix-4⁴ algorithms for computation of various FFTs. The Radix-4⁴ block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. In existing Cooley-Tukey architectures, the output from each stage has to be reordered before the next stage can start computation. This needs intermediate storage after each stage. In our architecture, each stage can directly generate the reordered outputs and hence reduce these buffers. A solution for output reordering problem in Radix-4³ and Radix-4⁴ FFT architectures are also discussed in this work. Although the hardware complexity in terms of adders and multipliers are increased in our architecture, a significant reduction in intermediate memory requirement is achieved. FFTs of varying sizes starting from 64 point to 64K point have been implemented in ASIC using UMC 130nm CMOS technology. The data representation used in this work is fixed point format and selected word length is 16 bits to get maximum Signal to Quantization Noise Ratio (SQNR). The architecture has been found to be more suitable for computing FFT of large sizes. For 4096 point and 64K point FFTs, this design gives comparable throughput with considerable reduction in area and latency when compared to the state-of-art implementations. The 64K point FFT architecture resulted in a throughput of 1332 mega samples per second with an area of 171.78 mm² and total power of 10.7W at 333 MHz. Advisors/Committee Members: Nandy, S K (advisor), Jamadagni, H S (advisor).

Subjects/Keywords: Wireless Communication Systems; Fast Fourier Transformation Processor; Fast Fourier Transform Archirecture; Fast Fourier Transform - Algorithms; Application Specific Integrated Circuit; FFT Processor; FFT Architecture; Orthogonal Frequency Division Multiplexing (OFDM); Communication Engineering

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APA (6^th Edition):

Kala, S. (2016). ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2557

Chicago Manual of Style (16^th Edition):

Kala, S. “ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor.” 2016. Masters Thesis, Indian Institute of Science. Accessed March 04, 2021. http://etd.iisc.ac.in/handle/2005/2557.

MLA Handbook (7^th Edition):

Kala, S. “ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor.” 2016. Web. 04 Mar 2021.

Vancouver:

Kala S. ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor. [Internet] [Masters thesis]. Indian Institute of Science; 2016. [cited 2021 Mar 04]. Available from: http://etd.iisc.ac.in/handle/2005/2557.

Council of Science Editors:

Kala S. ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor. [Masters Thesis]. Indian Institute of Science; 2016. Available from: http://etd.iisc.ac.in/handle/2005/2557

New Jersey Institute of Technology

24. Gururaj, Kiran K. On chip implement of deadlock avoidance in wormhole networks.

Degree: MSin Electrical Engineering - (M.S.), Electrical and Computer Engineering, 2002, New Jersey Institute of Technology

URL: https://digitalcommons.njit.edu/theses/696

► This thesis gives a detailed description of the Application Specific Integrated Circuit (ASIC) design to avoid deadlocks in Wormhole Networks. Deadlock avoidance is the… (more)

Subjects/Keywords: Application specific integrated circuit; Wormhole networks; DeadLock Avoidance; Electrical and Electronics

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APA (6^th Edition):

Gururaj, K. K. (2002). On chip implement of deadlock avoidance in wormhole networks. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/696

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Gururaj, Kiran K. “On chip implement of deadlock avoidance in wormhole networks.” 2002. Thesis, New Jersey Institute of Technology. Accessed March 04, 2021. https://digitalcommons.njit.edu/theses/696.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Gururaj, Kiran K. “On chip implement of deadlock avoidance in wormhole networks.” 2002. Web. 04 Mar 2021.

Vancouver:

Gururaj KK. On chip implement of deadlock avoidance in wormhole networks. [Internet] [Thesis]. New Jersey Institute of Technology; 2002. [cited 2021 Mar 04]. Available from: https://digitalcommons.njit.edu/theses/696.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gururaj KK. On chip implement of deadlock avoidance in wormhole networks. [Thesis]. New Jersey Institute of Technology; 2002. Available from: https://digitalcommons.njit.edu/theses/696

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Bellasi, David E. Toward Energy-Proportional Compressive Sensors.

Degree: 2018, ETH Zürich

URL: http://hdl.handle.net/20.500.11850/283900

► The vision of the Internet of things (IoT) entails the connection of all possible objects to the Internet for the purpose of monitoring and actuation,… (more)

▼ The vision of the Internet of things (IoT) entails the connection of all possible objects to the Internet for the purpose of monitoring and actuation, and its realization requires sensing devices that are highly optimized in terms of performance, size, cost, and energy-efficiency. The IoT is one of the main drivers for the exponential growth of the number of wireless electronic devices produced and sold worldwide. To ensure the economic and ecologic feasibility of the IoT, in addition to the improvement of known techniques to acquire, process, and communicate information, the pursuit of innovative and unconventional methods is needed. Compressive sensing (CS) was proposed as a groundbreaking signal acquisition method that fuses sampling and compression in a single procedure, and thereby potentially reduces the energy cost of both acquisition and transmission of information with respect to the conventional combination of Nyquist-rate sampling and digital data compression. The theory of CS – due to much excited research activity in the past years – has reached a certain maturity, whereas the knowledge about the performance and limitations of CS in practical applications and under real-world conditions is still fragmentary and not well consolidated. The goal of this thesis is the quantitative assessment of the quality/compression trade-off, the hardware complexity and power consumption of CS-based signal acquisition systems for typical low-rate IoT sensor applications, such as biomedical and environmental monitoring. Related work in the field was primarily concerned with demonstrating the potential of CS with respect to conventional signal acquisition producing uncompressed data. In contrast, in this thesis the performance of CS techniques is confronted with the performance of well-established conventional compression techniques under realistic conditions. The investigation is conducted empirically, analyzing compressive sensor systems based not only on mathematical models but based on measurement results from fabricated prototypes of integrated mixed-signal sensor systems. In the first part of this thesis, the theory of CS is reviewed with emphasis on theoretical bounds relevant for its practical application, limitations are identified, and possible remedies are proposed. The advantages and disadvantages of different CS signal acquisition modalities based on analog or digital signal processing are contemplated – both on theoretical and empirical grounds – and the difference between them in terms of quality/compression trade-off is quantified. In a second part, mathematical power estimation models for compressive sensors are developed and employed to quantify the energy-efficiency of different compressive sensor architectures. The scope of the discussion is extended from the confrontation of different CS implementations to the comparison of CS-based and conventional compression methods on the system-level of abstraction. The subject of a third part is the empirical verification of the observations and results of… Advisors/Committee Members: Benini, Luca, id_orcid0000-0001-8068-3806, Studer, Christoph.

Subjects/Keywords: Compressive sensing (CS); Internet of things (IoT); wireless sensors; data compression; microelectronics; application specific integrated circuits (ASIC); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/4; info:eu-repo/classification/ddc/621.3; Electric engineering; Data processing, computer science; Electric engineering

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APA (6^th Edition):

Bellasi, D. E. (2018). Toward Energy-Proportional Compressive Sensors. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/283900

Chicago Manual of Style (16^th Edition):

Bellasi, David E. “Toward Energy-Proportional Compressive Sensors.” 2018. Doctoral Dissertation, ETH Zürich. Accessed March 04, 2021. http://hdl.handle.net/20.500.11850/283900.

MLA Handbook (7^th Edition):

Bellasi, David E. “Toward Energy-Proportional Compressive Sensors.” 2018. Web. 04 Mar 2021.

Vancouver:

Bellasi DE. Toward Energy-Proportional Compressive Sensors. [Internet] [Doctoral dissertation]. ETH Zürich; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/20.500.11850/283900.

Council of Science Editors:

Bellasi DE. Toward Energy-Proportional Compressive Sensors. [Doctoral Dissertation]. ETH Zürich; 2018. Available from: http://hdl.handle.net/20.500.11850/283900

26. Rachamadugu, Arun. Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

URL: http://hdl.handle.net/1853/26603

► A method to implement high-speed pulse shaping filters has been discussed. This technique uses a unique look up table based architecture implemented in 90nm CMOS… (more)

Subjects/Keywords: ASIC implementation; SPI interface; Raised cosine FIR; Pulse shaping; Digital filters (Mathematics); Application-specific integrated circuits

…cell based ASIC flow. This method enables the implementation of pulse shaping filters for… …detail along with circuit level descriptions and timing diagrams describing the circuit… …can be easily integrated on silicon making them ideal for system on chip designs. FIR… …table with precalculated outcomes in even and odd paths 7 CHAPTER III ASIC IMPLEMENTATION… …In this chapter the specific details of all the steps involved in the design, from…

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APA (6^th Edition):

Rachamadugu, A. (2008). Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26603

Chicago Manual of Style (16^th Edition):

Rachamadugu, Arun. “Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design.” 2008. Masters Thesis, Georgia Tech. Accessed March 04, 2021. http://hdl.handle.net/1853/26603.

MLA Handbook (7^th Edition):

Rachamadugu, Arun. “Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design.” 2008. Web. 04 Mar 2021.

Vancouver:

Rachamadugu A. Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1853/26603.

Council of Science Editors:

Rachamadugu A. Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26603

North Carolina State University

27. Chandra, Dhruba. Speech Recognition Co-processor.

Degree: PhD, Computer Engineering, 2008, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/3421

► With computing trend moving towards ubiquitous computing propelled by the advances in embedded mobile processors and battery technology, speech recognition is becoming an essential part… (more)

▼ With computing trend moving towards ubiquitous computing propelled by the advances in embedded mobile processors and battery technology, speech recognition is becoming an essential part of embedded processor I⁄O device. Speech recognition is also used in command and control and automated customer service. Real time speech recognition application is both computation and memory intensive and it overwhelms even a high end multi-gigahertz processor to achieve real time performance. An embedded mobile device cannot support real time large vocabulary speech recognition application as the processors are less aggressive because of tighter power budget. Hardware solution to speech recognition, in the past, have mainly concentrated on buidling specialized hardware or ASIC accelerators to run software speech application faster but have largely ignored design for large vocabulary and power reduction. In this work, we propose a hardware-software co-design for real time large vocabulary speech recognition. Our design has custom ASIC blocks and RAM memories and a low power processor. The processor maintains a high level control over the blocks and processes parts of speech recognition application which is not computation and memory intensive. The custom ASIC computes the Gaussian probability and performs word search in the dictionary. The RAMs are used for storing the intermediate values and states. The design can handle large vocabulary speech recognition in real time on a mobile embedded device. Our word search uses innovative dictionary word layout in memory which reduces bandwidth by a factor of 11 compared to software implementation and by a factor of 4 compared to other ASIC implementation. One unit of our proposed design can perform 4x and 20x better than other proposed design of specialized hardware design for software speech application in computing the Gaussian probability and word search, respectively. Advisors/Committee Members: Dr Paul Franzon, Committee Chair (advisor), Dr. R. Rodman, Committee Member (advisor), Dr E. Rotenberg, Committee Member (advisor), Dr. W. Rhett Davis, Committee Member (advisor).

Subjects/Keywords: Application Specific; Low Power; ASIC; Speech Recognition

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APA (6^th Edition):

Chandra, D. (2008). Speech Recognition Co-processor. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3421

Chicago Manual of Style (16^th Edition):

Chandra, Dhruba. “Speech Recognition Co-processor.” 2008. Doctoral Dissertation, North Carolina State University. Accessed March 04, 2021. http://www.lib.ncsu.edu/resolver/1840.16/3421.

MLA Handbook (7^th Edition):

Chandra, Dhruba. “Speech Recognition Co-processor.” 2008. Web. 04 Mar 2021.

Vancouver:

Chandra D. Speech Recognition Co-processor. [Internet] [Doctoral dissertation]. North Carolina State University; 2008. [cited 2021 Mar 04]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3421.

Council of Science Editors:

Chandra D. Speech Recognition Co-processor. [Doctoral Dissertation]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3421

Nelson Mandela Metropolitan University

28. [No author]. Total ionizing dose and single event upset testing of flash based field programmable gate arrays.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2015, Nelson Mandela Metropolitan University

URL: http://hdl.handle.net/10948/12548

► The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private… (more)

▼ The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.

Subjects/Keywords: Field programmable gate arrays; Application-specific integrated circuits

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APA (6^th Edition):

author], [. (2015). Total ionizing dose and single event upset testing of flash based field programmable gate arrays. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/12548

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

author], [No. “Total ionizing dose and single event upset testing of flash based field programmable gate arrays.” 2015. Thesis, Nelson Mandela Metropolitan University. Accessed March 04, 2021. http://hdl.handle.net/10948/12548.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

author], [No. “Total ionizing dose and single event upset testing of flash based field programmable gate arrays.” 2015. Web. 04 Mar 2021.

Vancouver:

author] [. Total ionizing dose and single event upset testing of flash based field programmable gate arrays. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2015. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10948/12548.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Total ionizing dose and single event upset testing of flash based field programmable gate arrays. [Thesis]. Nelson Mandela Metropolitan University; 2015. Available from: http://hdl.handle.net/10948/12548

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Rutgers University

29. Sethuram, Rajamani. Reducing digital test volume using test point insertion.

Degree: PhD, Electrical and Computer Engineering, 2008, Rutgers University

URL: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215

►

Test cost accounts for more than 40% of the entire cost for making a chip. This figure is expected to grow even higher in the… (more)

▼

Test cost accounts for more than 40% of the entire cost for making a chip. This figure is expected to grow even higher in the future. Two major factors that determine test cost are a) test volume and b) test application time. Several techniques such as compaction and compression have been proposed in the past to keep the test cost under an acceptable limit. However, due to the ever increasing size of today's digital very large scale integrated circuits, all prior known test cost reduction techniques are unable to keep the test cost under control. In this dissertation, we present a new test point insertion (TPI) technique for regular cell-based application specific integrated chips (ASICs) and structured ASIC designs. The proposed technique can drastically reduce the test volume, the test application time and the test generation time. The TPI scheme facilitates the compression and the compaction algorithm to reduce test volume and test application time. By facilitating the automatic test pattern generation (ATPG) algorithm, we also reduce the test generation time. Test points are inserted using timing information, so they do not degrade performance. We present novel gain functions that quantify the reduction in test volume and ATPG time due to TPI and are used as heuristics to guide the selection of signal lines for inserting test points. We, then, show how test point insertion can be used to enhance the performance of a broadcast scan-based compressor. To further improve its performance, we use a new scan chain re-ordering algorithm to break the correlation that exists among different signal lines in the circuit due to a particular scan chain order. Experiments conducted with ISCAS '89, ITC '99, and few industrial benchmarks clearly demonstrate the effectiveness and scalability of the proposed technique. By using very little extra hardware for implementing test points and very little extra run time for the TPI step, we show that the test volume and test application can be reduced by up to 64.5% and test generation time can be reduced by up to 63.1% for structured ASIC designs. For the cell-based ASICs with broadcast scan compressors, experiments indicate that the proposed technique improves the compression by up to 46.6% and also reduces the overall ATPG CPU time by up to 49.3%.

Advisors/Committee Members: Sethuram, Rajamani (author), Bushnell, Michael (dissertation committee chair), Meer, Peter (internal member), Parashar, Manish (internal member), RABINER, LAWRENCE (internal member), Chakraborty, Tapan (outside member), Chakradhar, Srimat (outside member).

Subjects/Keywords: Application-specific integrated circuits; Integrated circuits

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APA (6^th Edition):

Sethuram, R. (2008). Reducing digital test volume using test point insertion. (Doctoral Dissertation). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215

Chicago Manual of Style (16^th Edition):

Sethuram, Rajamani. “Reducing digital test volume using test point insertion.” 2008. Doctoral Dissertation, Rutgers University. Accessed March 04, 2021. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215.

MLA Handbook (7^th Edition):

Sethuram, Rajamani. “Reducing digital test volume using test point insertion.” 2008. Web. 04 Mar 2021.

Vancouver:

Sethuram R. Reducing digital test volume using test point insertion. [Internet] [Doctoral dissertation]. Rutgers University; 2008. [cited 2021 Mar 04]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215.

Council of Science Editors:

Sethuram R. Reducing digital test volume using test point insertion. [Doctoral Dissertation]. Rutgers University; 2008. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215

30. Park, Chang Joon. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.

Degree: 2013, Texas Digital Library

URL: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

► Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal… (more)

▼ Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (????) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ???? ADCs allow elimination of the anti???aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ???? ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high???speed and low???power applications. In addition, CT ???? ADCs achieve high resolution due to the ???? modulator???s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ???? modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)???order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ???? modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ???? modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and… Advisors/Committee Members: Silva-Martinez, Jose (advisor).

Subjects/Keywords: Integrated Circuit

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APA (6^th Edition):

Park, C. J. (2013). Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. (Thesis). Texas Digital Library. Retrieved from http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Park, Chang Joon. “Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.” 2013. Thesis, Texas Digital Library. Accessed March 04, 2021. http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Park, Chang Joon. “Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.” 2013. Web. 04 Mar 2021.

Vancouver:

Park CJ. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. [Internet] [Thesis]. Texas Digital Library; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park CJ. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. [Thesis]. Texas Digital Library; 2013. Available from: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations