Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Application specific integrated circuit ASIC ). Showing records 1 – 30 of 25470 total matches.

[1] [2] [3] [4] [5] … [849]

Search Limiters

Last 2 Years | English Only

Degrees

Languages

Country

▼ Search Limiters


University of Illinois – Urbana-Champaign

1. Assem, Pourya. In-sensor information processing for resource-limited platforms on flexible epidermal substrates.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Moving towards the age of big data, the demand for embedded processing has been drastically increasing to make inference and intelligent decisions at lower architectural… (more)

Subjects/Keywords: Application-specific integrated circuit (ASIC); Integrated circuit (IC); Near-field communication (NFC); Pan-Tompkins Algorithm (PTA); Photoplethysmogram (PPG); Epidermal electronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Assem, P. (2016). In-sensor information processing for resource-limited platforms on flexible epidermal substrates. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Assem, Pourya. “In-sensor information processing for resource-limited platforms on flexible epidermal substrates.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/95628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Assem, Pourya. “In-sensor information processing for resource-limited platforms on flexible epidermal substrates.” 2016. Web. 04 Mar 2021.

Vancouver:

Assem P. In-sensor information processing for resource-limited platforms on flexible epidermal substrates. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/95628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Assem P. In-sensor information processing for resource-limited platforms on flexible epidermal substrates. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Chuang, Sheng-Chih. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.

Degree: Master, Electrical Engineering, 2015, NSYSU

 This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a… (more)

Subjects/Keywords: Nerve cuff recording; Electroneurogram; Sample-and-hold circuit; Application-specific integrated circuit (ASIC); Low power circuit; Velocity selective recording

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chuang, S. (2015). Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Web. 04 Mar 2021.

Vancouver:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Lin, Sheng-En. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.

Degree: Master, Electrical Engineering, 2017, NSYSU

 The analog-to-digital converter (ADC) is an essential component in modern mixed-signal system applications. This thesis presents the design and evaluation of a single-slope integrating ADC… (more)

Subjects/Keywords: single-slope integrating ADC; voltage-to-time converter; low power circuit design; application-specific integrated circuit (ASIC); biological-signal recording system

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, S. (2017). Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Web. 04 Mar 2021.

Vancouver:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Zhou, Yang. Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale.

Degree: Docteur es, Instrumentation et microélectronique, 2014, Université de Strasbourg

Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux… (more)

Subjects/Keywords: Très miniaturisé moniteur de rayonnement dans l'espace; CPS (CMOS pixel sensor); ASIC (Application Specific Integrated Circuit); Highly miniaturized space radiation monitor; CMOS pixel sensor (CPS); Application Specific Integrated Circuit (ASIC); Partical identification and counting; 621.38; 539.7

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, Y. (2014). Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2014STRAE021

Chicago Manual of Style (16th Edition):

Zhou, Yang. “Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale.” 2014. Doctoral Dissertation, Université de Strasbourg. Accessed March 04, 2021. http://www.theses.fr/2014STRAE021.

MLA Handbook (7th Edition):

Zhou, Yang. “Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale.” 2014. Web. 04 Mar 2021.

Vancouver:

Zhou Y. Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2014. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2014STRAE021.

Council of Science Editors:

Zhou Y. Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation : Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale. [Doctoral Dissertation]. Université de Strasbourg; 2014. Available from: http://www.theses.fr/2014STRAE021

5. Tinguy, Pierre. Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator.

Degree: Docteur es, Sciences pour l'ingénieur, 2011, Besançon

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à… (more)

Subjects/Keywords: Oscillateur à quartz; Intégration; ASIC Application specific integrated circuit; Topologie Colpitts; Régulation en température; Modélisation; Flip chip; Quartz crystal oscillator; Integration; ASIC Application specific integrated circuit; Colpitts topology; Thermal control; Modeling; Flip chip; 620

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tinguy, P. (2011). Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator. (Doctoral Dissertation). Besançon. Retrieved from http://www.theses.fr/2011BESA2017

Chicago Manual of Style (16th Edition):

Tinguy, Pierre. “Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator.” 2011. Doctoral Dissertation, Besançon. Accessed March 04, 2021. http://www.theses.fr/2011BESA2017.

MLA Handbook (7th Edition):

Tinguy, Pierre. “Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator.” 2011. Web. 04 Mar 2021.

Vancouver:

Tinguy P. Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator. [Internet] [Doctoral dissertation]. Besançon; 2011. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2011BESA2017.

Council of Science Editors:

Tinguy P. Etude et développement d’un oscillateur à quartz intégré : Study and development of an integrated quartz crystal oscillator. [Doctoral Dissertation]. Besançon; 2011. Available from: http://www.theses.fr/2011BESA2017


Université de Sherbrooke

6. Arpin, Louis. Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels.

Degree: 2012, Université de Sherbrooke

 Des développements technologiques récents concernant les photodiodes à effet avalanche (PDA) ont mené à la conception et la fabrication d'un tout nouveau module de détection… (more)

Subjects/Keywords: Lien différentiel à bas voltage (low-voltage differential signaling, LVDS); Machines à états-finis; Temps au-dessus d'un seuil (time over threshold, ToT); Circuit intégré à application spécifique (application specific integrated circuit, ASIC) à signaux mixtes; Imagerie moléculaire préclinique; LabPET[indice supérieur TM]; Tomographie d'émission par positrons (TEP); Photodiode à effet avalanche (PDA)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arpin, L. (2012). Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels. (Masters Thesis). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/6148

Chicago Manual of Style (16th Edition):

Arpin, Louis. “Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels.” 2012. Masters Thesis, Université de Sherbrooke. Accessed March 04, 2021. http://hdl.handle.net/11143/6148.

MLA Handbook (7th Edition):

Arpin, Louis. “Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels.” 2012. Web. 04 Mar 2021.

Vancouver:

Arpin L. Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels. [Internet] [Masters thesis]. Université de Sherbrooke; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11143/6148.

Council of Science Editors:

Arpin L. Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels. [Masters Thesis]. Université de Sherbrooke; 2012. Available from: http://hdl.handle.net/11143/6148


California State University – Northridge

7. Pandya, Parth. Backend design and testability of a digital ASIC.

Degree: MS, Electrical and Computer Engineering, 2, California State University – Northridge

 Very Large Scale Integration (VLSI) Design is an important and complex area of Electrical and Computer Engineering field. It uses many Computer Aided Design (CAD)… (more)

Subjects/Keywords: Application Specific Integrated Circuit (ASIC) design flow; Dissertations, Academic  – CSUN  – Engineering  – Electrical and Computer Engineering.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pandya, P. (2). Backend design and testability of a digital ASIC. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.3/199956

Chicago Manual of Style (16th Edition):

Pandya, Parth. “Backend design and testability of a digital ASIC.” 2. Masters Thesis, California State University – Northridge. Accessed March 04, 2021. http://hdl.handle.net/10211.3/199956.

MLA Handbook (7th Edition):

Pandya, Parth. “Backend design and testability of a digital ASIC.” 2. Web. 04 Mar 2021.

Vancouver:

Pandya P. Backend design and testability of a digital ASIC. [Internet] [Masters thesis]. California State University – Northridge; 2. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10211.3/199956.

Council of Science Editors:

Pandya P. Backend design and testability of a digital ASIC. [Masters Thesis]. California State University – Northridge; 2. Available from: http://hdl.handle.net/10211.3/199956


Ohio University

8. Gunawardena, Sanjeev. Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays.

Degree: MS, Electrical Engineering & Computer Science (Engineering and Technology), 2000, Ohio University

  The Global Positioning System represents the pinnacle of navigation technology for the 21st century. As new technologies integrate GPS services, the limited availability of… (more)

Subjects/Keywords: Global Positioning System; GPS; block-processing technique; application specific integrated circuit; ASIC; FFT; Field programmable gate arrays; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gunawardena, S. (2000). Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779

Chicago Manual of Style (16th Edition):

Gunawardena, Sanjeev. “Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays.” 2000. Masters Thesis, Ohio University. Accessed March 04, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779.

MLA Handbook (7th Edition):

Gunawardena, Sanjeev. “Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays.” 2000. Web. 04 Mar 2021.

Vancouver:

Gunawardena S. Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays. [Internet] [Masters thesis]. Ohio University; 2000. [cited 2021 Mar 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779.

Council of Science Editors:

Gunawardena S. Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays. [Masters Thesis]. Ohio University; 2000. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779

9. Zhao, Wei. Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex.

Degree: Docteur es, Instrumentation et microélectronique, 2015, Université de Strasbourg

La thèse présente le développement de CPS (CMOS Pixel Sensors) intégré avec CAN au niveau du pixel pour les couches externes du détecteur de vertex… (more)

Subjects/Keywords: Détection de particules de charge; CPS (CMOS Pixel Sensors); CAN (Convertisseur Analogique-Numérique) au niveau du pixel; ASIC; ILC; ILD; VTX; DPS; Charge particle detection; CPS (CMOS Pixel Sensors),; Pixel-level ADCs (Analog-to-Digital Converters); ASIC (Application Specific Integrated Circuit); ILC (International Linear Collider); ILD (International Large Detector); VTX (Vertex Detector); DPS (Digital Pixel Sensors); 621.38; 539.7

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, W. (2015). Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2015STRAE004

Chicago Manual of Style (16th Edition):

Zhao, Wei. “Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex.” 2015. Doctoral Dissertation, Université de Strasbourg. Accessed March 04, 2021. http://www.theses.fr/2015STRAE004.

MLA Handbook (7th Edition):

Zhao, Wei. “Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex.” 2015. Web. 04 Mar 2021.

Vancouver:

Zhao W. Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2015. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2015STRAE004.

Council of Science Editors:

Zhao W. Development of CMOS sensor with digital pixels for ILD vertex detector : Développement de capteurs à CMOS avec pixel numérique pour le ILD détecteur de vertex. [Doctoral Dissertation]. Université de Strasbourg; 2015. Available from: http://www.theses.fr/2015STRAE004

10. Petura, Oto. True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation.

Degree: Docteur es, Microélectronique, 2019, Lyon

Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour… (more)

Subjects/Keywords: TRNG; Générateur de nombres aléatoires; Tests embarqués; FPGA; ASIC; PLL-TRNG; Gigue; Mesure de la gigue; Réseaux logiques programmables; Clock jitter; Jitter measurement; True Random Number Generator; TRNG; Random number generator; Embedded tests; FPGA; Field Programmable Gate Arrays; ASIC; Application Specific Integrated Circuit; PLL-TRNG; Phase locked-loops - True random number generators

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Petura, O. (2019). True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2019LYSES053

Chicago Manual of Style (16th Edition):

Petura, Oto. “True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation.” 2019. Doctoral Dissertation, Lyon. Accessed March 04, 2021. http://www.theses.fr/2019LYSES053.

MLA Handbook (7th Edition):

Petura, Oto. “True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation.” 2019. Web. 04 Mar 2021.

Vancouver:

Petura O. True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation. [Internet] [Doctoral dissertation]. Lyon; 2019. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2019LYSES053.

Council of Science Editors:

Petura O. True random number generators for cryptography : Design, securing and evaluation : Générateurs de nombres aléatoires pour la cryptographie : Conception, sécurisation et évaluation. [Doctoral Dissertation]. Lyon; 2019. Available from: http://www.theses.fr/2019LYSES053


NSYSU

11. Shi, Po-Xu. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.

Degree: Master, Electrical Engineering, 2018, NSYSU

 This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference… (more)

Subjects/Keywords: quasi floating gate memory; clock generator; adjustable frequency; application-specific integrated circuit; oscillator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, P. (2018). Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Po-Xu. “Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.” 2018. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Po-Xu. “Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.” 2018. Web. 04 Mar 2021.

Vancouver:

Shi P. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi P. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

12. Adarsha Rao, S J. Polymorphic ASIC : For Video Decoding.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

 Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video… (more)

Subjects/Keywords: Application Specific Integrated Circuits (ASIC); Polymorphic ASIC (Applicaion Specific Integrated Circuits); Unified Software and Hardware Architecture (USHA); Video Decoding; Polymorphic ASIC Architecture; Multiprocessor System-On-Chip (MPSoC); H.264 Decoder; Video Encoding; H.264 Decoders; H.264 Decoding; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Adarsha Rao, S. J. (2018). Polymorphic ASIC : For Video Decoding. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3291

Chicago Manual of Style (16th Edition):

Adarsha Rao, S J. “Polymorphic ASIC : For Video Decoding.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed March 04, 2021. http://etd.iisc.ac.in/handle/2005/3291.

MLA Handbook (7th Edition):

Adarsha Rao, S J. “Polymorphic ASIC : For Video Decoding.” 2018. Web. 04 Mar 2021.

Vancouver:

Adarsha Rao SJ. Polymorphic ASIC : For Video Decoding. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Mar 04]. Available from: http://etd.iisc.ac.in/handle/2005/3291.

Council of Science Editors:

Adarsha Rao SJ. Polymorphic ASIC : For Video Decoding. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3291


Macquarie University

13. Hossain, Md Selim. High performance hardware implementation of elliptic curve cryptography.

Degree: 2017, Macquarie University

Empirical thesis.

Bibliography: pages 339-362.

1. Introduction  – 2. Background  – 3. Efficient hardware implementation of finite field arithmetic for elliptic curve cryptography  – 4.… (more)

Subjects/Keywords: Public key cryptography; Curves, Elliptic  – Industrial applications; elliptic curve cryptography (ECC); finite field arithmetic (FFA); point doubling (PD); point addition (PA); point doubling and point addition (PDPA); elliptic curve point multiplication (ECPM); ECC processor (ECP); application-specific integrated circuit (ASIC); field-programmable gate array (FPGA); Natonal Institute of Standards and Technology (NIST)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hossain, M. S. (2017). High performance hardware implementation of elliptic curve cryptography. (Doctoral Dissertation). Macquarie University. Retrieved from http://hdl.handle.net/1959.14/1261356

Chicago Manual of Style (16th Edition):

Hossain, Md Selim. “High performance hardware implementation of elliptic curve cryptography.” 2017. Doctoral Dissertation, Macquarie University. Accessed March 04, 2021. http://hdl.handle.net/1959.14/1261356.

MLA Handbook (7th Edition):

Hossain, Md Selim. “High performance hardware implementation of elliptic curve cryptography.” 2017. Web. 04 Mar 2021.

Vancouver:

Hossain MS. High performance hardware implementation of elliptic curve cryptography. [Internet] [Doctoral dissertation]. Macquarie University; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1959.14/1261356.

Council of Science Editors:

Hossain MS. High performance hardware implementation of elliptic curve cryptography. [Doctoral Dissertation]. Macquarie University; 2017. Available from: http://hdl.handle.net/1959.14/1261356


University of Cincinnati

14. Chadha, Vishal. Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.

Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati

 One limitation of current FPGAs is that the user is limited to strictly digital electronic designs and are not suitable for multi-technology applications. In 2002,… (more)

Subjects/Keywords: ASIC; Application specific integrated circuit; CMOS; Complementary Metal Oxide Semiconductor. Technology used to manufacture silicon; integrated circuits; Delay flip-flop or D-flop; The input is copied to the output delayed by one clock cycle; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chadha, V. (2005). Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992

Chicago Manual of Style (16th Edition):

Chadha, Vishal. “Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.” 2005. Masters Thesis, University of Cincinnati. Accessed March 04, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

MLA Handbook (7th Edition):

Chadha, Vishal. “Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.” 2005. Web. 04 Mar 2021.

Vancouver:

Chadha V. Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays. [Internet] [Masters thesis]. University of Cincinnati; 2005. [cited 2021 Mar 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

Council of Science Editors:

Chadha V. Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays. [Masters Thesis]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992

15. Li, Bo. Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies.

Degree: Docteur es, Génie électrique, 2012, INSA Lyon

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de… (more)

Subjects/Keywords: Électronique de puissance; Convertisseur à découpage; Convertisseur DC-DC; Commande électronique; Contrôle logique digital; Contrôleur numérique; SMPS - switching-mode power supply; Commande prédictive; DPWM - Digital pulse-width modulator; PwrSoC - Power supply-on-chip; Abaisseur de tension; Contrôleur PID linéaire; Commande par modes glissants; Prototype ASIC; Processeur ASIC; Power Electronics; Cutting Converter; Switched-mode power Converter; DC-to-DC Converter; Electronic Control; Digital Logic Monitoring; SMPS - switching-mode power supply; Feed Forward Control; DPWM - Digital pulse-width modulator; PwrSoC - Power supply-on-chip; ASIC - Application Specific Integrated Circuit - Processor; 621.381 044 072

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, B. (2012). Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2012ISAL0036

Chicago Manual of Style (16th Edition):

Li, Bo. “Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies.” 2012. Doctoral Dissertation, INSA Lyon. Accessed March 04, 2021. http://www.theses.fr/2012ISAL0036.

MLA Handbook (7th Edition):

Li, Bo. “Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies.” 2012. Web. 04 Mar 2021.

Vancouver:

Li B. Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies. [Internet] [Doctoral dissertation]. INSA Lyon; 2012. [cited 2021 Mar 04]. Available from: http://www.theses.fr/2012ISAL0036.

Council of Science Editors:

Li B. Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées : Design and test of digitally-controlled power management IPs in advanced CMOS technologies. [Doctoral Dissertation]. INSA Lyon; 2012. Available from: http://www.theses.fr/2012ISAL0036

16. Yang, Gangqiang. Optimized Hardware Implementations of Lightweight Cryptography.

Degree: 2017, University of Waterloo

 Radio frequency identification (RFID) is a key technology for the Internet of Things era. One important advantage of RFID over barcodes is that line-of-sight is… (more)

Subjects/Keywords: Lightweight Cryptography; Hardware Implementations; Hardware Optimizations; Field Programmable Gate Array (FPGA); Application Specific Integrated Circuit (ASIC); Radio Frequency IDentification (RFID); Block Cipher; Stream Cipher; Pseudorandom Number Generator (PRNG)

…smallest available hardware implementation of AES in CMOS 180nm Application Specific Integrated… …Circuit (ASIC) requires 2400 GEs [82]. In order to overcome this challenge… …approaches for cryptographic primitives. 2.4.1 Hardware Implementations Application specific… …Implementations and Results . . . . . . . . . . . . . . . . . . . . 72 4.4.3 ASIC Implementations and… …80 5.2 ASIC Architecture… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, G. (2017). Optimized Hardware Implementations of Lightweight Cryptography. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Gangqiang. “Optimized Hardware Implementations of Lightweight Cryptography.” 2017. Thesis, University of Waterloo. Accessed March 04, 2021. http://hdl.handle.net/10012/11237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Gangqiang. “Optimized Hardware Implementations of Lightweight Cryptography.” 2017. Web. 04 Mar 2021.

Vancouver:

Yang G. Optimized Hardware Implementations of Lightweight Cryptography. [Internet] [Thesis]. University of Waterloo; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10012/11237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang G. Optimized Hardware Implementations of Lightweight Cryptography. [Thesis]. University of Waterloo; 2017. Available from: http://hdl.handle.net/10012/11237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

17. Bagga, Shobi. Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing.

Degree: MSc Engg, Faculty of Engineering, 2009, Indian Institute of Science

 The widespread use of Liquid Petroleum Gas (LPG) for cooking and as fuel for automobile vehicles requires fast and selective detection of LPG to precisely… (more)

Subjects/Keywords: Electronic Devices; Gas Sensors; Sensor Film Deposition; Tin Oxide Films - Properties; Application Specific Integrated Circuit (ASIC); Tin Oxide Gas Sensor; Tin Oxide Films - Deposition; Gas Sensor System; Instrumentation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bagga, S. (2009). Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/474

Chicago Manual of Style (16th Edition):

Bagga, Shobi. “Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing.” 2009. Masters Thesis, Indian Institute of Science. Accessed March 04, 2021. http://etd.iisc.ac.in/handle/2005/474.

MLA Handbook (7th Edition):

Bagga, Shobi. “Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing.” 2009. Web. 04 Mar 2021.

Vancouver:

Bagga S. Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing. [Internet] [Masters thesis]. Indian Institute of Science; 2009. [cited 2021 Mar 04]. Available from: http://etd.iisc.ac.in/handle/2005/474.

Council of Science Editors:

Bagga S. Gas Sensor-Studies On Sensor Film Deposition, ASIC Design And Testing. [Masters Thesis]. Indian Institute of Science; 2009. Available from: http://etd.iisc.ac.in/handle/2005/474

18. York, Johnathan Andrew. Multiple personality integrated circuits and the cost of programmability.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

 This dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication… (more)

Subjects/Keywords: Programmability; Integrated circuit; ASIC; FPGA

Application Details . . . . . . . . . . . . . . . . . . . . . . . . 101 ASIC Implementation… …engineering costs forming a substantial component of device cost for many Application Specific… …outweigh the incremental fabrication costs of large scale integrated circuit fabrication. In… …function circuit implementation of a computation that exceeds a specific set of performance… …102 4.3.1 Input Circuit Baselines . . . . . . . . . . . . . . . . . . . . . 102 4.3.2… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Sample image

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

York, J. A. (2011). Multiple personality integrated circuits and the cost of programmability. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-2676

Chicago Manual of Style (16th Edition):

York, Johnathan Andrew. “Multiple personality integrated circuits and the cost of programmability.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed March 04, 2021. http://hdl.handle.net/2152/ETD-UT-2011-05-2676.

MLA Handbook (7th Edition):

York, Johnathan Andrew. “Multiple personality integrated circuits and the cost of programmability.” 2011. Web. 04 Mar 2021.

Vancouver:

York JA. Multiple personality integrated circuits and the cost of programmability. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-2676.

Council of Science Editors:

York JA. Multiple personality integrated circuits and the cost of programmability. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-2676

19. Ranganathan, Lavakumar. Sensor-array chip hybrid for simultaneous multiple analyte detection.

Degree: PhD, 2007, Oregon Health Sciences University

Subjects/Keywords: Biosensors  – Research; Application specific integrated circuits; Lab-on-chip; LOC; E-nose; Sensor array; Hybrid; Asic; Integrated chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ranganathan, L. (2007). Sensor-array chip hybrid for simultaneous multiple analyte detection. (Doctoral Dissertation). Oregon Health Sciences University. Retrieved from doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154

Chicago Manual of Style (16th Edition):

Ranganathan, Lavakumar. “Sensor-array chip hybrid for simultaneous multiple analyte detection.” 2007. Doctoral Dissertation, Oregon Health Sciences University. Accessed March 04, 2021. doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154.

MLA Handbook (7th Edition):

Ranganathan, Lavakumar. “Sensor-array chip hybrid for simultaneous multiple analyte detection.” 2007. Web. 04 Mar 2021.

Vancouver:

Ranganathan L. Sensor-array chip hybrid for simultaneous multiple analyte detection. [Internet] [Doctoral dissertation]. Oregon Health Sciences University; 2007. [cited 2021 Mar 04]. Available from: doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154.

Council of Science Editors:

Ranganathan L. Sensor-array chip hybrid for simultaneous multiple analyte detection. [Doctoral Dissertation]. Oregon Health Sciences University; 2007. Available from: doi:10.6083/M4348H8Z ; http://digitalcommons.ohsu.edu/etd/154


York University

20. Zhao, Yang. Low Power Circuits for Smart Flexible ECG Sensors.

Degree: PhD, Computer Science, 2020, York University

 Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor… (more)

Subjects/Keywords: Biomedical engineering; Electrocardiogram (ECG); Analog Front-end; QRS detector; Cardiac Arrhythmia Classifier; Low power; Common mode rejection ratio (CMRR); Noise efficiency factor (NEF); Application specific integrated circuits (ASIC); DC-coupled; Patient-specific; Classification accuracy; Low noise; Flexible ECG sensor; Sensor interface circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, Y. (2020). Low Power Circuits for Smart Flexible ECG Sensors. (Doctoral Dissertation). York University. Retrieved from https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346

Chicago Manual of Style (16th Edition):

Zhao, Yang. “Low Power Circuits for Smart Flexible ECG Sensors.” 2020. Doctoral Dissertation, York University. Accessed March 04, 2021. https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346.

MLA Handbook (7th Edition):

Zhao, Yang. “Low Power Circuits for Smart Flexible ECG Sensors.” 2020. Web. 04 Mar 2021.

Vancouver:

Zhao Y. Low Power Circuits for Smart Flexible ECG Sensors. [Internet] [Doctoral dissertation]. York University; 2020. [cited 2021 Mar 04]. Available from: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346.

Council of Science Editors:

Zhao Y. Low Power Circuits for Smart Flexible ECG Sensors. [Doctoral Dissertation]. York University; 2020. Available from: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37346


Brno University of Technology

21. Dvořák, Vojtěch. Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC.

Degree: 2019, Brno University of Technology

 The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation… (more)

Subjects/Keywords: Číslicové zpracování signálu; diskrétní Fourierova transformace; rychlá Fourierova transformace; DFT; FFT; VHDL; programovatelné logické obvody; FPGA; zákaznické obvody; ASIC; verifikace; syntéza digitálních obvodů; Digital signal processing; discrete Fourier transform; fast Fourier transform; DFT; FFT; VHDL; programable logic circuits; FPGA; application-specified integrated circuit; ASIC; verification; synthesis of digital circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dvořák, V. (2019). Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/27112

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dvořák, Vojtěch. “Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC.” 2019. Thesis, Brno University of Technology. Accessed March 04, 2021. http://hdl.handle.net/11012/27112.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dvořák, Vojtěch. “Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC.” 2019. Web. 04 Mar 2021.

Vancouver:

Dvořák V. Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/11012/27112.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dvořák V. Implementace výpočtu FFT v obvodech FPGA a ASIC: FFT implementation in FPGA and ASIC. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/27112

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

22. Bavaresco, Simone. On-silicon testbench for validation of soft logic cell libraries.

Degree: 2008, Universidade do Rio Grande do Sul

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células… (more)

Subjects/Keywords: Integrated circuit; Microeletrônica; ASIC; Testes : Circuitos integrados; Digital design; Standard cell; Library-free technology mapping; Soft library; Test circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bavaresco, S. (2008). On-silicon testbench for validation of soft logic cell libraries. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/14907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bavaresco, Simone. “On-silicon testbench for validation of soft logic cell libraries.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed March 04, 2021. http://hdl.handle.net/10183/14907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bavaresco, Simone. “On-silicon testbench for validation of soft logic cell libraries.” 2008. Web. 04 Mar 2021.

Vancouver:

Bavaresco S. On-silicon testbench for validation of soft logic cell libraries. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10183/14907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bavaresco S. On-silicon testbench for validation of soft logic cell libraries. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/14907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

23. Kala, S. ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor.

Degree: MSc Engg, Faculty of Engineering, 2016, Indian Institute of Science

 The rapid advancements in semiconductor technology have led to constant shrinking of transistor sizes as per Moore's Law. Wireless communications is one field which has… (more)

Subjects/Keywords: Wireless Communication Systems; Fast Fourier Transformation Processor; Fast Fourier Transform Archirecture; Fast Fourier Transform - Algorithms; Application Specific Integrated Circuit; FFT Processor; FFT Architecture; Orthogonal Frequency Division Multiplexing (OFDM); Communication Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kala, S. (2016). ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2557

Chicago Manual of Style (16th Edition):

Kala, S. “ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor.” 2016. Masters Thesis, Indian Institute of Science. Accessed March 04, 2021. http://etd.iisc.ac.in/handle/2005/2557.

MLA Handbook (7th Edition):

Kala, S. “ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor.” 2016. Web. 04 Mar 2021.

Vancouver:

Kala S. ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor. [Internet] [Masters thesis]. Indian Institute of Science; 2016. [cited 2021 Mar 04]. Available from: http://etd.iisc.ac.in/handle/2005/2557.

Council of Science Editors:

Kala S. ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor. [Masters Thesis]. Indian Institute of Science; 2016. Available from: http://etd.iisc.ac.in/handle/2005/2557


New Jersey Institute of Technology

24. Gururaj, Kiran K. On chip implement of deadlock avoidance in wormhole networks.

Degree: MSin Electrical Engineering - (M.S.), Electrical and Computer Engineering, 2002, New Jersey Institute of Technology

  This thesis gives a detailed description of the Application Specific Integrated Circuit (ASIC) design to avoid deadlocks in Wormhole Networks. Deadlock avoidance is the… (more)

Subjects/Keywords: Application specific integrated circuit; Wormhole networks; DeadLock Avoidance; Electrical and Electronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gururaj, K. K. (2002). On chip implement of deadlock avoidance in wormhole networks. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/696

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gururaj, Kiran K. “On chip implement of deadlock avoidance in wormhole networks.” 2002. Thesis, New Jersey Institute of Technology. Accessed March 04, 2021. https://digitalcommons.njit.edu/theses/696.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gururaj, Kiran K. “On chip implement of deadlock avoidance in wormhole networks.” 2002. Web. 04 Mar 2021.

Vancouver:

Gururaj KK. On chip implement of deadlock avoidance in wormhole networks. [Internet] [Thesis]. New Jersey Institute of Technology; 2002. [cited 2021 Mar 04]. Available from: https://digitalcommons.njit.edu/theses/696.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gururaj KK. On chip implement of deadlock avoidance in wormhole networks. [Thesis]. New Jersey Institute of Technology; 2002. Available from: https://digitalcommons.njit.edu/theses/696

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Bellasi, David E. Toward Energy-Proportional Compressive Sensors.

Degree: 2018, ETH Zürich

 The vision of the Internet of things (IoT) entails the connection of all possible objects to the Internet for the purpose of monitoring and actuation,… (more)

Subjects/Keywords: Compressive sensing (CS); Internet of things (IoT); wireless sensors; data compression; microelectronics; application specific integrated circuits (ASIC); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/4; info:eu-repo/classification/ddc/621.3; Electric engineering; Data processing, computer science; Electric engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bellasi, D. E. (2018). Toward Energy-Proportional Compressive Sensors. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/283900

Chicago Manual of Style (16th Edition):

Bellasi, David E. “Toward Energy-Proportional Compressive Sensors.” 2018. Doctoral Dissertation, ETH Zürich. Accessed March 04, 2021. http://hdl.handle.net/20.500.11850/283900.

MLA Handbook (7th Edition):

Bellasi, David E. “Toward Energy-Proportional Compressive Sensors.” 2018. Web. 04 Mar 2021.

Vancouver:

Bellasi DE. Toward Energy-Proportional Compressive Sensors. [Internet] [Doctoral dissertation]. ETH Zürich; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/20.500.11850/283900.

Council of Science Editors:

Bellasi DE. Toward Energy-Proportional Compressive Sensors. [Doctoral Dissertation]. ETH Zürich; 2018. Available from: http://hdl.handle.net/20.500.11850/283900

26. Rachamadugu, Arun. Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 A method to implement high-speed pulse shaping filters has been discussed. This technique uses a unique look up table based architecture implemented in 90nm CMOS… (more)

Subjects/Keywords: ASIC implementation; SPI interface; Raised cosine FIR; Pulse shaping; Digital filters (Mathematics); Application-specific integrated circuits

…cell based ASIC flow. This method enables the implementation of pulse shaping filters for… …detail along with circuit level descriptions and timing diagrams describing the circuit… …can be easily integrated on silicon making them ideal for system on chip designs. FIR… …table with precalculated outcomes in even and odd paths 7 CHAPTER III ASIC IMPLEMENTATION… …In this chapter the specific details of all the steps involved in the design, from… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rachamadugu, A. (2008). Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26603

Chicago Manual of Style (16th Edition):

Rachamadugu, Arun. “Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design.” 2008. Masters Thesis, Georgia Tech. Accessed March 04, 2021. http://hdl.handle.net/1853/26603.

MLA Handbook (7th Edition):

Rachamadugu, Arun. “Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design.” 2008. Web. 04 Mar 2021.

Vancouver:

Rachamadugu A. Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1853/26603.

Council of Science Editors:

Rachamadugu A. Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26603


North Carolina State University

27. Chandra, Dhruba. Speech Recognition Co-processor.

Degree: PhD, Computer Engineering, 2008, North Carolina State University

 With computing trend moving towards ubiquitous computing propelled by the advances in embedded mobile processors and battery technology, speech recognition is becoming an essential part… (more)

Subjects/Keywords: Application Specific; Low Power; ASIC; Speech Recognition

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandra, D. (2008). Speech Recognition Co-processor. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3421

Chicago Manual of Style (16th Edition):

Chandra, Dhruba. “Speech Recognition Co-processor.” 2008. Doctoral Dissertation, North Carolina State University. Accessed March 04, 2021. http://www.lib.ncsu.edu/resolver/1840.16/3421.

MLA Handbook (7th Edition):

Chandra, Dhruba. “Speech Recognition Co-processor.” 2008. Web. 04 Mar 2021.

Vancouver:

Chandra D. Speech Recognition Co-processor. [Internet] [Doctoral dissertation]. North Carolina State University; 2008. [cited 2021 Mar 04]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3421.

Council of Science Editors:

Chandra D. Speech Recognition Co-processor. [Doctoral Dissertation]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3421


Nelson Mandela Metropolitan University

28. [No author]. Total ionizing dose and single event upset testing of flash based field programmable gate arrays.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2015, Nelson Mandela Metropolitan University

 The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private… (more)

Subjects/Keywords: Field programmable gate arrays; Application-specific integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2015). Total ionizing dose and single event upset testing of flash based field programmable gate arrays. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/12548

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Total ionizing dose and single event upset testing of flash based field programmable gate arrays.” 2015. Thesis, Nelson Mandela Metropolitan University. Accessed March 04, 2021. http://hdl.handle.net/10948/12548.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Total ionizing dose and single event upset testing of flash based field programmable gate arrays.” 2015. Web. 04 Mar 2021.

Vancouver:

author] [. Total ionizing dose and single event upset testing of flash based field programmable gate arrays. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2015. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10948/12548.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Total ionizing dose and single event upset testing of flash based field programmable gate arrays. [Thesis]. Nelson Mandela Metropolitan University; 2015. Available from: http://hdl.handle.net/10948/12548

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rutgers University

29. Sethuram, Rajamani. Reducing digital test volume using test point insertion.

Degree: PhD, Electrical and Computer Engineering, 2008, Rutgers University

Test cost accounts for more than 40% of the entire cost for making a chip. This figure is expected to grow even higher in the… (more)

Subjects/Keywords: Application-specific integrated circuits; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sethuram, R. (2008). Reducing digital test volume using test point insertion. (Doctoral Dissertation). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215

Chicago Manual of Style (16th Edition):

Sethuram, Rajamani. “Reducing digital test volume using test point insertion.” 2008. Doctoral Dissertation, Rutgers University. Accessed March 04, 2021. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215.

MLA Handbook (7th Edition):

Sethuram, Rajamani. “Reducing digital test volume using test point insertion.” 2008. Web. 04 Mar 2021.

Vancouver:

Sethuram R. Reducing digital test volume using test point insertion. [Internet] [Doctoral dissertation]. Rutgers University; 2008. [cited 2021 Mar 04]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215.

Council of Science Editors:

Sethuram R. Reducing digital test volume using test point insertion. [Doctoral Dissertation]. Rutgers University; 2008. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215

30. Park, Chang Joon. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.

Degree: 2013, Texas Digital Library

 Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal… (more)

Subjects/Keywords: Integrated Circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, C. J. (2013). Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. (Thesis). Texas Digital Library. Retrieved from http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Chang Joon. “Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.” 2013. Thesis, Texas Digital Library. Accessed March 04, 2021. http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Chang Joon. “Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.” 2013. Web. 04 Mar 2021.

Vancouver:

Park CJ. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. [Internet] [Thesis]. Texas Digital Library; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park CJ. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. [Thesis]. Texas Digital Library; 2013. Available from: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [849]

.