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Dates: 2010 – 2014

You searched for subject:(Analog to digital converters). Showing records 1 – 30 of 14436 total matches.

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Oregon State University

1. Hu, Yue. Efficient use of time information in analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information… (more)

Subjects/Keywords: Analog-to-digital converters

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APA (6th Edition):

Hu, Y. (2014). Efficient use of time information in analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/52553

Chicago Manual of Style (16th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/52553.

MLA Handbook (7th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Web. 18 Oct 2019.

Vancouver:

Hu Y. Efficient use of time information in analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/52553.

Council of Science Editors:

Hu Y. Efficient use of time information in analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/52553


Oregon State University

2. Tong, Tao. Design techniques for successive approximation register analog-to-digital converters.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently,… (more)

Subjects/Keywords: analog-to-digital converters

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APA (6th Edition):

Tong, T. (2011). Design techniques for successive approximation register analog-to-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22662

Chicago Manual of Style (16th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/22662.

MLA Handbook (7th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Web. 18 Oct 2019.

Vancouver:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/22662.

Council of Science Editors:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/22662


Oregon State University

3. Maghari, Nima. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR)… (more)

Subjects/Keywords: Analog Ciruits; Analog-to-digital converters

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APA (6th Edition):

Maghari, N. (2010). Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18851

Chicago Manual of Style (16th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/18851.

MLA Handbook (7th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Web. 18 Oct 2019.

Vancouver:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/18851.

Council of Science Editors:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18851


Dalhousie University

4. D'souza, Rowena Joan. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2010, Dalhousie University

 This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The… (more)

Subjects/Keywords: Digital-to-analog converters; Time-interleaving

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APA (6th Edition):

D'souza, R. J. (2010). Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/12994

Chicago Manual of Style (16th Edition):

D'souza, Rowena Joan. “Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.” 2010. Masters Thesis, Dalhousie University. Accessed October 18, 2019. http://hdl.handle.net/10222/12994.

MLA Handbook (7th Edition):

D'souza, Rowena Joan. “Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.” 2010. Web. 18 Oct 2019.

Vancouver:

D'souza RJ. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. [Internet] [Masters thesis]. Dalhousie University; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10222/12994.

Council of Science Editors:

D'souza RJ. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. [Masters Thesis]. Dalhousie University; 2010. Available from: http://hdl.handle.net/10222/12994

5. Meganathan D. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.

Degree: A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits, 2014, Anna University

High speed and medium resolution Analog to Digital Converters newline ADC are widely used in commercial applications including data newlinecommunication and image signal processing In… (more)

Subjects/Keywords: Analog to Digital Converters; Complementary Metal Oxide

Page 1

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APA (6th Edition):

D, M. (2014). A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/29245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

D, Meganathan. “A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.” 2014. Thesis, Anna University. Accessed October 18, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/29245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

D, Meganathan. “A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.” 2014. Web. 18 Oct 2019.

Vancouver:

D M. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Oct 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

D M. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

6. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 18 Oct 2019.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709


Oregon State University

7. Leung, Jerry. Data driven optimization in SAR ADC.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques… (more)

Subjects/Keywords: SAR; Successive approximation analog-to-digital converters

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APA (6th Edition):

Leung, J. (2014). Data driven optimization in SAR ADC. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/54631

Chicago Manual of Style (16th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/54631.

MLA Handbook (7th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Web. 18 Oct 2019.

Vancouver:

Leung J. Data driven optimization in SAR ADC. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/54631.

Council of Science Editors:

Leung J. Data driven optimization in SAR ADC. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/54631


Hong Kong University of Science and Technology

8. Yang, Shiliang. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.

Degree: 2014, Hong Kong University of Science and Technology

 In the deep sub-micron process, the transistor intrinsic gain is low and the supply voltage is low, resulting in the great difficulty in designing a… (more)

Subjects/Keywords: Analog-to-digital converters; Calibration; Operational amplifiers

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APA (6th Edition):

Yang, S. (2014). A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Shiliang. “A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed October 18, 2019. https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Shiliang. “A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.” 2014. Web. 18 Oct 2019.

Vancouver:

Yang S. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Oct 18]. Available from: https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang S. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

9. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 18 Oct 2019.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


Oregon State University

10. Musah, Tawfiq. Low power design techniques for analog-to-digital converters in submicron CMOS.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical… (more)

Subjects/Keywords: correlated level shifting; Analog-to-digital converters

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APA (6th Edition):

Musah, T. (2010). Low power design techniques for analog-to-digital converters in submicron CMOS. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18826

Chicago Manual of Style (16th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/18826.

MLA Handbook (7th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Web. 18 Oct 2019.

Vancouver:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/18826.

Council of Science Editors:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18826


Oregon State University

11. Zanbaghi, Ramin. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high… (more)

Subjects/Keywords: delta-sigma modulator; Analog-to-digital converters

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APA (6th Edition):

Zanbaghi, R. (2011). Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/23456

Chicago Manual of Style (16th Edition):

Zanbaghi, Ramin. “Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/23456.

MLA Handbook (7th Edition):

Zanbaghi, Ramin. “Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.” 2011. Web. 18 Oct 2019.

Vancouver:

Zanbaghi R. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/23456.

Council of Science Editors:

Zanbaghi R. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/23456


Oregon State University

12. Oh, Taehwan. Power efficient analog-to-digital converters using both voltage and time domain information.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs… (more)

Subjects/Keywords: Delta-sigma; Analog-to-digital converters

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APA (6th Edition):

Oh, T. (2013). Power efficient analog-to-digital converters using both voltage and time domain information. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39042

Chicago Manual of Style (16th Edition):

Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/39042.

MLA Handbook (7th Edition):

Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Web. 18 Oct 2019.

Vancouver:

Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/39042.

Council of Science Editors:

Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39042


Oregon State University

13. Gande, Manideep. Design techniques for time based data converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data… (more)

Subjects/Keywords: Time based data converters; Analog-to-digital converters

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APA (6th Edition):

Gande, M. (2013). Design techniques for time based data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39773

Chicago Manual of Style (16th Edition):

Gande, Manideep. “Design techniques for time based data converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/39773.

MLA Handbook (7th Edition):

Gande, Manideep. “Design techniques for time based data converters.” 2013. Web. 18 Oct 2019.

Vancouver:

Gande M. Design techniques for time based data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/39773.

Council of Science Editors:

Gande M. Design techniques for time based data converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39773


University of Waterloo

14. Shirtliff, Jason Neil. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.

Degree: 2010, University of Waterloo

 Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum… (more)

Subjects/Keywords: analog circuit design; timing mismatches; interleaved analog to digital converters; microelectronics

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APA (6th Edition):

Shirtliff, J. N. (2010). Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shirtliff, Jason Neil. “Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.” 2010. Thesis, University of Waterloo. Accessed October 18, 2019. http://hdl.handle.net/10012/5523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shirtliff, Jason Neil. “Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.” 2010. Web. 18 Oct 2019.

Vancouver:

Shirtliff JN. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10012/5523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shirtliff JN. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2010. Available from: http://hdl.handle.net/10012/5523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

15. Chan, Man Pun. Design of monolithic digital current-mode controllers for DC-DC converters.

Degree: 2013, Hong Kong University of Science and Technology

 Monolithic digital controllers for dc-dc converters are the future trend of voltage regulators for space-constrained portable devices because they can be highly integrated on-chip. This… (more)

Subjects/Keywords: DC-to-DC converters; Analog-to-digital converters; Electric switchgear; Digital control systems

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APA (6th Edition):

Chan, M. P. (2013). Design of monolithic digital current-mode controllers for DC-DC converters. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1251005 ; http://repository.ust.hk/ir/bitstream/1783.1-81377/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chan, Man Pun. “Design of monolithic digital current-mode controllers for DC-DC converters.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed October 18, 2019. https://doi.org/10.14711/thesis-b1251005 ; http://repository.ust.hk/ir/bitstream/1783.1-81377/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chan, Man Pun. “Design of monolithic digital current-mode controllers for DC-DC converters.” 2013. Web. 18 Oct 2019.

Vancouver:

Chan MP. Design of monolithic digital current-mode controllers for DC-DC converters. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2019 Oct 18]. Available from: https://doi.org/10.14711/thesis-b1251005 ; http://repository.ust.hk/ir/bitstream/1783.1-81377/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan MP. Design of monolithic digital current-mode controllers for DC-DC converters. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: https://doi.org/10.14711/thesis-b1251005 ; http://repository.ust.hk/ir/bitstream/1783.1-81377/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

16. Chen, Denis Guangyin. Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression.

Degree: 2013, Hong Kong University of Science and Technology

 Mobile and portable applications have become the driving force behind the growth of the Complementary Metal-Oxide Semiconductor (CMOS) image sensor's industry. Low power and increased… (more)

Subjects/Keywords: Image converters; Metal oxide semiconductors, Complementary; Image processing; Digital techniques; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, D. G. (2013). Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1214726 ; http://repository.ust.hk/ir/bitstream/1783.1-8143/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Denis Guangyin. “Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed October 18, 2019. https://doi.org/10.14711/thesis-b1214726 ; http://repository.ust.hk/ir/bitstream/1783.1-8143/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Denis Guangyin. “Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression.” 2013. Web. 18 Oct 2019.

Vancouver:

Chen DG. Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2019 Oct 18]. Available from: https://doi.org/10.14711/thesis-b1214726 ; http://repository.ust.hk/ir/bitstream/1783.1-8143/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen DG. Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: https://doi.org/10.14711/thesis-b1214726 ; http://repository.ust.hk/ir/bitstream/1783.1-8143/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

17. Gadde, Venkata Veera Satya Sair. Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC.

Degree: 2011, Texas A&M University

 Continuous-time filters are critical components in the implementation of large bandwidth, high frequency, and high resolution continuous-time (CT) sigma-delta (??) analog-to-digital converters (ADCs). The loop… (more)

Subjects/Keywords: Continuos-time filters; Sigma-delta modulators; Analog-to-digital converters

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APA (6th Edition):

Gadde, V. V. S. S. (2011). Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gadde, Venkata Veera Satya Sair. “Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC.” 2011. Thesis, Texas A&M University. Accessed October 18, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gadde, Venkata Veera Satya Sair. “Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC.” 2011. Web. 18 Oct 2019.

Vancouver:

Gadde VVSS. Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC. [Internet] [Thesis]. Texas A&M University; 2011. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gadde VVSS. Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC. [Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

18. Yu, Wenhuan. Design techniques for low power ADCs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the… (more)

Subjects/Keywords: data converter; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Yu, W. (2010). Design techniques for low power ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14316

Chicago Manual of Style (16th Edition):

Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/14316.

MLA Handbook (7th Edition):

Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Web. 18 Oct 2019.

Vancouver:

Yu W. Design techniques for low power ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/14316.

Council of Science Editors:

Yu W. Design techniques for low power ADCs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14316


Oregon State University

19. Wang, Tao. Low-power high-resolution delta-sigma ADC design techniques.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to… (more)

Subjects/Keywords: ADC; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Wang, T. (2012). Low-power high-resolution delta-sigma ADC design techniques. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/29740

Chicago Manual of Style (16th Edition):

Wang, Tao. “Low-power high-resolution delta-sigma ADC design techniques.” 2012. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/29740.

MLA Handbook (7th Edition):

Wang, Tao. “Low-power high-resolution delta-sigma ADC design techniques.” 2012. Web. 18 Oct 2019.

Vancouver:

Wang T. Low-power high-resolution delta-sigma ADC design techniques. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/29740.

Council of Science Editors:

Wang T. Low-power high-resolution delta-sigma ADC design techniques. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29740


Oregon State University

20. Kuo, Ming-Hung. Low-power high-linearity digital-to-analog converters.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB)… (more)

Subjects/Keywords: DAC; Digital-to-analog converters  – Design and construction

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APA (6th Edition):

Kuo, M. (2012). Low-power high-linearity digital-to-analog converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/28313

Chicago Manual of Style (16th Edition):

Kuo, Ming-Hung. “Low-power high-linearity digital-to-analog converters.” 2012. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/28313.

MLA Handbook (7th Edition):

Kuo, Ming-Hung. “Low-power high-linearity digital-to-analog converters.” 2012. Web. 18 Oct 2019.

Vancouver:

Kuo M. Low-power high-linearity digital-to-analog converters. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/28313.

Council of Science Editors:

Kuo M. Low-power high-linearity digital-to-analog converters. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/28313


Hong Kong University of Science and Technology

21. Lo, Ming Yam. Design and implementation of analog continuous-time min-sum iterative decoders.

Degree: 2010, Hong Kong University of Science and Technology

 IN THIS THESIS, the concept of analog decoding as a power-saving implementation alternative to the traditional digital decoding is introduced. The advantages and disadvantages of… (more)

Subjects/Keywords: Analog-to-digital converters  – Design and construction; Coding theory

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APA (6th Edition):

Lo, M. Y. (2010). Design and implementation of analog continuous-time min-sum iterative decoders. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1114806 ; http://repository.ust.hk/ir/bitstream/1783.1-6959/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo, Ming Yam. “Design and implementation of analog continuous-time min-sum iterative decoders.” 2010. Thesis, Hong Kong University of Science and Technology. Accessed October 18, 2019. https://doi.org/10.14711/thesis-b1114806 ; http://repository.ust.hk/ir/bitstream/1783.1-6959/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo, Ming Yam. “Design and implementation of analog continuous-time min-sum iterative decoders.” 2010. Web. 18 Oct 2019.

Vancouver:

Lo MY. Design and implementation of analog continuous-time min-sum iterative decoders. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2010. [cited 2019 Oct 18]. Available from: https://doi.org/10.14711/thesis-b1114806 ; http://repository.ust.hk/ir/bitstream/1783.1-6959/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo MY. Design and implementation of analog continuous-time min-sum iterative decoders. [Thesis]. Hong Kong University of Science and Technology; 2010. Available from: https://doi.org/10.14711/thesis-b1114806 ; http://repository.ust.hk/ir/bitstream/1783.1-6959/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

22. Chen, Chia-Hung. Micropower incremental analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Incremental ADCs (IADCs) have many advantages for low-frequency high-accuracy data conversion—they are easy to multiplex between channels, need simpler digital decimation filter, and allow extended… (more)

Subjects/Keywords: IADC; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Chen, C. (2013). Micropower incremental analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/44655

Chicago Manual of Style (16th Edition):

Chen, Chia-Hung. “Micropower incremental analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/44655.

MLA Handbook (7th Edition):

Chen, Chia-Hung. “Micropower incremental analog-to-digital converters.” 2013. Web. 18 Oct 2019.

Vancouver:

Chen C. Micropower incremental analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/44655.

Council of Science Editors:

Chen C. Micropower incremental analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/44655


Oregon State University

23. Rajaee, Omid. Design of low OSR, high precision analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy… (more)

Subjects/Keywords: Oversampled ADC; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Rajaee, O. (2010). Design of low OSR, high precision analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19654

Chicago Manual of Style (16th Edition):

Rajaee, Omid. “Design of low OSR, high precision analog-to-digital converters.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/19654.

MLA Handbook (7th Edition):

Rajaee, Omid. “Design of low OSR, high precision analog-to-digital converters.” 2010. Web. 18 Oct 2019.

Vancouver:

Rajaee O. Design of low OSR, high precision analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/19654.

Council of Science Editors:

Rajaee O. Design of low OSR, high precision analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19654


Southern Illinois University

24. Sekar, Ramgopal. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.

Degree: MS, Electrical and Computer Engineering, 2010, Southern Illinois University

  In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC… (more)

Subjects/Keywords: Analog to Digital Converters; Low Power Design; Successive Approximation Register ADC

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APA (6th Edition):

Sekar, R. (2010). LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. (Masters Thesis). Southern Illinois University. Retrieved from http://opensiuc.lib.siu.edu/theses/350

Chicago Manual of Style (16th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Masters Thesis, Southern Illinois University. Accessed October 18, 2019. http://opensiuc.lib.siu.edu/theses/350.

MLA Handbook (7th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Web. 18 Oct 2019.

Vancouver:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Internet] [Masters thesis]. Southern Illinois University; 2010. [cited 2019 Oct 18]. Available from: http://opensiuc.lib.siu.edu/theses/350.

Council of Science Editors:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Masters Thesis]. Southern Illinois University; 2010. Available from: http://opensiuc.lib.siu.edu/theses/350


University of Waterloo

25. Bray, Adam. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.

Degree: 2013, University of Waterloo

 Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and… (more)

Subjects/Keywords: ADC; Analog to Digital Converter; Converters; Jitter; Timing Skew; Interleaved; TI-ADC; Time Interleaved; Analog

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APA (6th Edition):

Bray, A. (2013). A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Thesis, University of Waterloo. Accessed October 18, 2019. http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Web. 18 Oct 2019.

Vancouver:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

26. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: 2013, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA (6th Edition):

Vasudevamurthy, R. (2013). Time-based All-Digital Technique for Analog Built-in Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Thesis, Indian Institute of Science. Accessed October 18, 2019. http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Web. 18 Oct 2019.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

27. Choi, Ricky Yiu-kee. An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch.

Degree: 2012, Hong Kong University of Science and Technology

 Successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some… (more)

Subjects/Keywords: Analog-to-digital converters  – Design and construction; Electric filters; Comparator circuits  – Design and construction

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APA (6th Edition):

Choi, R. Y. (2012). An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Choi, Ricky Yiu-kee. “An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed October 18, 2019. https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Choi, Ricky Yiu-kee. “An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch.” 2012. Web. 18 Oct 2019.

Vancouver:

Choi RY. An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2019 Oct 18]. Available from: https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Choi RY. An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

28. Peker, Shaul. Complex incremental ΣΔ ADC.

Degree: 2013, Ryerson University

 This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches… (more)

Subjects/Keywords: Modulators (Electronics); Analog-to-digital converters.; Graphical user interfaces (Computer systems); Metal oxide semiconductors, Complementary.

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APA (6th Edition):

Peker, S. (2013). Complex incremental ΣΔ ADC. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A2783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Peker, Shaul. “Complex incremental ΣΔ ADC.” 2013. Thesis, Ryerson University. Accessed October 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A2783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Peker, Shaul. “Complex incremental ΣΔ ADC.” 2013. Web. 18 Oct 2019.

Vancouver:

Peker S. Complex incremental ΣΔ ADC. [Internet] [Thesis]. Ryerson University; 2013. [cited 2019 Oct 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Peker S. Complex incremental ΣΔ ADC. [Thesis]. Ryerson University; 2013. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

29. Jayaraman, Karthik. RF Frontend for Spectrum Analysis in Cognitive Radio.

Degree: 2014, Columbia University

 Advances in wireless technology have sparked a plethora of mobile communication standards to support a variety of applications. FCC predicts a looming crisis due to… (more)

Subjects/Keywords: Cognitive radio networks; Analog-to-digital converters; Wireless communication systems; Electrical engineering

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APA (6th Edition):

Jayaraman, K. (2014). RF Frontend for Spectrum Analysis in Cognitive Radio. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8ZC810Z

Chicago Manual of Style (16th Edition):

Jayaraman, Karthik. “RF Frontend for Spectrum Analysis in Cognitive Radio.” 2014. Doctoral Dissertation, Columbia University. Accessed October 18, 2019. https://doi.org/10.7916/D8ZC810Z.

MLA Handbook (7th Edition):

Jayaraman, Karthik. “RF Frontend for Spectrum Analysis in Cognitive Radio.” 2014. Web. 18 Oct 2019.

Vancouver:

Jayaraman K. RF Frontend for Spectrum Analysis in Cognitive Radio. [Internet] [Doctoral dissertation]. Columbia University; 2014. [cited 2019 Oct 18]. Available from: https://doi.org/10.7916/D8ZC810Z.

Council of Science Editors:

Jayaraman K. RF Frontend for Spectrum Analysis in Cognitive Radio. [Doctoral Dissertation]. Columbia University; 2014. Available from: https://doi.org/10.7916/D8ZC810Z


Ryerson University

30. Zhu, Guangyu. Time-mode signal processing and application in ΔΣ ADC design.

Degree: 2014, Ryerson University

 An all-digitally implemented 1st order and a 2nd order time-mode ΔΣ ADCs are proposed and presented in this dissertation. Each proposed ΔΣ ADC consists of… (more)

Subjects/Keywords: Signal processing  – Digital techniques; Analog-to-digital converters  – Design and construction; Signal processing  – Digital techniques  – Computer simulation

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APA (6th Edition):

Zhu, G. (2014). Time-mode signal processing and application in ΔΣ ADC design. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A3465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhu, Guangyu. “Time-mode signal processing and application in ΔΣ ADC design.” 2014. Thesis, Ryerson University. Accessed October 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A3465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhu, Guangyu. “Time-mode signal processing and application in ΔΣ ADC design.” 2014. Web. 18 Oct 2019.

Vancouver:

Zhu G. Time-mode signal processing and application in ΔΣ ADC design. [Internet] [Thesis]. Ryerson University; 2014. [cited 2019 Oct 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhu G. Time-mode signal processing and application in ΔΣ ADC design. [Thesis]. Ryerson University; 2014. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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