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You searched for subject:(Analog to digital converter ADC ). Showing records 1 – 30 of 49006 total matches.

[1] [2] [3] [4] [5] … [1634]

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Texas A&M University

1. Larsson, Andreas 1978-. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.

Degree: PhD, Electrical Engineering, 2012, Texas A&M University

 The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher… (more)

Subjects/Keywords: Analog/Mixed Signal Design; Switched-Capacitor; Analog-To-Digital Converter (ADC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Larsson, A. 1. (2012). Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148307

Chicago Manual of Style (16th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Doctoral Dissertation, Texas A&M University. Accessed October 21, 2020. http://hdl.handle.net/1969.1/148307.

MLA Handbook (7th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Web. 21 Oct 2020.

Vancouver:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/1969.1/148307.

Council of Science Editors:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148307


University of Waterloo

2. Bray, Adam. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.

Degree: 2013, University of Waterloo

 Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and… (more)

Subjects/Keywords: ADC; Analog to Digital Converter; Converters; Jitter; Timing Skew; Interleaved; TI-ADC; Time Interleaved; Analog

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APA (6th Edition):

Bray, A. (2013). A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Thesis, University of Waterloo. Accessed October 21, 2020. http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Web. 21 Oct 2020.

Vancouver:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Carnegie Mellon University

3. Liu, Shaolong. SAR ADCs Design and Calibration in Nano-scaled Technologies.

Degree: 2017, Carnegie Mellon University

 The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital(more)

Subjects/Keywords: ADC; analog-to-digital converter; Calibration; Integrated circuits; Low power; Offset

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APA (6th Edition):

Liu, S. (2017). SAR ADCs Design and Calibration in Nano-scaled Technologies. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/1073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Shaolong. “SAR ADCs Design and Calibration in Nano-scaled Technologies.” 2017. Thesis, Carnegie Mellon University. Accessed October 21, 2020. http://repository.cmu.edu/dissertations/1073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Shaolong. “SAR ADCs Design and Calibration in Nano-scaled Technologies.” 2017. Web. 21 Oct 2020.

Vancouver:

Liu S. SAR ADCs Design and Calibration in Nano-scaled Technologies. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2020 Oct 21]. Available from: http://repository.cmu.edu/dissertations/1073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu S. SAR ADCs Design and Calibration in Nano-scaled Technologies. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/1073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

4. Mirhaj, Seyed Arash. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.

Degree: Electrical Engineering, 2014, UCLA

 In recent years, Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) has received significant attention due to its well-known energy and hardware efficiency, which also benefits even… (more)

Subjects/Keywords: Electrical engineering; Analog to Digital Converter; Calibration; Piecewise Linear; SAR-ADC

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APA (6th Edition):

Mirhaj, S. A. (2014). Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Thesis, UCLA. Accessed October 21, 2020. http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Web. 21 Oct 2020.

Vancouver:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Oct 21]. Available from: http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Ito, Tomohiko. 無線通信システム用A/D変換器の高性能化に関する研究.

Degree: 博士(工学), 2013, Hosei University / 法政大学

 To realize next-generation high-throughput wireless communication systems, it is essential to develop analog-to-digital converters (ADC) with high conversion speed, high resolution, low power, and low… (more)

Subjects/Keywords: ADC; A/D; Analog-to-Digital Converter; Pipeline; Flash; Wireless; Receiver

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APA (6th Edition):

Ito, T. (2013). 無線通信システム用A/D変換器の高性能化に関する研究. (Thesis). Hosei University / 法政大学. Retrieved from http://hdl.handle.net/10114/9760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ito, Tomohiko. “無線通信システム用A/D変換器の高性能化に関する研究.” 2013. Thesis, Hosei University / 法政大学. Accessed October 21, 2020. http://hdl.handle.net/10114/9760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ito, Tomohiko. “無線通信システム用A/D変換器の高性能化に関する研究.” 2013. Web. 21 Oct 2020.

Vancouver:

Ito T. 無線通信システム用A/D変換器の高性能化に関する研究. [Internet] [Thesis]. Hosei University / 法政大学; 2013. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/10114/9760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ito T. 無線通信システム用A/D変換器の高性能化に関する研究. [Thesis]. Hosei University / 法政大学; 2013. Available from: http://hdl.handle.net/10114/9760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Lindeberg, Johan. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); Cyclic; Algorithmic; Incremental; Capacitor mismatch; Compensation

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APA (6th Edition):

Lindeberg, J. (2014). Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lindeberg, Johan. “Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.” 2014. Thesis, Linköping UniversityLinköping University. Accessed October 21, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lindeberg, Johan. “Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.” 2014. Web. 21 Oct 2020.

Vancouver:

Lindeberg J. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2020 Oct 21]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lindeberg J. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Majidi, Rabeeh. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.

Degree: PhD, 2015, Worcester Polytechnic Institute

 With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve… (more)

Subjects/Keywords: Analog to Digital Converter ADC SAR Flash Frequenc

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APA (6th Edition):

Majidi, R. (2015). DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. (Doctoral Dissertation). Worcester Polytechnic Institute. Retrieved from etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275

Chicago Manual of Style (16th Edition):

Majidi, Rabeeh. “DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.” 2015. Doctoral Dissertation, Worcester Polytechnic Institute. Accessed October 21, 2020. etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275.

MLA Handbook (7th Edition):

Majidi, Rabeeh. “DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.” 2015. Web. 21 Oct 2020.

Vancouver:

Majidi R. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. [Internet] [Doctoral dissertation]. Worcester Polytechnic Institute; 2015. [cited 2020 Oct 21]. Available from: etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275.

Council of Science Editors:

Majidi R. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. [Doctoral Dissertation]. Worcester Polytechnic Institute; 2015. Available from: etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275


Indian Institute of Science

8. Harish, C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.

Degree: MSc Engg, Faculty of Engineering, 2013, Indian Institute of Science

 This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); CMOS Technologies; Analog to Digital Signal Processing; Sigma Delta ADC; Wireless Applications; Communication Engineering

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APA (6th Edition):

Harish, C. (2013). Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2049

Chicago Manual of Style (16th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2013. Masters Thesis, Indian Institute of Science. Accessed October 21, 2020. http://etd.iisc.ac.in/handle/2005/2049.

MLA Handbook (7th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2013. Web. 21 Oct 2020.

Vancouver:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Internet] [Masters thesis]. Indian Institute of Science; 2013. [cited 2020 Oct 21]. Available from: http://etd.iisc.ac.in/handle/2005/2049.

Council of Science Editors:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Masters Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ac.in/handle/2005/2049


NSYSU

9. Chen, Bang-Cyuan. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is… (more)

Subjects/Keywords: SAR; ADC; Low Power; Pipelined-SAR ADC; Pipelined; Analog-to-Digital Converter

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APA (6th Edition):

Chen, B. (2013). A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Thesis, NSYSU. Accessed October 21, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Bang-Cyuan. “A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design.” 2013. Web. 21 Oct 2020.

Vancouver:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Oct 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen B. A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-165815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

10. Chen, Long. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.

Degree: PhD, Electrical and Computer engineering, 2016, University of Texas – Austin

 This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two… (more)

Subjects/Keywords: Analog-to-digital converter; SAR ADC; ADC; Low power; Comparator; High speed

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APA (6th Edition):

Chen, L. (2016). Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/40286

Chicago Manual of Style (16th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed October 21, 2020. http://hdl.handle.net/2152/40286.

MLA Handbook (7th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Web. 21 Oct 2020.

Vancouver:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/2152/40286.

Council of Science Editors:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/40286


University of Michigan

11. Fredenburg, Jeffrey Alan. Noise-Shaping SAR ADCs.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping… (more)

Subjects/Keywords: Analog-to-Digital Converter; Noise-shaping SAR; Successive-approximation ADC; Analog Circuits; Electrical Engineering; Engineering

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APA (6th Edition):

Fredenburg, J. A. (2015). Noise-Shaping SAR ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113647

Chicago Manual of Style (16th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Doctoral Dissertation, University of Michigan. Accessed October 21, 2020. http://hdl.handle.net/2027.42/113647.

MLA Handbook (7th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Web. 21 Oct 2020.

Vancouver:

Fredenburg JA. Noise-Shaping SAR ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/2027.42/113647.

Council of Science Editors:

Fredenburg JA. Noise-Shaping SAR ADCs. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113647


Oregon State University

12. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC(more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed October 21, 2020. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 21 Oct 2020.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


NSYSU

13. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed October 21, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 21 Oct 2020.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Oct 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

14. Lim, Yong. Energy Efficient Pipeline ADCs Using Ring Amplifiers.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the… (more)

Subjects/Keywords: Ring Amplifier; Analog to Digital Converter; Pipeline ADC; Switched Capacitor; Energy Efficient ADC; Low Power ADC; Electrical Engineering; Engineering

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APA (6th Edition):

Lim, Y. (2017). Energy Efficient Pipeline ADCs Using Ring Amplifiers. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138759

Chicago Manual of Style (16th Edition):

Lim, Yong. “Energy Efficient Pipeline ADCs Using Ring Amplifiers.” 2017. Doctoral Dissertation, University of Michigan. Accessed October 21, 2020. http://hdl.handle.net/2027.42/138759.

MLA Handbook (7th Edition):

Lim, Yong. “Energy Efficient Pipeline ADCs Using Ring Amplifiers.” 2017. Web. 21 Oct 2020.

Vancouver:

Lim Y. Energy Efficient Pipeline ADCs Using Ring Amplifiers. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/2027.42/138759.

Council of Science Editors:

Lim Y. Energy Efficient Pipeline ADCs Using Ring Amplifiers. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138759


University of British Columbia

15. Sheikhaei, Samad. A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS.

Degree: PhD, Electrical and Computer Engineering, 2008, University of British Columbia

 The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed… (more)

Subjects/Keywords: Analog-to-digital converter; Flash ADC

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APA (6th Edition):

Sheikhaei, S. (2008). A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS. (Doctoral Dissertation). University of British Columbia. Retrieved from http://hdl.handle.net/2429/2746

Chicago Manual of Style (16th Edition):

Sheikhaei, Samad. “A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS.” 2008. Doctoral Dissertation, University of British Columbia. Accessed October 21, 2020. http://hdl.handle.net/2429/2746.

MLA Handbook (7th Edition):

Sheikhaei, Samad. “A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS.” 2008. Web. 21 Oct 2020.

Vancouver:

Sheikhaei S. A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS. [Internet] [Doctoral dissertation]. University of British Columbia; 2008. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/2429/2746.

Council of Science Editors:

Sheikhaei S. A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS. [Doctoral Dissertation]. University of British Columbia; 2008. Available from: http://hdl.handle.net/2429/2746

16. Pham, Long. Lookup-Table-Based Background Linearization for VCO-Based ADCs.

Degree: MS, 2015, Worcester Polytechnic Institute

 Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic… (more)

Subjects/Keywords: linearization; Lookup-table; split ADC; votlage controlled oscillator; background calibration technique; Analog to digital converter; VCO-based ADC

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APA (6th Edition):

Pham, L. (2015). Lookup-Table-Based Background Linearization for VCO-Based ADCs. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-043015-093200 ; https://digitalcommons.wpi.edu/etd-theses/586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pham, Long. “Lookup-Table-Based Background Linearization for VCO-Based ADCs.” 2015. Thesis, Worcester Polytechnic Institute. Accessed October 21, 2020. etd-043015-093200 ; https://digitalcommons.wpi.edu/etd-theses/586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pham, Long. “Lookup-Table-Based Background Linearization for VCO-Based ADCs.” 2015. Web. 21 Oct 2020.

Vancouver:

Pham L. Lookup-Table-Based Background Linearization for VCO-Based ADCs. [Internet] [Thesis]. Worcester Polytechnic Institute; 2015. [cited 2020 Oct 21]. Available from: etd-043015-093200 ; https://digitalcommons.wpi.edu/etd-theses/586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pham L. Lookup-Table-Based Background Linearization for VCO-Based ADCs. [Thesis]. Worcester Polytechnic Institute; 2015. Available from: etd-043015-093200 ; https://digitalcommons.wpi.edu/etd-theses/586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Croughwell, Rosamaria. A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter.

Degree: MS, 2007, Worcester Polytechnic Institute

 "This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters… (more)

Subjects/Keywords: A/D Converter; Interleaved ADC; ADC; split-ADC; Analog-to-Digital Converter

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APA (6th Edition):

Croughwell, R. (2007). A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-082507-073448 ; https://digitalcommons.wpi.edu/etd-theses/974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Croughwell, Rosamaria. “A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter.” 2007. Thesis, Worcester Polytechnic Institute. Accessed October 21, 2020. etd-082507-073448 ; https://digitalcommons.wpi.edu/etd-theses/974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Croughwell, Rosamaria. “A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter.” 2007. Web. 21 Oct 2020.

Vancouver:

Croughwell R. A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter. [Internet] [Thesis]. Worcester Polytechnic Institute; 2007. [cited 2020 Oct 21]. Available from: etd-082507-073448 ; https://digitalcommons.wpi.edu/etd-theses/974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Croughwell R. A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter. [Thesis]. Worcester Polytechnic Institute; 2007. Available from: etd-082507-073448 ; https://digitalcommons.wpi.edu/etd-theses/974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

18. Lin, Yingyan. Energy-efficient systems for information transfer and processing.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Machine learning (ML) systems are finding excellent utility in tackling the data deluge of the big data era thanks to the exponential increase in computing… (more)

Subjects/Keywords: Machine learning; Energy efficiency; Analog-to-digital converter; Bit-error-rate optimal analog-to-digital converter (ADC); Convolutional neural networks; Sparsity; Statistical error compensation; Near threshold computing

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APA (6th Edition):

Lin, Y. (2017). Energy-efficient systems for information transfer and processing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98139

Chicago Manual of Style (16th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 21, 2020. http://hdl.handle.net/2142/98139.

MLA Handbook (7th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Web. 21 Oct 2020.

Vancouver:

Lin Y. Energy-efficient systems for information transfer and processing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/2142/98139.

Council of Science Editors:

Lin Y. Energy-efficient systems for information transfer and processing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98139


Universidade do Rio Grande do Sul

19. Aguirre, Paulo Cesar Comassetto de. Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD.

Degree: 2014, Universidade do Rio Grande do Sul

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre… (more)

Subjects/Keywords: Sigma-delta modulation; Conversor analogico/digital; Continuous-time sigma-delta modulator; Modulação; Simulação numérica; Analog-to-digital converter (ADC); Behavioral modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aguirre, P. C. C. d. (2014). Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/105065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aguirre, Paulo Cesar Comassetto de. “Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed October 21, 2020. http://hdl.handle.net/10183/105065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aguirre, Paulo Cesar Comassetto de. “Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD.” 2014. Web. 21 Oct 2020.

Vancouver:

Aguirre PCCd. Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/10183/105065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aguirre PCCd. Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/105065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

20. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 21, 2020. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 21 Oct 2020.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709


Oregon State University

21. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed October 21, 2020. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 21 Oct 2020.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


Université de Grenoble

22. Regis, Guillaume. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.

Degree: Docteur es, Physique Expérimentale et Instrumentation, 2011, Université de Grenoble

Le domaine de l'instrumentation des capteurs est en constante évolution. Ce travail propose la conception des éléments clefs qui constituent les chaines d'instrumentations de capteurs… (more)

Subjects/Keywords: Convertisseur Analogique/Numérique; CAN SAR; CAN Sigma Delta; Chaine d’amplification analogique; Analog-to-Digital Converter; ADC SAR; ADC Sigma Delta; Analog amplifier

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APA (6th Edition):

Regis, G. (2011). Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENA001

Chicago Manual of Style (16th Edition):

Regis, Guillaume. “Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed October 21, 2020. http://www.theses.fr/2011GRENA001.

MLA Handbook (7th Edition):

Regis, Guillaume. “Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning.” 2011. Web. 21 Oct 2020.

Vancouver:

Regis G. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2020 Oct 21]. Available from: http://www.theses.fr/2011GRENA001.

Council of Science Editors:

Regis G. Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués : Analogical-digital circuits conception for embedded micro-sensors conditioning. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENA001


Punjabi University

23. Mohanty, Biraja Prasad. Particle induced x ray cross section measurements and pixe analysis of forensic samples; -.

Degree: Physics, 2010, Punjabi University

In the first chapter, basic aspects of ion atom collisions are discussed. Collisions of heavy ions with atoms define one of the most active areas… (more)

Subjects/Keywords: Particle induced x-ray emission (PIXE); Ion Beam; Analog to Digital Converter (ADC); x-ray spectrum; Gunshot residue (GSR)

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APA (6th Edition):

Mohanty, B. P. (2010). Particle induced x ray cross section measurements and pixe analysis of forensic samples; -. (Thesis). Punjabi University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/4929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohanty, Biraja Prasad. “Particle induced x ray cross section measurements and pixe analysis of forensic samples; -.” 2010. Thesis, Punjabi University. Accessed October 21, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/4929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohanty, Biraja Prasad. “Particle induced x ray cross section measurements and pixe analysis of forensic samples; -.” 2010. Web. 21 Oct 2020.

Vancouver:

Mohanty BP. Particle induced x ray cross section measurements and pixe analysis of forensic samples; -. [Internet] [Thesis]. Punjabi University; 2010. [cited 2020 Oct 21]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/4929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohanty BP. Particle induced x ray cross section measurements and pixe analysis of forensic samples; -. [Thesis]. Punjabi University; 2010. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/4929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

24. Lee, Keytaek. High-Speed Link Modeling: Analog/Digital Equalization and Modulation Techniques.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 High-speed serial input-output (I/O) link has required advanced equalization and modulation techniques to mitigate inter-symbol interference (ISI) caused by multi-Gb/s signaling over band-limited channels. Increasing… (more)

Subjects/Keywords: Analog-to-digital converter (ADC); equalization; modulation; I/O link; link analysis tools; statistical signaling analysis

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APA (6th Edition):

Lee, K. (2012). High-Speed Link Modeling: Analog/Digital Equalization and Modulation Techniques. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11000

Chicago Manual of Style (16th Edition):

Lee, Keytaek. “High-Speed Link Modeling: Analog/Digital Equalization and Modulation Techniques.” 2012. Masters Thesis, Texas A&M University. Accessed October 21, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11000.

MLA Handbook (7th Edition):

Lee, Keytaek. “High-Speed Link Modeling: Analog/Digital Equalization and Modulation Techniques.” 2012. Web. 21 Oct 2020.

Vancouver:

Lee K. High-Speed Link Modeling: Analog/Digital Equalization and Modulation Techniques. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11000.

Council of Science Editors:

Lee K. High-Speed Link Modeling: Analog/Digital Equalization and Modulation Techniques. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11000


Universidade Nova

25. Silva, Alexandre Herculano Mendes. Pipelined analog-to-digital conversion using current-mode reference shifting.

Degree: 2012, Universidade Nova

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Pipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high… (more)

Subjects/Keywords: Analog-to-Digital Converter (ADC),; Current-mode reference shifting; Switched-capacitor; CMOS current reference; pipelined A/D conversion

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APA (6th Edition):

Silva, A. H. M. (2012). Pipelined analog-to-digital conversion using current-mode reference shifting. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Silva, Alexandre Herculano Mendes. “Pipelined analog-to-digital conversion using current-mode reference shifting.” 2012. Thesis, Universidade Nova. Accessed October 21, 2020. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Silva, Alexandre Herculano Mendes. “Pipelined analog-to-digital conversion using current-mode reference shifting.” 2012. Web. 21 Oct 2020.

Vancouver:

Silva AHM. Pipelined analog-to-digital conversion using current-mode reference shifting. [Internet] [Thesis]. Universidade Nova; 2012. [cited 2020 Oct 21]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Silva AHM. Pipelined analog-to-digital conversion using current-mode reference shifting. [Thesis]. Universidade Nova; 2012. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boston University

26. Yang, Jiao. Design of a low power 8-bit A/D converter for wireless neural recorder applications.

Degree: MS, Electrical & Computer Engineering, 2017, Boston University

 Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues… (more)

Subjects/Keywords: Electrical engineering; Energy-saving capacitor array; Low power design; Neural recorder applications; Successive approximation register analog-to-digital converter (SAR-ADC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2017). Design of a low power 8-bit A/D converter for wireless neural recorder applications. (Masters Thesis). Boston University. Retrieved from http://hdl.handle.net/2144/23685

Chicago Manual of Style (16th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Masters Thesis, Boston University. Accessed October 21, 2020. http://hdl.handle.net/2144/23685.

MLA Handbook (7th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Web. 21 Oct 2020.

Vancouver:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Internet] [Masters thesis]. Boston University; 2017. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/2144/23685.

Council of Science Editors:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Masters Thesis]. Boston University; 2017. Available from: http://hdl.handle.net/2144/23685


Linköping University

27. Khan, Shehryar. Study on Zero-Crossing-Based ADCs for Smart Dust Applications.

Degree: Electronics System, 2011, Linköping University

  The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart… (more)

Subjects/Keywords: smart dust; Comparator Based Switched Capacitor (CBSC); Zero Crossing Based Circuit(ZCBC); Analog to Digital Converter (ADC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khan, S. (2011). Study on Zero-Crossing-Based ADCs for Smart Dust Applications. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khan, Shehryar. “Study on Zero-Crossing-Based ADCs for Smart Dust Applications.” 2011. Thesis, Linköping University. Accessed October 21, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khan, Shehryar. “Study on Zero-Crossing-Based ADCs for Smart Dust Applications.” 2011. Web. 21 Oct 2020.

Vancouver:

Khan S. Study on Zero-Crossing-Based ADCs for Smart Dust Applications. [Internet] [Thesis]. Linköping University; 2011. [cited 2020 Oct 21]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khan S. Study on Zero-Crossing-Based ADCs for Smart Dust Applications. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

28. Kozina, Lubomír. Ověření parametrů USB modulů: USB modules verification.

Degree: 2018, Brno University of Technology

 In the bachelor´s thesis on the topic USB modules verification I was engaged in National Instruments modules, especially in module NI USB-6008. I have been… (more)

Subjects/Keywords: analogově digitální převodník (A/D); doba vzorkování; synchronní vzorkování; LabVIEW; analog-to-digital converter (ADC); sampling time; synchronous sampling; LabVIEW

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kozina, L. (2018). Ověření parametrů USB modulů: USB modules verification. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/3238

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kozina, Lubomír. “Ověření parametrů USB modulů: USB modules verification.” 2018. Thesis, Brno University of Technology. Accessed October 21, 2020. http://hdl.handle.net/11012/3238.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kozina, Lubomír. “Ověření parametrů USB modulů: USB modules verification.” 2018. Web. 21 Oct 2020.

Vancouver:

Kozina L. Ověření parametrů USB modulů: USB modules verification. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/11012/3238.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kozina L. Ověření parametrů USB modulů: USB modules verification. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/3238

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

29. Aust, Carrie Ellen. A Low-Power, Variable-Resolution Analog-to-Digital Converter.

Degree: MS, Electrical and Computer Engineering, 2000, Virginia Tech

Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet… (more)

Subjects/Keywords: Analog-to-digital converter; ADC; Low power; Variable resolution

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aust, C. E. (2000). A Low-Power, Variable-Resolution Analog-to-Digital Converter. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33737

Chicago Manual of Style (16th Edition):

Aust, Carrie Ellen. “A Low-Power, Variable-Resolution Analog-to-Digital Converter.” 2000. Masters Thesis, Virginia Tech. Accessed October 21, 2020. http://hdl.handle.net/10919/33737.

MLA Handbook (7th Edition):

Aust, Carrie Ellen. “A Low-Power, Variable-Resolution Analog-to-Digital Converter.” 2000. Web. 21 Oct 2020.

Vancouver:

Aust CE. A Low-Power, Variable-Resolution Analog-to-Digital Converter. [Internet] [Masters thesis]. Virginia Tech; 2000. [cited 2020 Oct 21]. Available from: http://hdl.handle.net/10919/33737.

Council of Science Editors:

Aust CE. A Low-Power, Variable-Resolution Analog-to-Digital Converter. [Masters Thesis]. Virginia Tech; 2000. Available from: http://hdl.handle.net/10919/33737

30. Carter, Nathan R. A 12-b 50Msample/s Pipeline Analog to Digital Converter.

Degree: MS, 2000, Worcester Polytechnic Institute

 This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC(more)

Subjects/Keywords: digital; converter; analog; flash; ADC; folding; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carter, N. R. (2000). A 12-b 50Msample/s Pipeline Analog to Digital Converter. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carter, Nathan R. “A 12-b 50Msample/s Pipeline Analog to Digital Converter.” 2000. Thesis, Worcester Polytechnic Institute. Accessed October 21, 2020. etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carter, Nathan R. “A 12-b 50Msample/s Pipeline Analog to Digital Converter.” 2000. Web. 21 Oct 2020.

Vancouver:

Carter NR. A 12-b 50Msample/s Pipeline Analog to Digital Converter. [Internet] [Thesis]. Worcester Polytechnic Institute; 2000. [cited 2020 Oct 21]. Available from: etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carter NR. A 12-b 50Msample/s Pipeline Analog to Digital Converter. [Thesis]. Worcester Polytechnic Institute; 2000. Available from: etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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