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You searched for subject:(Analog to Digital Waveforms). Showing records 1 – 30 of 43570 total matches.

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Indian Institute of Science

1. Chandravadan, Vora Santoshkumar. Novel Methods For Estimation Of Static Nonlinearity Of High-Speed High-Resolution Waveform Digitizers.

Degree: 2009, Indian Institute of Science

Analog-to-digital converter (ADC) is the main workhorse in a digital waveform recorder. Strictly speaking, an ADC is supposed to perform uniformly, irrespective of the characteristics… (more)

Subjects/Keywords: Analog-to-Digital Waveforms; Electric Converters; Analog-to-Digital Converters (ADC); Digital Electronics; Waveform Digitizers; Analog-to-Digital Converters - Nonlinearity; Static Nonlinearity; Dynamic Nonlinearity; Low Linearity Ramp; Electrical Engineering

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APA (6th Edition):

Chandravadan, V. S. (2009). Novel Methods For Estimation Of Static Nonlinearity Of High-Speed High-Resolution Waveform Digitizers. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chandravadan, Vora Santoshkumar. “Novel Methods For Estimation Of Static Nonlinearity Of High-Speed High-Resolution Waveform Digitizers.” 2009. Thesis, Indian Institute of Science. Accessed April 01, 2020. http://hdl.handle.net/2005/1019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chandravadan, Vora Santoshkumar. “Novel Methods For Estimation Of Static Nonlinearity Of High-Speed High-Resolution Waveform Digitizers.” 2009. Web. 01 Apr 2020.

Vancouver:

Chandravadan VS. Novel Methods For Estimation Of Static Nonlinearity Of High-Speed High-Resolution Waveform Digitizers. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2005/1019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chandravadan VS. Novel Methods For Estimation Of Static Nonlinearity Of High-Speed High-Resolution Waveform Digitizers. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

2. Maghari, Nima. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR)… (more)

Subjects/Keywords: Analog Ciruits; Analog-to-digital converters

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APA (6th Edition):

Maghari, N. (2010). Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18851

Chicago Manual of Style (16th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/18851.

MLA Handbook (7th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Web. 01 Apr 2020.

Vancouver:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/18851.

Council of Science Editors:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18851


Oregon State University

3. Nishida, Yoshio. Improved design techniques for analog and mixed circuits.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice,… (more)

Subjects/Keywords: analog; Analog-to-digital converters  – Design

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APA (6th Edition):

Nishida, Y. (2008). Improved design techniques for analog and mixed circuits. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7985

Chicago Manual of Style (16th Edition):

Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/7985.

MLA Handbook (7th Edition):

Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Web. 01 Apr 2020.

Vancouver:

Nishida Y. Improved design techniques for analog and mixed circuits. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/7985.

Council of Science Editors:

Nishida Y. Improved design techniques for analog and mixed circuits. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/7985


Oregon State University

4. Hu, Yue. Efficient use of time information in analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information… (more)

Subjects/Keywords: Analog-to-digital converters

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APA (6th Edition):

Hu, Y. (2014). Efficient use of time information in analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/52553

Chicago Manual of Style (16th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/52553.

MLA Handbook (7th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Web. 01 Apr 2020.

Vancouver:

Hu Y. Efficient use of time information in analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/52553.

Council of Science Editors:

Hu Y. Efficient use of time information in analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/52553


Oregon State University

5. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC… (more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 01 Apr 2020.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


Oregon State University

6. Tong, Tao. Design techniques for successive approximation register analog-to-digital converters.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently,… (more)

Subjects/Keywords: analog-to-digital converters

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APA (6th Edition):

Tong, T. (2011). Design techniques for successive approximation register analog-to-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22662

Chicago Manual of Style (16th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Masters Thesis, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/22662.

MLA Handbook (7th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Web. 01 Apr 2020.

Vancouver:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/22662.

Council of Science Editors:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/22662


Ryerson University

7. Park, Young Jun. Time-interleaved pulse-shrinking and all-digital time-to-digital converters.

Degree: 2017, Ryerson University

 This dissertation deals with the design of sub-per-stage delay time-to-digital converters (TDCs). Two classes of TDCs namely pulse-shrinking TDCs and TDCs are investigated. In pulse-shrinking… (more)

Subjects/Keywords: Analog-to-digital converters; Digital-to-analog converters

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APA (6th Edition):

Park, Y. J. (2017). Time-interleaved pulse-shrinking and all-digital time-to-digital converters. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Young Jun. “Time-interleaved pulse-shrinking and all-digital time-to-digital converters.” 2017. Thesis, Ryerson University. Accessed April 01, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Young Jun. “Time-interleaved pulse-shrinking and all-digital time-to-digital converters.” 2017. Web. 01 Apr 2020.

Vancouver:

Park YJ. Time-interleaved pulse-shrinking and all-digital time-to-digital converters. [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 Apr 01]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park YJ. Time-interleaved pulse-shrinking and all-digital time-to-digital converters. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dalhousie University

8. D'souza, Rowena Joan. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2010, Dalhousie University

 This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The… (more)

Subjects/Keywords: Digital-to-analog converters; Time-interleaving

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APA (6th Edition):

D'souza, R. J. (2010). Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/12994

Chicago Manual of Style (16th Edition):

D'souza, Rowena Joan. “Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.” 2010. Masters Thesis, Dalhousie University. Accessed April 01, 2020. http://hdl.handle.net/10222/12994.

MLA Handbook (7th Edition):

D'souza, Rowena Joan. “Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.” 2010. Web. 01 Apr 2020.

Vancouver:

D'souza RJ. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. [Internet] [Masters thesis]. Dalhousie University; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10222/12994.

Council of Science Editors:

D'souza RJ. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. [Masters Thesis]. Dalhousie University; 2010. Available from: http://hdl.handle.net/10222/12994


Oregon State University

9. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 01 Apr 2020.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709


Oregon State University

10. Leung, Jerry. Data driven optimization in SAR ADC.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques… (more)

Subjects/Keywords: SAR; Successive approximation analog-to-digital converters

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APA (6th Edition):

Leung, J. (2014). Data driven optimization in SAR ADC. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/54631

Chicago Manual of Style (16th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Masters Thesis, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/54631.

MLA Handbook (7th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Web. 01 Apr 2020.

Vancouver:

Leung J. Data driven optimization in SAR ADC. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/54631.

Council of Science Editors:

Leung J. Data driven optimization in SAR ADC. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/54631


Oregon State University

11. Waters, Allen. Automated verilog-to-layout synthesis of ADCs using custom analog cells.

Degree: PhD, Electrical and Computer Engineering, 2015, Oregon State University

 A procedure for automating the design and layout of analog-to-digital converters (ADCs) is presented. This procedure makes use of the existing synthesis and place-and-route tools… (more)

Subjects/Keywords: Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Waters, A. (2015). Automated verilog-to-layout synthesis of ADCs using custom analog cells. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/55310

Chicago Manual of Style (16th Edition):

Waters, Allen. “Automated verilog-to-layout synthesis of ADCs using custom analog cells.” 2015. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/55310.

MLA Handbook (7th Edition):

Waters, Allen. “Automated verilog-to-layout synthesis of ADCs using custom analog cells.” 2015. Web. 01 Apr 2020.

Vancouver:

Waters A. Automated verilog-to-layout synthesis of ADCs using custom analog cells. [Internet] [Doctoral dissertation]. Oregon State University; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/55310.

Council of Science Editors:

Waters A. Automated verilog-to-layout synthesis of ADCs using custom analog cells. [Doctoral Dissertation]. Oregon State University; 2015. Available from: http://hdl.handle.net/1957/55310

12. Meganathan D. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.

Degree: A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits, 2014, Anna University

High speed and medium resolution Analog to Digital Converters newline ADC are widely used in commercial applications including data newlinecommunication and image signal processing In… (more)

Subjects/Keywords: Analog to Digital Converters; Complementary Metal Oxide

Page 1

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APA (6th Edition):

D, M. (2014). A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/29245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

D, Meganathan. “A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.” 2014. Thesis, Anna University. Accessed April 01, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/29245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

D, Meganathan. “A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.” 2014. Web. 01 Apr 2020.

Vancouver:

D M. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Apr 01]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

D M. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

13. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 01 Apr 2020.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


Oregon State University

14. Shen, Weilun. Low-power double-sampled delta-sigma modulator for broadband applications.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on.… (more)

Subjects/Keywords: Analog-to-Digital Converter; Modulators (Electronics)

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APA (6th Edition):

Shen, W. (2010). Low-power double-sampled delta-sigma modulator for broadband applications. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/17568

Chicago Manual of Style (16th Edition):

Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/17568.

MLA Handbook (7th Edition):

Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Web. 01 Apr 2020.

Vancouver:

Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/17568.

Council of Science Editors:

Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/17568


Oregon State University

15. Musah, Tawfiq. Low power design techniques for analog-to-digital converters in submicron CMOS.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical… (more)

Subjects/Keywords: correlated level shifting; Analog-to-digital converters

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APA (6th Edition):

Musah, T. (2010). Low power design techniques for analog-to-digital converters in submicron CMOS. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18826

Chicago Manual of Style (16th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/18826.

MLA Handbook (7th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Web. 01 Apr 2020.

Vancouver:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/18826.

Council of Science Editors:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18826


Oregon State University

16. Chae, Jeong Seok. Novel structures for high-speed delta-sigma data converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover,… (more)

Subjects/Keywords: Analog-to-digital converter; Modulators (Electronics)

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APA (6th Edition):

Chae, J. S. (2011). Novel structures for high-speed delta-sigma data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19813

Chicago Manual of Style (16th Edition):

Chae, Jeong Seok. “Novel structures for high-speed delta-sigma data converters.” 2011. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/19813.

MLA Handbook (7th Edition):

Chae, Jeong Seok. “Novel structures for high-speed delta-sigma data converters.” 2011. Web. 01 Apr 2020.

Vancouver:

Chae JS. Novel structures for high-speed delta-sigma data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/19813.

Council of Science Editors:

Chae JS. Novel structures for high-speed delta-sigma data converters. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/19813


Oregon State University

17. Zanbaghi, Ramin. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high… (more)

Subjects/Keywords: delta-sigma modulator; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zanbaghi, R. (2011). Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/23456

Chicago Manual of Style (16th Edition):

Zanbaghi, Ramin. “Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.” 2011. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/23456.

MLA Handbook (7th Edition):

Zanbaghi, Ramin. “Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.” 2011. Web. 01 Apr 2020.

Vancouver:

Zanbaghi R. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/23456.

Council of Science Editors:

Zanbaghi R. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/23456


Oregon State University

18. Oh, Taehwan. Power efficient analog-to-digital converters using both voltage and time domain information.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs… (more)

Subjects/Keywords: Delta-sigma; Analog-to-digital converters

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APA (6th Edition):

Oh, T. (2013). Power efficient analog-to-digital converters using both voltage and time domain information. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39042

Chicago Manual of Style (16th Edition):

Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 01, 2020. http://hdl.handle.net/1957/39042.

MLA Handbook (7th Edition):

Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Web. 01 Apr 2020.

Vancouver:

Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1957/39042.

Council of Science Editors:

Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39042


Hong Kong University of Science and Technology

19. Yang, Shiliang. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.

Degree: 2014, Hong Kong University of Science and Technology

 In the deep sub-micron process, the transistor intrinsic gain is low and the supply voltage is low, resulting in the great difficulty in designing a… (more)

Subjects/Keywords: Analog-to-digital converters ; Calibration ; Operational amplifiers

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APA (6th Edition):

Yang, S. (2014). A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-71878 ; https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Shiliang. “A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed April 01, 2020. http://repository.ust.hk/ir/Record/1783.1-71878 ; https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Shiliang. “A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.” 2014. Web. 01 Apr 2020.

Vancouver:

Yang S. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2020 Apr 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-71878 ; https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang S. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-71878 ; https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

20. Mukhopadhyay, Ishita. Variation Tolerant Calibration Circuits For High Performance I/O .

Degree: 2015, Cornell University

 Continuous scaling of CMOS processes leads to increasing integration of digital and analog subsystems on one chip. But the impact of process variation on these… (more)

Subjects/Keywords: digital to analog converter; process variation; calibration

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APA (6th Edition):

Mukhopadhyay, I. (2015). Variation Tolerant Calibration Circuits For High Performance I/O . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/39348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mukhopadhyay, Ishita. “Variation Tolerant Calibration Circuits For High Performance I/O .” 2015. Thesis, Cornell University. Accessed April 01, 2020. http://hdl.handle.net/1813/39348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mukhopadhyay, Ishita. “Variation Tolerant Calibration Circuits For High Performance I/O .” 2015. Web. 01 Apr 2020.

Vancouver:

Mukhopadhyay I. Variation Tolerant Calibration Circuits For High Performance I/O . [Internet] [Thesis]. Cornell University; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1813/39348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mukhopadhyay I. Variation Tolerant Calibration Circuits For High Performance I/O . [Thesis]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/39348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

21. Larsson, Andreas 1978-. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.

Degree: 2012, Texas A&M University

 The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher… (more)

Subjects/Keywords: Analog/Mixed Signal Design; Switched-Capacitor; Analog-To-Digital Converter (ADC)

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APA (6th Edition):

Larsson, A. 1. (2012). Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Thesis, Texas A&M University. Accessed April 01, 2020. http://hdl.handle.net/1969.1/148307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Web. 01 Apr 2020.

Vancouver:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1969.1/148307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

22. Shirtliff, Jason Neil. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.

Degree: 2010, University of Waterloo

 Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum… (more)

Subjects/Keywords: analog circuit design; timing mismatches; interleaved analog to digital converters; microelectronics

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APA (6th Edition):

Shirtliff, J. N. (2010). Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shirtliff, Jason Neil. “Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.” 2010. Thesis, University of Waterloo. Accessed April 01, 2020. http://hdl.handle.net/10012/5523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shirtliff, Jason Neil. “Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.” 2010. Web. 01 Apr 2020.

Vancouver:

Shirtliff JN. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10012/5523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shirtliff JN. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2010. Available from: http://hdl.handle.net/10012/5523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Nairobi

23. Wafula, Michael J. Design of a PC Data Acquisition System .

Degree: 2014, University of Nairobi

 This report presents the design and implementation of a PC based data acquisition system. The aim of the project is to design a system that… (more)

Subjects/Keywords: Analogue to digital conversion; serial communication; Microcontroller; Sensors.

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APA (6th Edition):

Wafula, M. J. (2014). Design of a PC Data Acquisition System . (Thesis). University of Nairobi. Retrieved from http://hdl.handle.net/11295/71277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wafula, Michael J. “Design of a PC Data Acquisition System .” 2014. Thesis, University of Nairobi. Accessed April 01, 2020. http://hdl.handle.net/11295/71277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wafula, Michael J. “Design of a PC Data Acquisition System .” 2014. Web. 01 Apr 2020.

Vancouver:

Wafula MJ. Design of a PC Data Acquisition System . [Internet] [Thesis]. University of Nairobi; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/11295/71277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wafula MJ. Design of a PC Data Acquisition System . [Thesis]. University of Nairobi; 2014. Available from: http://hdl.handle.net/11295/71277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

24. Wu, Chao ECE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.

Degree: 2018, Hong Kong University of Science and Technology

 High-speed high-precision analog-to-digital converters (ADCs) are widely used in the fields of image processing, information storage and wireless communication. To achieve high speed and high… (more)

Subjects/Keywords: Analog-to-digital converters ; Successive approximation analog-to-digital converters ; Signal processing ; Digital techniques ; Real-time data processing ; Electronic data processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. E. (2018). A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-93162 ; https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chao ECE. “A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.” 2018. Thesis, Hong Kong University of Science and Technology. Accessed April 01, 2020. http://repository.ust.hk/ir/Record/1783.1-93162 ; https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chao ECE. “A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.” 2018. Web. 01 Apr 2020.

Vancouver:

Wu CE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2018. [cited 2020 Apr 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-93162 ; https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu CE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. [Thesis]. Hong Kong University of Science and Technology; 2018. Available from: http://repository.ust.hk/ir/Record/1783.1-93162 ; https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

25. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: 2013, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA (6th Edition):

Vasudevamurthy, R. (2013). Time-based All-Digital Technique for Analog Built-in Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Thesis, Indian Institute of Science. Accessed April 01, 2020. http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Web. 01 Apr 2020.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oxford

26. Levski, Deyan. Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors.

Degree: PhD, 2018, University of Oxford

 This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few… (more)

Subjects/Keywords: Analog to Digital Converters; Engineering Science; Microelectronics; Analog Integrated Circuit Design; Photonics Devices; CMOS Image Sensors; Time to Digital Converter; Pixel; Column Parallel; Analog to Digital Converter

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APA (6th Edition):

Levski, D. (2018). Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors. (Doctoral Dissertation). University of Oxford. Retrieved from http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825

Chicago Manual of Style (16th Edition):

Levski, Deyan. “Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors.” 2018. Doctoral Dissertation, University of Oxford. Accessed April 01, 2020. http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825.

MLA Handbook (7th Edition):

Levski, Deyan. “Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors.” 2018. Web. 01 Apr 2020.

Vancouver:

Levski D. Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors. [Internet] [Doctoral dissertation]. University of Oxford; 2018. [cited 2020 Apr 01]. Available from: http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825.

Council of Science Editors:

Levski D. Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors. [Doctoral Dissertation]. University of Oxford; 2018. Available from: http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825


Indian Institute of Science

27. Harish, C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.

Degree: 2011, Indian Institute of Science

 This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); CMOS Technologies; Analog to Digital Signal Processing; Sigma Delta ADC; Wireless Applications; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harish, C. (2011). Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Thesis, Indian Institute of Science. Accessed April 01, 2020. http://hdl.handle.net/2005/2049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Web. 01 Apr 2020.

Vancouver:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2005/2049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Thesis]. Indian Institute of Science; 2011. Available from: http://hdl.handle.net/2005/2049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)

28. Mountrichas, Lampros. Study and design of analog to digital and digital to analog converters.

Degree: 2016, Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)

In today’s technology with the vast implementation of digital processing analog−to−digital and digital−to−analog converters are some of the most important blocks. The increasing speed of… (more)

Subjects/Keywords: Μετατροπέας αναλογικού σήματος σε ψηφιακό; Μετατροπέας ψηφιακού σήματος σε αναλογικό; Analog to digital converters; Digital to analog converters

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APA (6th Edition):

Mountrichas, L. (2016). Study and design of analog to digital and digital to analog converters. (Thesis). Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/39753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mountrichas, Lampros. “Study and design of analog to digital and digital to analog converters.” 2016. Thesis, Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ). Accessed April 01, 2020. http://hdl.handle.net/10442/hedi/39753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mountrichas, Lampros. “Study and design of analog to digital and digital to analog converters.” 2016. Web. 01 Apr 2020.

Vancouver:

Mountrichas L. Study and design of analog to digital and digital to analog converters. [Internet] [Thesis]. Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ); 2016. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10442/hedi/39753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mountrichas L. Study and design of analog to digital and digital to analog converters. [Thesis]. Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ); 2016. Available from: http://hdl.handle.net/10442/hedi/39753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Harish, C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.

Degree: 2011, Indian Institute of Science

 This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); CMOS Technologies; Analog to Digital Signal Processing; Sigma Delta ADC; Wireless Applications; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harish, C. (2011). Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Thesis, Indian Institute of Science. Accessed April 01, 2020. http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2011. Web. 01 Apr 2020.

Vancouver:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2020 Apr 01]. Available from: http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ernet.in/handle/2005/2049 ; http://etd.ncsi.iisc.ernet.in/abstracts/2645/G24903-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

30. Ankamah-Kusi, Sylvester. An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications.

Degree: MS, Electrical Engineering, 2016, Texas A&M University

 This thesis focuses on designing a low power Pipeline Analog to Digital Converter (ADC) for use in a Cognitive radio network. The Pipeline ADC architecture… (more)

Subjects/Keywords: Analog to Digital Converter; Pipeline; Kick-back; Residue; Distortion; Operational Amplifier; Multiplying Digital to Analog Converter (MDAC); Partial Positive Feedback Amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ankamah-Kusi, S. (2016). An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/159069

Chicago Manual of Style (16th Edition):

Ankamah-Kusi, Sylvester. “An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications.” 2016. Masters Thesis, Texas A&M University. Accessed April 01, 2020. http://hdl.handle.net/1969.1/159069.

MLA Handbook (7th Edition):

Ankamah-Kusi, Sylvester. “An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications.” 2016. Web. 01 Apr 2020.

Vancouver:

Ankamah-Kusi S. An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1969.1/159069.

Council of Science Editors:

Ankamah-Kusi S. An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/159069

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