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You searched for subject:(Analog to Digital Converter). Showing records 1 – 30 of 48690 total matches.

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Cornell University

1. Mukhopadhyay, Ishita. Variation Tolerant Calibration Circuits For High Performance I/O.

Degree: PhD, Electrical Engineering, 2015, Cornell University

 Continuous scaling of CMOS processes leads to increasing integration of digital and analog subsystems on one chip. But the impact of process variation on these… (more)

Subjects/Keywords: digital to analog converter; process variation; calibration

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APA (6th Edition):

Mukhopadhyay, I. (2015). Variation Tolerant Calibration Circuits For High Performance I/O. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/39348

Chicago Manual of Style (16th Edition):

Mukhopadhyay, Ishita. “Variation Tolerant Calibration Circuits For High Performance I/O.” 2015. Doctoral Dissertation, Cornell University. Accessed October 28, 2020. http://hdl.handle.net/1813/39348.

MLA Handbook (7th Edition):

Mukhopadhyay, Ishita. “Variation Tolerant Calibration Circuits For High Performance I/O.” 2015. Web. 28 Oct 2020.

Vancouver:

Mukhopadhyay I. Variation Tolerant Calibration Circuits For High Performance I/O. [Internet] [Doctoral dissertation]. Cornell University; 2015. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1813/39348.

Council of Science Editors:

Mukhopadhyay I. Variation Tolerant Calibration Circuits For High Performance I/O. [Doctoral Dissertation]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/39348


Oregon State University

2. Shen, Weilun. Low-power double-sampled delta-sigma modulator for broadband applications.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on.… (more)

Subjects/Keywords: Analog-to-Digital Converter; Modulators (Electronics)

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APA (6th Edition):

Shen, W. (2010). Low-power double-sampled delta-sigma modulator for broadband applications. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/17568

Chicago Manual of Style (16th Edition):

Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/17568.

MLA Handbook (7th Edition):

Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Web. 28 Oct 2020.

Vancouver:

Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/17568.

Council of Science Editors:

Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/17568


Oregon State University

3. Chae, Jeong Seok. Novel structures for high-speed delta-sigma data converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover,… (more)

Subjects/Keywords: Analog-to-digital converter; Modulators (Electronics)

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APA (6th Edition):

Chae, J. S. (2011). Novel structures for high-speed delta-sigma data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19813

Chicago Manual of Style (16th Edition):

Chae, Jeong Seok. “Novel structures for high-speed delta-sigma data converters.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/19813.

MLA Handbook (7th Edition):

Chae, Jeong Seok. “Novel structures for high-speed delta-sigma data converters.” 2011. Web. 28 Oct 2020.

Vancouver:

Chae JS. Novel structures for high-speed delta-sigma data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/19813.

Council of Science Editors:

Chae JS. Novel structures for high-speed delta-sigma data converters. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/19813


Iowa State University

4. Chaganti, Shravan Kumar. Cost-efficient solutions for analog and mixed-signal test and calibration challenges.

Degree: 2020, Iowa State University

 Integrated Circuits (ICs) are used in a myriad of applications and impact our lives every single day. Some of these applications are mission critical, like… (more)

Subjects/Keywords: Analog to Digital Converter; Calibration; Cost-efficient; Digital to Analog Converter; Testing; VLSI

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APA (6th Edition):

Chaganti, S. K. (2020). Cost-efficient solutions for analog and mixed-signal test and calibration challenges. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/18102

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chaganti, Shravan Kumar. “Cost-efficient solutions for analog and mixed-signal test and calibration challenges.” 2020. Thesis, Iowa State University. Accessed October 28, 2020. https://lib.dr.iastate.edu/etd/18102.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chaganti, Shravan Kumar. “Cost-efficient solutions for analog and mixed-signal test and calibration challenges.” 2020. Web. 28 Oct 2020.

Vancouver:

Chaganti SK. Cost-efficient solutions for analog and mixed-signal test and calibration challenges. [Internet] [Thesis]. Iowa State University; 2020. [cited 2020 Oct 28]. Available from: https://lib.dr.iastate.edu/etd/18102.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chaganti SK. Cost-efficient solutions for analog and mixed-signal test and calibration challenges. [Thesis]. Iowa State University; 2020. Available from: https://lib.dr.iastate.edu/etd/18102

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Larsson, Andreas 1978-. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.

Degree: PhD, Electrical Engineering, 2012, Texas A&M University

 The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher… (more)

Subjects/Keywords: Analog/Mixed Signal Design; Switched-Capacitor; Analog-To-Digital Converter (ADC)

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APA (6th Edition):

Larsson, A. 1. (2012). Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148307

Chicago Manual of Style (16th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Doctoral Dissertation, Texas A&M University. Accessed October 28, 2020. http://hdl.handle.net/1969.1/148307.

MLA Handbook (7th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Web. 28 Oct 2020.

Vancouver:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1969.1/148307.

Council of Science Editors:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148307


Michigan Technological University

6. Guni, Shanta. A Comparative Study of Sigma Delta and Nonuniform Sampling A/D Converters.

Degree: MS, Department of Electrical and Computer Engineering, 2016, Michigan Technological University

  This thesis compares the performance of the Sigma Delta Analog to Digital Converter (ΣΔADC) and the Nonuniform Sampling Analog to Digital Converter (NUSADC) in… (more)

Subjects/Keywords: Sigma Delta; Analog-to-Digital Converter; Nonuniform Sampling; Time-to-Digital Converter; Signal Processing

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APA (6th Edition):

Guni, S. (2016). A Comparative Study of Sigma Delta and Nonuniform Sampling A/D Converters. (Masters Thesis). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etdr/164

Chicago Manual of Style (16th Edition):

Guni, Shanta. “A Comparative Study of Sigma Delta and Nonuniform Sampling A/D Converters.” 2016. Masters Thesis, Michigan Technological University. Accessed October 28, 2020. http://digitalcommons.mtu.edu/etdr/164.

MLA Handbook (7th Edition):

Guni, Shanta. “A Comparative Study of Sigma Delta and Nonuniform Sampling A/D Converters.” 2016. Web. 28 Oct 2020.

Vancouver:

Guni S. A Comparative Study of Sigma Delta and Nonuniform Sampling A/D Converters. [Internet] [Masters thesis]. Michigan Technological University; 2016. [cited 2020 Oct 28]. Available from: http://digitalcommons.mtu.edu/etdr/164.

Council of Science Editors:

Guni S. A Comparative Study of Sigma Delta and Nonuniform Sampling A/D Converters. [Masters Thesis]. Michigan Technological University; 2016. Available from: http://digitalcommons.mtu.edu/etdr/164


University of Texas – Austin

7. Jung, Woo Young. Time-based oversampled analog-to-digital converters in nano-scale integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable… (more)

Subjects/Keywords: Analog-to-digital converter; Delta-sigma modulation; Time-to-digital converter; Pulse-width modulation; Digital-to-time converter

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APA (6th Edition):

Jung, W. Y. (2014). Time-based oversampled analog-to-digital converters in nano-scale integrated circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/29195

Chicago Manual of Style (16th Edition):

Jung, Woo Young. “Time-based oversampled analog-to-digital converters in nano-scale integrated circuits.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed October 28, 2020. http://hdl.handle.net/2152/29195.

MLA Handbook (7th Edition):

Jung, Woo Young. “Time-based oversampled analog-to-digital converters in nano-scale integrated circuits.” 2014. Web. 28 Oct 2020.

Vancouver:

Jung WY. Time-based oversampled analog-to-digital converters in nano-scale integrated circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/2152/29195.

Council of Science Editors:

Jung WY. Time-based oversampled analog-to-digital converters in nano-scale integrated circuits. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/29195


Texas A&M University

8. Ankamah-Kusi, Sylvester. An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications.

Degree: MS, Electrical Engineering, 2016, Texas A&M University

 This thesis focuses on designing a low power Pipeline Analog to Digital Converter (ADC) for use in a Cognitive radio network. The Pipeline ADC architecture… (more)

Subjects/Keywords: Analog to Digital Converter; Pipeline; Kick-back; Residue; Distortion; Operational Amplifier; Multiplying Digital to Analog Converter (MDAC); Partial Positive Feedback Amplifier

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APA (6th Edition):

Ankamah-Kusi, S. (2016). An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/159069

Chicago Manual of Style (16th Edition):

Ankamah-Kusi, Sylvester. “An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications.” 2016. Masters Thesis, Texas A&M University. Accessed October 28, 2020. http://hdl.handle.net/1969.1/159069.

MLA Handbook (7th Edition):

Ankamah-Kusi, Sylvester. “An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications.” 2016. Web. 28 Oct 2020.

Vancouver:

Ankamah-Kusi S. An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1969.1/159069.

Council of Science Editors:

Ankamah-Kusi S. An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/159069


University of Texas – Austin

9. Sanyal, Arindam. Digital enhancement techniques for data converters in scaled CMOS technologies.

Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin

 This thesis presents digital enhancement techniques for data converters in advanced technology nodes. With technology scaling, traditional voltage-domain (VD) analog-to-digital converters (ADCs) face two major… (more)

Subjects/Keywords: Time-domain quantizer; Analog-to-digital converter; Digital-to-analog converter; Successive approximation register; Voltage controlled oscillator; Inter-symbol interference error

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APA (6th Edition):

Sanyal, A. (2015). Digital enhancement techniques for data converters in scaled CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32851

Chicago Manual of Style (16th Edition):

Sanyal, Arindam. “Digital enhancement techniques for data converters in scaled CMOS technologies.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed October 28, 2020. http://hdl.handle.net/2152/32851.

MLA Handbook (7th Edition):

Sanyal, Arindam. “Digital enhancement techniques for data converters in scaled CMOS technologies.” 2015. Web. 28 Oct 2020.

Vancouver:

Sanyal A. Digital enhancement techniques for data converters in scaled CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/2152/32851.

Council of Science Editors:

Sanyal A. Digital enhancement techniques for data converters in scaled CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32851


NSYSU

10. Ou, Shih-hao. Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With advances in integrated circuit (IC) processing technology, medical devices are becoming miniature, with low power consumption. Therefore, wearable and implantable applications become feasible, and… (more)

Subjects/Keywords: Common-mode; Differential-mode; Analog-to-digital converter; Voltage-to-time converter; Integrated circuit

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APA (6th Edition):

Ou, S. (2013). Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ou, Shih-hao. “Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion.” 2013. Thesis, NSYSU. Accessed October 28, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ou, Shih-hao. “Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion.” 2013. Web. 28 Oct 2020.

Vancouver:

Ou S. Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Oct 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ou S. Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oxford

11. Levski, Deyan. Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors.

Degree: PhD, 2018, University of Oxford

 This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few… (more)

Subjects/Keywords: Analog to Digital Converters; Engineering Science; Microelectronics; Analog Integrated Circuit Design; Photonics Devices; CMOS Image Sensors; Time to Digital Converter; Pixel; Column Parallel; Analog to Digital Converter

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APA (6th Edition):

Levski, D. (2018). Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors. (Doctoral Dissertation). University of Oxford. Retrieved from http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825

Chicago Manual of Style (16th Edition):

Levski, Deyan. “Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors.” 2018. Doctoral Dissertation, University of Oxford. Accessed October 28, 2020. http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825.

MLA Handbook (7th Edition):

Levski, Deyan. “Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors.” 2018. Web. 28 Oct 2020.

Vancouver:

Levski D. Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors. [Internet] [Doctoral dissertation]. University of Oxford; 2018. [cited 2020 Oct 28]. Available from: http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825.

Council of Science Editors:

Levski D. Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors. [Doctoral Dissertation]. University of Oxford; 2018. Available from: http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.757825


Oregon State University

12. Yu, Wenhuan. Design techniques for low power ADCs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the… (more)

Subjects/Keywords: data converter; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Yu, W. (2010). Design techniques for low power ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14316

Chicago Manual of Style (16th Edition):

Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/14316.

MLA Handbook (7th Edition):

Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Web. 28 Oct 2020.

Vancouver:

Yu W. Design techniques for low power ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/14316.

Council of Science Editors:

Yu W. Design techniques for low power ADCs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14316


Carnegie Mellon University

13. Liu, Shaolong. SAR ADCs Design and Calibration in Nano-scaled Technologies.

Degree: 2017, Carnegie Mellon University

 The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital(more)

Subjects/Keywords: ADC; analog-to-digital converter; Calibration; Integrated circuits; Low power; Offset

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APA (6th Edition):

Liu, S. (2017). SAR ADCs Design and Calibration in Nano-scaled Technologies. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/1073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Shaolong. “SAR ADCs Design and Calibration in Nano-scaled Technologies.” 2017. Thesis, Carnegie Mellon University. Accessed October 28, 2020. http://repository.cmu.edu/dissertations/1073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Shaolong. “SAR ADCs Design and Calibration in Nano-scaled Technologies.” 2017. Web. 28 Oct 2020.

Vancouver:

Liu S. SAR ADCs Design and Calibration in Nano-scaled Technologies. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2020 Oct 28]. Available from: http://repository.cmu.edu/dissertations/1073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu S. SAR ADCs Design and Calibration in Nano-scaled Technologies. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/1073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

14. Mirhaj, Seyed Arash. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.

Degree: Electrical Engineering, 2014, UCLA

 In recent years, Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) has received significant attention due to its well-known energy and hardware efficiency, which also benefits even… (more)

Subjects/Keywords: Electrical engineering; Analog to Digital Converter; Calibration; Piecewise Linear; SAR-ADC

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APA (6th Edition):

Mirhaj, S. A. (2014). Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Thesis, UCLA. Accessed October 28, 2020. http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mirhaj, Seyed Arash. “Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC.” 2014. Web. 28 Oct 2020.

Vancouver:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Oct 28]. Available from: http://www.escholarship.org/uc/item/9jx6c9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mirhaj SA. Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9jx6c9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Gao, Yang. An Energy Efficient Asynchronous Time-Domain Comparator.

Degree: MS, Electrical Engineering, 2013, Texas A&M University

 In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long… (more)

Subjects/Keywords: Analog-to-digital converter; asynchronous circuits; comparator; successive approximation

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APA (6th Edition):

Gao, Y. (2013). An Energy Efficient Asynchronous Time-Domain Comparator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149314

Chicago Manual of Style (16th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Masters Thesis, Texas A&M University. Accessed October 28, 2020. http://hdl.handle.net/1969.1/149314.

MLA Handbook (7th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Web. 28 Oct 2020.

Vancouver:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Internet] [Masters thesis]. Texas A&M University; 2013. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1969.1/149314.

Council of Science Editors:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Masters Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149314

16. Ito, Tomohiko. 無線通信システム用A/D変換器の高性能化に関する研究.

Degree: 博士(工学), 2013, Hosei University / 法政大学

 To realize next-generation high-throughput wireless communication systems, it is essential to develop analog-to-digital converters (ADC) with high conversion speed, high resolution, low power, and low… (more)

Subjects/Keywords: ADC; A/D; Analog-to-Digital Converter; Pipeline; Flash; Wireless; Receiver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ito, T. (2013). 無線通信システム用A/D変換器の高性能化に関する研究. (Thesis). Hosei University / 法政大学. Retrieved from http://hdl.handle.net/10114/9760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ito, Tomohiko. “無線通信システム用A/D変換器の高性能化に関する研究.” 2013. Thesis, Hosei University / 法政大学. Accessed October 28, 2020. http://hdl.handle.net/10114/9760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ito, Tomohiko. “無線通信システム用A/D変換器の高性能化に関する研究.” 2013. Web. 28 Oct 2020.

Vancouver:

Ito T. 無線通信システム用A/D変換器の高性能化に関する研究. [Internet] [Thesis]. Hosei University / 法政大学; 2013. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10114/9760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ito T. 無線通信システム用A/D変換器の高性能化に関する研究. [Thesis]. Hosei University / 法政大学; 2013. Available from: http://hdl.handle.net/10114/9760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

17. Scholfield, Kristin. Low power biosensor and decimator design.

Degree: MS(M.S.), Electrical and Computer Engineering, 2013, Colorado State University

 This paper examines the use of low power circuits applied to biosensors used to observe neurotransmission. The term "biosensors" in the broadest sense describes many… (more)

Subjects/Keywords: analog-to-digital converter; low power circuits; electrode; decimator; biosensor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Scholfield, K. (2013). Low power biosensor and decimator design. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/80308

Chicago Manual of Style (16th Edition):

Scholfield, Kristin. “Low power biosensor and decimator design.” 2013. Masters Thesis, Colorado State University. Accessed October 28, 2020. http://hdl.handle.net/10217/80308.

MLA Handbook (7th Edition):

Scholfield, Kristin. “Low power biosensor and decimator design.” 2013. Web. 28 Oct 2020.

Vancouver:

Scholfield K. Low power biosensor and decimator design. [Internet] [Masters thesis]. Colorado State University; 2013. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10217/80308.

Council of Science Editors:

Scholfield K. Low power biosensor and decimator design. [Masters Thesis]. Colorado State University; 2013. Available from: http://hdl.handle.net/10217/80308

18. Lindeberg, Johan. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); Cyclic; Algorithmic; Incremental; Capacitor mismatch; Compensation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lindeberg, J. (2014). Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lindeberg, Johan. “Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.” 2014. Thesis, Linköping UniversityLinköping University. Accessed October 28, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lindeberg, Johan. “Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.” 2014. Web. 28 Oct 2020.

Vancouver:

Lindeberg J. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2020 Oct 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lindeberg J. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Majidi, Rabeeh. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.

Degree: PhD, 2015, Worcester Polytechnic Institute

 With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve… (more)

Subjects/Keywords: Analog to Digital Converter ADC SAR Flash Frequenc

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Majidi, R. (2015). DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. (Doctoral Dissertation). Worcester Polytechnic Institute. Retrieved from etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275

Chicago Manual of Style (16th Edition):

Majidi, Rabeeh. “DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.” 2015. Doctoral Dissertation, Worcester Polytechnic Institute. Accessed October 28, 2020. etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275.

MLA Handbook (7th Edition):

Majidi, Rabeeh. “DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.” 2015. Web. 28 Oct 2020.

Vancouver:

Majidi R. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. [Internet] [Doctoral dissertation]. Worcester Polytechnic Institute; 2015. [cited 2020 Oct 28]. Available from: etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275.

Council of Science Editors:

Majidi R. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. [Doctoral Dissertation]. Worcester Polytechnic Institute; 2015. Available from: etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275

20. -1877-2730. MIMO communications with low resolution ADCs.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 The wide bandwidths and large antenna arrays in future communication systems impose big challenges for the hardware design of the receiver, which has to efficiently… (more)

Subjects/Keywords: MIMO; Low resolution analog-to-digital converter; Millimeter wave communication

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APA (6th Edition):

-1877-2730. (2018). MIMO communications with low resolution ADCs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63363

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-1877-2730. “MIMO communications with low resolution ADCs.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed October 28, 2020. http://hdl.handle.net/2152/63363.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-1877-2730. “MIMO communications with low resolution ADCs.” 2018. Web. 28 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-1877-2730. MIMO communications with low resolution ADCs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/2152/63363.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-1877-2730. MIMO communications with low resolution ADCs. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63363

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Universidade do Rio Grande do Sul

21. Mello, Israel Sperotto de. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.

Degree: 2015, Universidade do Rio Grande do Sul

 Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de… (more)

Subjects/Keywords: Microeletrônica; CMOS analog design; Circuitos digitais; Low voltage design; Digital to analog converter; Mismatch

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mello, I. S. d. (2015). All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/169086

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mello, Israel Sperotto de. “All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed October 28, 2020. http://hdl.handle.net/10183/169086.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mello, Israel Sperotto de. “All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.” 2015. Web. 28 Oct 2020.

Vancouver:

Mello ISd. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10183/169086.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mello ISd. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/169086

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

22. Fredenburg, Jeffrey Alan. Noise-Shaping SAR ADCs.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping… (more)

Subjects/Keywords: Analog-to-Digital Converter; Noise-shaping SAR; Successive-approximation ADC; Analog Circuits; Electrical Engineering; Engineering

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APA (6th Edition):

Fredenburg, J. A. (2015). Noise-Shaping SAR ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113647

Chicago Manual of Style (16th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Doctoral Dissertation, University of Michigan. Accessed October 28, 2020. http://hdl.handle.net/2027.42/113647.

MLA Handbook (7th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Web. 28 Oct 2020.

Vancouver:

Fredenburg JA. Noise-Shaping SAR ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/2027.42/113647.

Council of Science Editors:

Fredenburg JA. Noise-Shaping SAR ADCs. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113647


University of Waterloo

23. Bray, Adam. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.

Degree: 2013, University of Waterloo

 Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and… (more)

Subjects/Keywords: ADC; Analog to Digital Converter; Converters; Jitter; Timing Skew; Interleaved; TI-ADC; Time Interleaved; Analog

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bray, A. (2013). A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Thesis, University of Waterloo. Accessed October 28, 2020. http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Web. 28 Oct 2020.

Vancouver:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Younis, Choudhry Jabbar. Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

  Modern communication systems require higher data rates which have increased thedemand for high speed transceivers. For a system to work efficiently, all blocks ofthat… (more)

Subjects/Keywords: Analog front end; data rates; Analog to digital converter; track and hold; bootstrap; averaging; interpolation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Younis, C. J. (2012). Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Younis, Choudhry Jabbar. “Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers.” 2012. Thesis, Linköping UniversityLinköping University. Accessed October 28, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Younis, Choudhry Jabbar. “Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers.” 2012. Web. 28 Oct 2020.

Vancouver:

Younis CJ. Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2020 Oct 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Younis CJ. Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

25. Harish, C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.

Degree: MSc Engg, Faculty of Engineering, 2013, Indian Institute of Science

 This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); CMOS Technologies; Analog to Digital Signal Processing; Sigma Delta ADC; Wireless Applications; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harish, C. (2013). Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2049

Chicago Manual of Style (16th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2013. Masters Thesis, Indian Institute of Science. Accessed October 28, 2020. http://etd.iisc.ac.in/handle/2005/2049.

MLA Handbook (7th Edition):

Harish, C. “Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications.” 2013. Web. 28 Oct 2020.

Vancouver:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Internet] [Masters thesis]. Indian Institute of Science; 2013. [cited 2020 Oct 28]. Available from: http://etd.iisc.ac.in/handle/2005/2049.

Council of Science Editors:

Harish C. Design & Implementation Of Low Power Sigma Delta ADCs For Wide Band Applications. [Masters Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ac.in/handle/2005/2049


Linköping University

26. Rajendran, Dinesh Babu. Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology.

Degree: Electronics System, 2011, Linköping University

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the… (more)

Subjects/Keywords: Pipelined Analog-to-Digital Converter; Sample and Hold Amplifier; Comparator; Current-Steering Digital-to-Analog Converter; Binary to Thermometer Decoder; TECHNOLOGY; TEKNIKVETENSKAP

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APA (6th Edition):

Rajendran, D. B. (2011). Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajendran, Dinesh Babu. “Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology.” 2011. Thesis, Linköping University. Accessed October 28, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajendran, Dinesh Babu. “Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology.” 2011. Web. 28 Oct 2020.

Vancouver:

Rajendran DB. Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology. [Internet] [Thesis]. Linköping University; 2011. [cited 2020 Oct 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajendran DB. Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

27. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: PhD, Faculty of Engineering, 2017, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vasudevamurthy, R. (2017). Time-based All-Digital Technique for Analog Built-in Self Test. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2841

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2017. Doctoral Dissertation, Indian Institute of Science. Accessed October 28, 2020. http://etd.iisc.ac.in/handle/2005/2841.

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2017. Web. 28 Oct 2020.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2017. [cited 2020 Oct 28]. Available from: http://etd.iisc.ac.in/handle/2005/2841.

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Doctoral Dissertation]. Indian Institute of Science; 2017. Available from: http://etd.iisc.ac.in/handle/2005/2841


University of Illinois – Urbana-Champaign

28. Lin, Yingyan. Energy-efficient systems for information transfer and processing.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Machine learning (ML) systems are finding excellent utility in tackling the data deluge of the big data era thanks to the exponential increase in computing… (more)

Subjects/Keywords: Machine learning; Energy efficiency; Analog-to-digital converter; Bit-error-rate optimal analog-to-digital converter (ADC); Convolutional neural networks; Sparsity; Statistical error compensation; Near threshold computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, Y. (2017). Energy-efficient systems for information transfer and processing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98139

Chicago Manual of Style (16th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 28, 2020. http://hdl.handle.net/2142/98139.

MLA Handbook (7th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Web. 28 Oct 2020.

Vancouver:

Lin Y. Energy-efficient systems for information transfer and processing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/2142/98139.

Council of Science Editors:

Lin Y. Energy-efficient systems for information transfer and processing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98139


Brno University of Technology

29. Koleček, Jan. Programovatelná umělá zátěž: Programmable load.

Degree: 2019, Brno University of Technology

 The diploma thesis deals with the design of a programmable load. As first, the research of available commercial devices was made in the theoretical part.… (more)

Subjects/Keywords: Programovatelná umělá zátěž; řízení přeběhu; analogově-digitální převodník; digitálně-analogový převodník; FPGA obvod; mikrokontrolér; Programmable load; slew rate controlling; analog to digital converter; digital to analog converter; FPGA; microcontroller

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Koleček, J. (2019). Programovatelná umělá zátěž: Programmable load. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/59823

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Koleček, Jan. “Programovatelná umělá zátěž: Programmable load.” 2019. Thesis, Brno University of Technology. Accessed October 28, 2020. http://hdl.handle.net/11012/59823.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Koleček, Jan. “Programovatelná umělá zátěž: Programmable load.” 2019. Web. 28 Oct 2020.

Vancouver:

Koleček J. Programovatelná umělá zátěž: Programmable load. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/11012/59823.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Koleček J. Programovatelná umělá zátěž: Programmable load. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/59823

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Lo, Ching-Wen. High Speed SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In this thesis, the circuits are designing with TSMC 90nm CMOS process and 1.2V of supply voltage. The speed and resolution of ADC are 8-bit… (more)

Subjects/Keywords: Bootstrapped switch; Dynamic Comparator; Successive Approximation; Low power; Analog-to-Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, C. (2014). High Speed SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Thesis, NSYSU. Accessed October 28, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Web. 28 Oct 2020.

Vancouver:

Lo C. High Speed SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Oct 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo C. High Speed SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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