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You searched for subject:(Altera). Showing records 1 – 28 of 28 total matches.

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Penn State University

1. Nandakumar, Vishnu Vardhan. DESIGN OF A DATALOGGER, SHOTBOX AND PHASE LOCKED LOOP FREQUENCY SYNTHESIZER USED IN SEISMIC STUDY AND 3D IMAGING OF ANTARCTIC ICE SHEETS .

Degree: 2008, Penn State University

 With growing concern for global warming and climate change, it is of most importance to extend current research and studies towards the factors that contribute… (more)

Subjects/Keywords: electrical; propeller; altera

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APA (6th Edition):

Nandakumar, V. V. (2008). DESIGN OF A DATALOGGER, SHOTBOX AND PHASE LOCKED LOOP FREQUENCY SYNTHESIZER USED IN SEISMIC STUDY AND 3D IMAGING OF ANTARCTIC ICE SHEETS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/8919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nandakumar, Vishnu Vardhan. “DESIGN OF A DATALOGGER, SHOTBOX AND PHASE LOCKED LOOP FREQUENCY SYNTHESIZER USED IN SEISMIC STUDY AND 3D IMAGING OF ANTARCTIC ICE SHEETS .” 2008. Thesis, Penn State University. Accessed January 16, 2021. https://submit-etda.libraries.psu.edu/catalog/8919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nandakumar, Vishnu Vardhan. “DESIGN OF A DATALOGGER, SHOTBOX AND PHASE LOCKED LOOP FREQUENCY SYNTHESIZER USED IN SEISMIC STUDY AND 3D IMAGING OF ANTARCTIC ICE SHEETS .” 2008. Web. 16 Jan 2021.

Vancouver:

Nandakumar VV. DESIGN OF A DATALOGGER, SHOTBOX AND PHASE LOCKED LOOP FREQUENCY SYNTHESIZER USED IN SEISMIC STUDY AND 3D IMAGING OF ANTARCTIC ICE SHEETS . [Internet] [Thesis]. Penn State University; 2008. [cited 2021 Jan 16]. Available from: https://submit-etda.libraries.psu.edu/catalog/8919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nandakumar VV. DESIGN OF A DATALOGGER, SHOTBOX AND PHASE LOCKED LOOP FREQUENCY SYNTHESIZER USED IN SEISMIC STUDY AND 3D IMAGING OF ANTARCTIC ICE SHEETS . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/8919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

2. Shao, Jingnan. Characterization of FPGA-based Arbiter Physical Unclonable Functions.

Degree: Electrical Engineering and Computer Science (EECS), 2019, KTH

The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many… (more)

Subjects/Keywords: Arbiter PUF; FPGA; Altera; Verilog HDL; Arbiter PUF; FPGA; Altera; Verilog HDL; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik

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APA (6th Edition):

Shao, J. (2019). Characterization of FPGA-based Arbiter Physical Unclonable Functions. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-269549

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shao, Jingnan. “Characterization of FPGA-based Arbiter Physical Unclonable Functions.” 2019. Thesis, KTH. Accessed January 16, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-269549.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shao, Jingnan. “Characterization of FPGA-based Arbiter Physical Unclonable Functions.” 2019. Web. 16 Jan 2021.

Vancouver:

Shao J. Characterization of FPGA-based Arbiter Physical Unclonable Functions. [Internet] [Thesis]. KTH; 2019. [cited 2021 Jan 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-269549.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shao J. Characterization of FPGA-based Arbiter Physical Unclonable Functions. [Thesis]. KTH; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-269549

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

3. Svoboda, Stanislav. Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration.

Degree: 2019, Brno University of Technology

 This bachelor’s project deals with solutions of laboratory kit for teaching of work with CPLD curcuits which are made by company ALTERA. It is also… (more)

Subjects/Keywords: Přípravek pro výuku; ALTERA; CPLD; EPM7064; napájecí zdroj; JTAG.; Laboratory kit; ALTERA; CPLD; EPM7064; power supply unit; JTAG.

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APA (6th Edition):

Svoboda, S. (2019). Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/14121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Svoboda, Stanislav. “Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration.” 2019. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/14121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Svoboda, Stanislav. “Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration.” 2019. Web. 16 Jan 2021.

Vancouver:

Svoboda S. Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/14121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Svoboda S. Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/14121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

4. Gajdošík, Petr. Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices.

Degree: 2019, Brno University of Technology

 In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The… (more)

Subjects/Keywords: Laboratorní přípravek; CPLD; Altera; JTAG; VHDL; QUARTUS II.; Laboratory kit; CPLD; Altera; JTAG; VHDL; QUARTUS II.

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APA (6th Edition):

Gajdošík, P. (2019). Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/11375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gajdošík, Petr. “Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices.” 2019. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/11375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gajdošík, Petr. “Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices.” 2019. Web. 16 Jan 2021.

Vancouver:

Gajdošík P. Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/11375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gajdošík P. Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/11375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

5. Kremel, Bruno. Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips.

Degree: 2019, Brno University of Technology

 This work reviews the development frameworks available for the Altera System-On-Chip solutions. These solutions are then compared to solutions available on the Xilinx platform. The… (more)

Subjects/Keywords: SoC; FPGA; Altera; Cyclone V SoC; Zynq; RSoC; SoC; FPGA; Altera; Cyclone V SoC; Zynq; RSoC

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APA (6th Edition):

Kremel, B. (2019). Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/64072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kremel, Bruno. “Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips.” 2019. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/64072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kremel, Bruno. “Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips.” 2019. Web. 16 Jan 2021.

Vancouver:

Kremel B. Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/64072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kremel B. Framework for Reconfigurable Systems on the Altera Chips: Framework for Reconfigurable Systems on the Altera Chips. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/64072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Wang, Li-chieh. System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In recent years, accelerating compute-intensive applications by utilizing FPGA computing resources based on OpenCL interface has received a lot of attention. This scheme cannot only… (more)

Subjects/Keywords: Altera FPGA; convolutional neural network; HOG; CNN; human detection; OpenCL

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APA (6th Edition):

Wang, L. (2017). System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Li-chieh. “System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework.” 2017. Thesis, NSYSU. Accessed January 16, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Li-chieh. “System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework.” 2017. Web. 16 Jan 2021.

Vancouver:

Wang L. System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Jan 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang L. System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

7. Hajdú, Gábor. Ébresztőóra megvalósítása hardver leíró nyelv segítségével .

Degree: DE – Informatikai Kar, University of Debrecen

 Dolgozatomat úgy építettem fel, hogy szemléltethessem, hogyan járok el, milyen lépésekkel valósítok meg egy programot. A dolgozatomban elkészített program egy közismert funkciót valósít meg, az… (more)

Subjects/Keywords: FPGA; Verilog; Altera DE2

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APA (6th Edition):

Hajdú, G. (n.d.). Ébresztőóra megvalósítása hardver leíró nyelv segítségével . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/203065

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hajdú, Gábor. “Ébresztőóra megvalósítása hardver leíró nyelv segítségével .” Thesis, University of Debrecen. Accessed January 16, 2021. http://hdl.handle.net/2437/203065.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hajdú, Gábor. “Ébresztőóra megvalósítása hardver leíró nyelv segítségével .” Web. 16 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Hajdú G. Ébresztőóra megvalósítása hardver leíró nyelv segítségével . [Internet] [Thesis]. University of Debrecen; [cited 2021 Jan 16]. Available from: http://hdl.handle.net/2437/203065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Hajdú G. Ébresztőóra megvalósítása hardver leíró nyelv segítségével . [Thesis]. University of Debrecen; Available from: http://hdl.handle.net/2437/203065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

8. Gustavsson, Anders. Konstruktion av radiokontrollerad klocka.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

  Uppgiften var att ta emot och avkoda en radiosignal för tidsangivelse, DCF77. Avkodaren implementerades i en FPGA-krets från ALTERA. Utvecklingen genomfördes i Quartus II-miljön… (more)

Subjects/Keywords: VHDL; Mjuk processor; Altera Nios; Quartus II; DCF77

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APA (6th Edition):

Gustavsson, A. (2012). Konstruktion av radiokontrollerad klocka. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79253

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gustavsson, Anders. “Konstruktion av radiokontrollerad klocka.” 2012. Thesis, Linköping UniversityLinköping University. Accessed January 16, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79253.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gustavsson, Anders. “Konstruktion av radiokontrollerad klocka.” 2012. Web. 16 Jan 2021.

Vancouver:

Gustavsson A. Konstruktion av radiokontrollerad klocka. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2021 Jan 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79253.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gustavsson A. Konstruktion av radiokontrollerad klocka. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79253

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Tampereen ammattikorkeakoulu

9. Kivelä, Anssi. Digitaalipiirisuunnittelu Altera Quartus II 5.0 -ohjelmistolla.

Degree: 2010, Tampereen ammattikorkeakoulu

Subjects/Keywords: Altera-ohjelmisto; AHDL; laitteiston kuvauskieli

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APA (6th Edition):

Kivelä, A. (2010). Digitaalipiirisuunnittelu Altera Quartus II 5.0 -ohjelmistolla. (Thesis). Tampereen ammattikorkeakoulu. Retrieved from http://www.theseus.fi/handle/10024/10269

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kivelä, Anssi. “Digitaalipiirisuunnittelu Altera Quartus II 5.0 -ohjelmistolla.” 2010. Thesis, Tampereen ammattikorkeakoulu. Accessed January 16, 2021. http://www.theseus.fi/handle/10024/10269.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kivelä, Anssi. “Digitaalipiirisuunnittelu Altera Quartus II 5.0 -ohjelmistolla.” 2010. Web. 16 Jan 2021.

Vancouver:

Kivelä A. Digitaalipiirisuunnittelu Altera Quartus II 5.0 -ohjelmistolla. [Internet] [Thesis]. Tampereen ammattikorkeakoulu; 2010. [cited 2021 Jan 16]. Available from: http://www.theseus.fi/handle/10024/10269.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kivelä A. Digitaalipiirisuunnittelu Altera Quartus II 5.0 -ohjelmistolla. [Thesis]. Tampereen ammattikorkeakoulu; 2010. Available from: http://www.theseus.fi/handle/10024/10269

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

10. Macko, Peter. Implementace 10 GbE technologie použitím zařízení s FPGA modulem: IMPLEMENTATION OF 10GbE TECHNOLOGY USING DEVICE WITH FPGA MODULE.

Degree: 2019, Brno University of Technology

 The thesis is focused on implementation of the IEEE 802.3 10GBASE-R communication protocol into development kit Terasic DE5-NET with FPGA Altera Stratix V and on… (more)

Subjects/Keywords: 10GBASE-R PHY; 10Gb Ethernet; FPGA; IEEE 802.3; Altera Stratix V; SDR XGMII; DE5-NET Development Kit; Intel Altera IP; Mentor ModelSIM; 10GBASE-R PHY; 10Gb Ethernet; FPGA; IEEE 802.3; Altera Stratix V; SDR XGMII; DE5-NET Development Kit; Intel Altera IP; Mentor ModelSIM

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APA (6th Edition):

Macko, P. (2019). Implementace 10 GbE technologie použitím zařízení s FPGA modulem: IMPLEMENTATION OF 10GbE TECHNOLOGY USING DEVICE WITH FPGA MODULE. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/68091

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Macko, Peter. “Implementace 10 GbE technologie použitím zařízení s FPGA modulem: IMPLEMENTATION OF 10GbE TECHNOLOGY USING DEVICE WITH FPGA MODULE.” 2019. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/68091.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Macko, Peter. “Implementace 10 GbE technologie použitím zařízení s FPGA modulem: IMPLEMENTATION OF 10GbE TECHNOLOGY USING DEVICE WITH FPGA MODULE.” 2019. Web. 16 Jan 2021.

Vancouver:

Macko P. Implementace 10 GbE technologie použitím zařízení s FPGA modulem: IMPLEMENTATION OF 10GbE TECHNOLOGY USING DEVICE WITH FPGA MODULE. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/68091.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Macko P. Implementace 10 GbE technologie použitím zařízení s FPGA modulem: IMPLEMENTATION OF 10GbE TECHNOLOGY USING DEVICE WITH FPGA MODULE. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/68091

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

11. Xin, Xin. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA.

Degree: MS, Electrical Engineering, 2013, Virginia Tech

 There is a belief that radio frequencies  are running out. However, according to a report from the Federal Communications Commission (FCC) in 2002, a different… (more)

Subjects/Keywords: Multicarrier Communication; FMT; Overlay; Cognitive Radio; Altera FPGA

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APA (6th Edition):

Xin, X. (2013). A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23193

Chicago Manual of Style (16th Edition):

Xin, Xin. “A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA.” 2013. Masters Thesis, Virginia Tech. Accessed January 16, 2021. http://hdl.handle.net/10919/23193.

MLA Handbook (7th Edition):

Xin, Xin. “A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA.” 2013. Web. 16 Jan 2021.

Vancouver:

Xin X. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10919/23193.

Council of Science Editors:

Xin X. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23193

12. Daniel Soares e Marques. Sistema Misto Reconfigurável Aplicado à Interface PCI para Otimização do Algoritmo Non-local Means.

Degree: 2012, Universidade Federal da Paraíba

A área de processamento de imagens digitais está evoluindo continuamente e, embora as áreas de aplicações sejam diversas, os problemas encontrados comumente convergem para os… (more)

Subjects/Keywords: Non-local Means; NLM; Processamento Digital de Imagens; Computação Reconfigurável; PCI; FPGA; ALTERA; SISTEMAS DE COMPUTACAO; Non-local Means; NLM; Digital Image Processing; Reconfigurable Computing; PCI; FPGA; ALTERA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marques, D. S. e. (2012). Sistema Misto Reconfigurável Aplicado à Interface PCI para Otimização do Algoritmo Non-local Means. (Thesis). Universidade Federal da Paraíba. Retrieved from http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=2688

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Marques, Daniel Soares e. “Sistema Misto Reconfigurável Aplicado à Interface PCI para Otimização do Algoritmo Non-local Means.” 2012. Thesis, Universidade Federal da Paraíba. Accessed January 16, 2021. http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=2688.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Marques, Daniel Soares e. “Sistema Misto Reconfigurável Aplicado à Interface PCI para Otimização do Algoritmo Non-local Means.” 2012. Web. 16 Jan 2021.

Vancouver:

Marques DSe. Sistema Misto Reconfigurável Aplicado à Interface PCI para Otimização do Algoritmo Non-local Means. [Internet] [Thesis]. Universidade Federal da Paraíba; 2012. [cited 2021 Jan 16]. Available from: http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=2688.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Marques DSe. Sistema Misto Reconfigurável Aplicado à Interface PCI para Otimização do Algoritmo Non-local Means. [Thesis]. Universidade Federal da Paraíba; 2012. Available from: http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=2688

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

13. Trhoň, Adam. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.

Degree: 2020, Brno University of Technology

 This thesis describes a conceptual design of touchless fingerprint sensor and design, implementation and testing of its firmware, which is a composition of hardware implemented… (more)

Subjects/Keywords: biometrie; jazyk C; VHDL; Altera; hardware-software codesign; vícekamerový snímač otisku prstu; biometrics; C programming language; VHDL; Altera; hardware-software codesign; multi-camera fingerprint scanner

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Trhoň, A. (2020). Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/189623

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trhoň, Adam. “Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.” 2020. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/189623.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trhoň, Adam. “Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.” 2020. Web. 16 Jan 2021.

Vancouver:

Trhoň A. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/189623.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trhoň A. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/189623

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

14. Trhoň, Adam. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.

Degree: 2020, Brno University of Technology

 This thesis describes a conceptual design of touchless fingerprint sensor and design, implementation and testing of its firmware, which is a composition of hardware implemented… (more)

Subjects/Keywords: biometrie; jazyk C; VHDL; Altera; hardware-software codesign; vícekamerový snímač otisku prstu; biometrics; C programming language; VHDL; Altera; hardware-software codesign; multi-camera fingerprint scanner

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Trhoň, A. (2020). Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/188805

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trhoň, Adam. “Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.” 2020. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/188805.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trhoň, Adam. “Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.” 2020. Web. 16 Jan 2021.

Vancouver:

Trhoň A. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/188805.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trhoň A. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/188805

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

15. Bárta, Jakub. Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA.

Degree: 2019, Brno University of Technology

 At the begining of this thesis radar theory and classification of radar systems is explained. Next part introduces antenna arrays with it’s parameters and possibilities.… (more)

Subjects/Keywords: Radar; PSR; anténní řada; vyzařovací charakteristika; monopulz; tvarování svazku; FPGA; Altera; Cyclone V; Radar; PSR; antena array; antena pattern; monopulse; beamforming; FPGA; Altera; Cyclone V

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bárta, J. (2019). Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/177762

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bárta, Jakub. “Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA.” 2019. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/177762.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bárta, Jakub. “Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA.” 2019. Web. 16 Jan 2021.

Vancouver:

Bárta J. Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/177762.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bárta J. Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/177762

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

16. Trhoň, Adam. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.

Degree: 2020, Brno University of Technology

 This thesis describes a conceptual design of touchless fingerprint sensor and design, implementation and testing of its firmware, which is a composition of hardware implemented… (more)

Subjects/Keywords: biometrie; jazyk C; VHDL; Altera; hardware-software codesign; vícekamerový snímač otisku prstu; biometrics; C programming language; VHDL; Altera; hardware-software codesign; multi-camera fingerprint scanner

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Trhoň, A. (2020). Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/52244

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trhoň, Adam. “Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.” 2020. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/52244.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trhoň, Adam. “Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger.” 2020. Web. 16 Jan 2021.

Vancouver:

Trhoň A. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/52244.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trhoň A. Vícekamerový snímač biometrických vlastností lidského prstu: Multi-Camera Scanner of Biometric Features of Human Finger. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/52244

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Missouri University of Science and Technology

17. Chandra, Sandeep K. R. Characterization of noise on PDN and electromagnetic shielding.

Degree: M.S. in Electrical Engineering, Electrical Engineering, Missouri University of Science and Technology

 "Modern FPGA and microprocessor have complex logic inside them, which draw current from the Power Distribution Network (PDN). This current drawn from the PDN creates… (more)

Subjects/Keywords: Altera Stratix; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandra, S. K. R. (n.d.). Characterization of noise on PDN and electromagnetic shielding. (Masters Thesis). Missouri University of Science and Technology. Retrieved from https://scholarsmine.mst.edu/masters_theses/6886

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Chicago Manual of Style (16th Edition):

Chandra, Sandeep K R. “Characterization of noise on PDN and electromagnetic shielding.” Masters Thesis, Missouri University of Science and Technology. Accessed January 16, 2021. https://scholarsmine.mst.edu/masters_theses/6886.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

MLA Handbook (7th Edition):

Chandra, Sandeep K R. “Characterization of noise on PDN and electromagnetic shielding.” Web. 16 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Chandra SKR. Characterization of noise on PDN and electromagnetic shielding. [Internet] [Masters thesis]. Missouri University of Science and Technology; [cited 2021 Jan 16]. Available from: https://scholarsmine.mst.edu/masters_theses/6886.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Council of Science Editors:

Chandra SKR. Characterization of noise on PDN and electromagnetic shielding. [Masters Thesis]. Missouri University of Science and Technology; Available from: https://scholarsmine.mst.edu/masters_theses/6886

Note: this citation may be lacking information needed for this citation format:
No year of publication.

18. Sousa, António João dos Santos. Multiprocessor platform using LEON3 processor.

Degree: 2009, Instituto Politécnico do Porto

The recent advances in embedded systems world, lead us to more complex systems with application specific blocks (IP cores), the System on Chip (SoC) devices.… (more)

Subjects/Keywords: Multiprocessor; Multicore; LEON3; IP core; SPARC V8; FPGA; Altera; SoC; MSoC; Linux; Operating System; Multicore; Sistema Operativo; Multiprocessador

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APA (6th Edition):

Sousa, A. J. d. S. (2009). Multiprocessor platform using LEON3 processor. (Thesis). Instituto Politécnico do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sousa, António João dos Santos. “Multiprocessor platform using LEON3 processor.” 2009. Thesis, Instituto Politécnico do Porto. Accessed January 16, 2021. http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sousa, António João dos Santos. “Multiprocessor platform using LEON3 processor.” 2009. Web. 16 Jan 2021.

Vancouver:

Sousa AJdS. Multiprocessor platform using LEON3 processor. [Internet] [Thesis]. Instituto Politécnico do Porto; 2009. [cited 2021 Jan 16]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sousa AJdS. Multiprocessor platform using LEON3 processor. [Thesis]. Instituto Politécnico do Porto; 2009. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

19. Bajramovic, Jasko. FPGA Implementation of an Interpolator for PWM applications.

Degree: Electrical Engineering, 2007, Linköping University

  In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width… (more)

Subjects/Keywords: interpolator; half band FIR filter; MCM; Altera; Electronics; Elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bajramovic, J. (2007). FPGA Implementation of an Interpolator for PWM applications. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bajramovic, Jasko. “FPGA Implementation of an Interpolator for PWM applications.” 2007. Thesis, Linköping University. Accessed January 16, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bajramovic, Jasko. “FPGA Implementation of an Interpolator for PWM applications.” 2007. Web. 16 Jan 2021.

Vancouver:

Bajramovic J. FPGA Implementation of an Interpolator for PWM applications. [Internet] [Thesis]. Linköping University; 2007. [cited 2021 Jan 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bajramovic J. FPGA Implementation of an Interpolator for PWM applications. [Thesis]. Linköping University; 2007. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

20. Hantoosh, Majid. A Boolean Cube to VHDL converter and its application to parallel CRC generation.

Degree: Information and Communication Technology (ICT), 2011, KTH

  The primary outcome of this thesis is found in three contributions. First, we developed an automatic converter from the cube representation of incompletely specified… (more)

Subjects/Keywords: ASIC; LFSR; NLFSR; Espresso; Parallel CRC; TCL; VHDL; FPGA; design compiler; ModelSim; Xilinx; Altera; TECHNOLOGY; TEKNIKVETENSKAP

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hantoosh, M. (2011). A Boolean Cube to VHDL converter and its application to parallel CRC generation. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48493

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hantoosh, Majid. “A Boolean Cube to VHDL converter and its application to parallel CRC generation.” 2011. Thesis, KTH. Accessed January 16, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48493.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hantoosh, Majid. “A Boolean Cube to VHDL converter and its application to parallel CRC generation.” 2011. Web. 16 Jan 2021.

Vancouver:

Hantoosh M. A Boolean Cube to VHDL converter and its application to parallel CRC generation. [Internet] [Thesis]. KTH; 2011. [cited 2021 Jan 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48493.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hantoosh M. A Boolean Cube to VHDL converter and its application to parallel CRC generation. [Thesis]. KTH; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48493

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

21. Sheth, Pranav Harishkumar. Implementation of stereo sound enhancement on FPGA.

Degree: MS, Electrical and Electronic Engineering, 2010, California State University – Sacramento

 The main objective of this project is to understand the concept of stereo sound enhancement techniques and implement a stereo sound enhancement algorithm on Altera(more)

Subjects/Keywords: Altera FPGA; Look up table design; Digital FIR filter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sheth, P. H. (2010). Implementation of stereo sound enhancement on FPGA. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/789

Chicago Manual of Style (16th Edition):

Sheth, Pranav Harishkumar. “Implementation of stereo sound enhancement on FPGA.” 2010. Masters Thesis, California State University – Sacramento. Accessed January 16, 2021. http://hdl.handle.net/10211.9/789.

MLA Handbook (7th Edition):

Sheth, Pranav Harishkumar. “Implementation of stereo sound enhancement on FPGA.” 2010. Web. 16 Jan 2021.

Vancouver:

Sheth PH. Implementation of stereo sound enhancement on FPGA. [Internet] [Masters thesis]. California State University – Sacramento; 2010. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10211.9/789.

Council of Science Editors:

Sheth PH. Implementation of stereo sound enhancement on FPGA. [Masters Thesis]. California State University – Sacramento; 2010. Available from: http://hdl.handle.net/10211.9/789


Brno University of Technology

22. Bajer, Jan. Vzorové úlohy pro hradlová pole: Samples of examples for configurable gate array.

Degree: 2020, Brno University of Technology

 This thesis introduces the issue of configurable gate arrays and their position with respect to microprocessor technology. The aim is to present work with gate… (more)

Subjects/Keywords: Hradlová pole; FPGA; Altera; Intel; Cyclone; VHDL; UART; PWM; stejnosměrný motor; PID regulátor; krokový motor; AD převodník; Configurable gate array; FPGA; Altera; Intel; Cyclone; VHDL; UART; PWM; DC motor; PID controller; stepper motor; AD converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bajer, J. (2020). Vzorové úlohy pro hradlová pole: Samples of examples for configurable gate array. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/193469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bajer, Jan. “Vzorové úlohy pro hradlová pole: Samples of examples for configurable gate array.” 2020. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/193469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bajer, Jan. “Vzorové úlohy pro hradlová pole: Samples of examples for configurable gate array.” 2020. Web. 16 Jan 2021.

Vancouver:

Bajer J. Vzorové úlohy pro hradlová pole: Samples of examples for configurable gate array. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/193469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bajer J. Vzorové úlohy pro hradlová pole: Samples of examples for configurable gate array. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/193469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

23. Bárta, Jakub. Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA.

Degree: 2019, Brno University of Technology

 This thesis deals with design and implementation of digital beamformer for 3D radar. The text of this thesis contains derivation of beamforming algorithm and detailed… (more)

Subjects/Keywords: 3D radar; fázovaná anténní řada; vyzařovací charakteristika; AESA; PESA; Butlerova matice; tvarování svazku; vychylování svazku; s-parametry; monopulzní detekce; FPGA; Altera; Cyclone V; SoC; 3D radar; phased antena array; antena pattern; AESA; PESA; Butler matrix; beamforming; beamsteerig; monopulse detection; s-parameters; FPGA; Altera; Cyclone V; SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bárta, J. (2019). Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/180536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bárta, Jakub. “Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA.” 2019. Thesis, Brno University of Technology. Accessed January 16, 2021. http://hdl.handle.net/11012/180536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bárta, Jakub. “Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA.” 2019. Web. 16 Jan 2021.

Vancouver:

Bárta J. Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11012/180536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bárta J. Implementace tvarování anténních příjmových svazků radaru v FPGA: Radar receiver beamforming implementation in FPGA. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/180536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Florida

24. Inamdar, Shahabuddin L. VHDL Coding Style Guidelines and Synthesis: A Comparative Approach.

Degree: 2004, University of South Florida

 With the transistor density on an integrated circuit doubling every 18 months, Moore’s law seems likely to hold for another decade at least. This exponential… (more)

Subjects/Keywords: Altera; Xilinx; Portability; FPGA; VHDL Subset; American Studies; Arts and Humanities

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Inamdar, S. L. (2004). VHDL Coding Style Guidelines and Synthesis: A Comparative Approach. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/1089

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Inamdar, Shahabuddin L. “VHDL Coding Style Guidelines and Synthesis: A Comparative Approach.” 2004. Thesis, University of South Florida. Accessed January 16, 2021. https://scholarcommons.usf.edu/etd/1089.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Inamdar, Shahabuddin L. “VHDL Coding Style Guidelines and Synthesis: A Comparative Approach.” 2004. Web. 16 Jan 2021.

Vancouver:

Inamdar SL. VHDL Coding Style Guidelines and Synthesis: A Comparative Approach. [Internet] [Thesis]. University of South Florida; 2004. [cited 2021 Jan 16]. Available from: https://scholarcommons.usf.edu/etd/1089.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Inamdar SL. VHDL Coding Style Guidelines and Synthesis: A Comparative Approach. [Thesis]. University of South Florida; 2004. Available from: https://scholarcommons.usf.edu/etd/1089

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Μεϊντάνης, Δημήτριος. Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems.

Degree: 2012, Technical University of Crete (TUC); Πολυτεχνείο Κρήτης

In the industrial market, designers have a significant incentive to get their products to market quickly: to maximize revenue and time-in-market. Every week that a… (more)

Subjects/Keywords: Κατανάλωση ενέργειας; Αναδιατασσόμενη λογική; Κρυπτογραφία; Αλγόριθμος του Πόλαρντ; Μετρήσεις; R.S.A.; General number field sieve; Field programmable gate array; Power consumption; Polard rho algorithm; XILINX; Altera; Power estimation

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APA (6th Edition):

Μεϊντάνης, . . (2012). Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems. (Thesis). Technical University of Crete (TUC); Πολυτεχνείο Κρήτης. Retrieved from http://hdl.handle.net/10442/hedi/27095

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Μεϊντάνης, Δημήτριος. “Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems.” 2012. Thesis, Technical University of Crete (TUC); Πολυτεχνείο Κρήτης. Accessed January 16, 2021. http://hdl.handle.net/10442/hedi/27095.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Μεϊντάνης, Δημήτριος. “Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems.” 2012. Web. 16 Jan 2021.

Vancouver:

Μεϊντάνης . Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems. [Internet] [Thesis]. Technical University of Crete (TUC); Πολυτεχνείο Κρήτης; 2012. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10442/hedi/27095.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Μεϊντάνης . Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems. [Thesis]. Technical University of Crete (TUC); Πολυτεχνείο Κρήτης; 2012. Available from: http://hdl.handle.net/10442/hedi/27095

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Swegert, Eric B. RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2013, University of Cincinnati

 Students with an interest in embedded systems come from a variety of backgrounds: EE, COMPE, CS, Telecommunications, etc. The students may be on-campus students or… (more)

Subjects/Keywords: Computer Engineering; RTOS; OS; Embedded System; Altera; Nios II; FPGA

…student practical experience. Altera provides a tool chain of easy to use tools that allows for… …The tutorials provided by Altera provide an adequate understanding of how to use the tools… …following along with the same Altera development board the tutorial was written for, it is… …sections. The Nios II processor, Altera tool chain and design flow, and Altera DE1 development… …peripherals, onchip memory, and interfaces to off-chip memory, all implemented on a single Altera… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Swegert, E. B. (2013). RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367934958

Chicago Manual of Style (16th Edition):

Swegert, Eric B. “RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students.” 2013. Masters Thesis, University of Cincinnati. Accessed January 16, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367934958.

MLA Handbook (7th Edition):

Swegert, Eric B. “RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students.” 2013. Web. 16 Jan 2021.

Vancouver:

Swegert EB. RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students. [Internet] [Masters thesis]. University of Cincinnati; 2013. [cited 2021 Jan 16]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367934958.

Council of Science Editors:

Swegert EB. RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students. [Masters Thesis]. University of Cincinnati; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367934958


Linköping University

27. Johansson, Jonas. Klass-D Förstärkare.

Degree: Electrical Engineering, 2007, Linköping University

  Syftet med högskoleavhandlingen var att konstruera en klass-D förstärkare för audio med en DDXi-2161 krets från Apogee. Förstärkaren har en digital stereoingång för I²S-format.… (more)

Subjects/Keywords: FPGA; DDXi-2161; Digital Förstäkare; Klass-D förstäkare; VHDL; Altera; Quartus II; Mentor Graphics; DDX®; Electrical engineering; Elektroteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Johansson, J. (2007). Klass-D Förstärkare. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Johansson, Jonas. “Klass-D Förstärkare.” 2007. Thesis, Linköping University. Accessed January 16, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Johansson, Jonas. “Klass-D Förstärkare.” 2007. Web. 16 Jan 2021.

Vancouver:

Johansson J. Klass-D Förstärkare. [Internet] [Thesis]. Linköping University; 2007. [cited 2021 Jan 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Johansson J. Klass-D Förstärkare. [Thesis]. Linköping University; 2007. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Jönköping University

28. Mahmood, Adnan. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP.

Degree: Computer and Electrical Engineering, 2009, Jönköping University

  Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core),… (more)

Subjects/Keywords: Network on Chip (NoC); System on Chip (SoC); Resource Network Interface (RNI); Altera FPGA; Nios II Core; On Chip Communication; Distributed Routing; Source Routing; Electrical engineering; Elektroteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mahmood, A. (2009). DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mahmood, Adnan. “DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP.” 2009. Thesis, Jönköping University. Accessed January 16, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mahmood, Adnan. “DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP.” 2009. Web. 16 Jan 2021.

Vancouver:

Mahmood A. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP. [Internet] [Thesis]. Jönköping University; 2009. [cited 2021 Jan 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mahmood A. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP. [Thesis]. Jönköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.