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You searched for subject:(All digital Phase locked Loops ADPLLs ). Showing records 1 – 30 of 31415 total matches.

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Vanderbilt University

1. Chen, Yanran. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals… (more)

Subjects/Keywords: Single-Event Upsets (SEU); All-digital Phase-locked Loops (ADPLLs); Single-Event Effects (SEE)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2017). Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;

Chicago Manual of Style (16th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed November 13, 2019. http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.

MLA Handbook (7th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Web. 13 Nov 2019.

Vancouver:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2019 Nov 13]. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.

Council of Science Editors:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;


Oregon State University

2. Yin, Wenjing. Design techniques for high-performance digital PLLs and CDRs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as… (more)

Subjects/Keywords: digital PLL; Phase-locked loops

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APA (6th Edition):

Yin, W. (2010). Design techniques for high-performance digital PLLs and CDRs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19407

Chicago Manual of Style (16th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Doctoral Dissertation, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/19407.

MLA Handbook (7th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Web. 13 Nov 2019.

Vancouver:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/19407.

Council of Science Editors:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19407


Oregon State University

3. Elshazly, Amr. Performance enhancement techniques for low power digital phase locked loops.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves… (more)

Subjects/Keywords: Phase locked loops; Phase-locked loops

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APA (6th Edition):

Elshazly, A. (2012). Performance enhancement techniques for low power digital phase locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/31116

Chicago Manual of Style (16th Edition):

Elshazly, Amr. “Performance enhancement techniques for low power digital phase locked loops.” 2012. Doctoral Dissertation, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/31116.

MLA Handbook (7th Edition):

Elshazly, Amr. “Performance enhancement techniques for low power digital phase locked loops.” 2012. Web. 13 Nov 2019.

Vancouver:

Elshazly A. Performance enhancement techniques for low power digital phase locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/31116.

Council of Science Editors:

Elshazly A. Performance enhancement techniques for low power digital phase locked loops. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/31116


Oregon State University

4. Arakali, Abhijith. Low-power techniques for supply-noise mitigation in phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Modern day digital systems employ frequency synthesizers to provide a common clock to the system. They are undergoing large scale integration due to which, mitigation… (more)

Subjects/Keywords: Phase-locked loops

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APA (6th Edition):

Arakali, A. (2010). Low-power techniques for supply-noise mitigation in phase-locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14281

Chicago Manual of Style (16th Edition):

Arakali, Abhijith. “Low-power techniques for supply-noise mitigation in phase-locked loops.” 2010. Doctoral Dissertation, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/14281.

MLA Handbook (7th Edition):

Arakali, Abhijith. “Low-power techniques for supply-noise mitigation in phase-locked loops.” 2010. Web. 13 Nov 2019.

Vancouver:

Arakali A. Low-power techniques for supply-noise mitigation in phase-locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/14281.

Council of Science Editors:

Arakali A. Low-power techniques for supply-noise mitigation in phase-locked loops. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14281


Montana State University

5. Ostrander, Charles Nicholas. Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit.

Degree: College of Engineering, 2009, Montana State University

 The Periodic Event Synchronization Unit aligns devices without the ability to be triggered by an external source. The primary function of the unit is to… (more)

Subjects/Keywords: Phase-locked loops.; Digital electronics.; Trigger circuits.; Sensor networks.

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APA (6th Edition):

Ostrander, C. N. (2009). Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1997

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ostrander, Charles Nicholas. “Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit.” 2009. Thesis, Montana State University. Accessed November 13, 2019. https://scholarworks.montana.edu/xmlui/handle/1/1997.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ostrander, Charles Nicholas. “Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit.” 2009. Web. 13 Nov 2019.

Vancouver:

Ostrander CN. Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit. [Internet] [Thesis]. Montana State University; 2009. [cited 2019 Nov 13]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1997.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ostrander CN. Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit. [Thesis]. Montana State University; 2009. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1997

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. Liu, Yubo. Design of all digital phase-locked loop in serial link communication.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 The speed of wireline and wireless communication systems has been increasing aggressively over the past decade. Multi-GHz clocks are in demand more than ever. In… (more)

Subjects/Keywords: phase-locked loop (PLL); serial link; all digital phase-locked loop (ADPLL); jitter

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APA (6th Edition):

Liu, Y. (2015). Design of all digital phase-locked loop in serial link communication. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed November 13, 2019. http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Web. 13 Nov 2019.

Vancouver:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Wei, Da. Clock synthesizer design with analog and digital phase locked loop.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 As process technology has aggressively scaled, the demand for fast, robust computing has grown tremendously. With the rise of large scale data centers to handhold… (more)

Subjects/Keywords: All Digital Phase-Locked Loop (PLL); Charge Pump Phase-Locked Loop (PLL); Clock Synthesizer; Phase Locked Loop

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APA (6th Edition):

Wei, D. (2014). Clock synthesizer design with analog and digital phase locked loop. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Da. “Clock synthesizer design with analog and digital phase locked loop.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed November 13, 2019. http://hdl.handle.net/2142/50472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Da. “Clock synthesizer design with analog and digital phase locked loop.” 2014. Web. 13 Nov 2019.

Vancouver:

Wei D. Clock synthesizer design with analog and digital phase locked loop. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/2142/50472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei D. Clock synthesizer design with analog and digital phase locked loop. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

8. Kratyuk, Volodymyr. Digital phase-locked loops for multi-GHz clock generation.

Degree: PhD, Electrical and Computer Engineering, 2007, Oregon State University

 A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise… (more)

Subjects/Keywords: digital phase-locked loop; Phase-locked loops

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APA (6th Edition):

Kratyuk, V. (2007). Digital phase-locked loops for multi-GHz clock generation. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/3804

Chicago Manual of Style (16th Edition):

Kratyuk, Volodymyr. “Digital phase-locked loops for multi-GHz clock generation.” 2007. Doctoral Dissertation, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/3804.

MLA Handbook (7th Edition):

Kratyuk, Volodymyr. “Digital phase-locked loops for multi-GHz clock generation.” 2007. Web. 13 Nov 2019.

Vancouver:

Kratyuk V. Digital phase-locked loops for multi-GHz clock generation. [Internet] [Doctoral dissertation]. Oregon State University; 2007. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/3804.

Council of Science Editors:

Kratyuk V. Digital phase-locked loops for multi-GHz clock generation. [Doctoral Dissertation]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/3804

9. Staszewski, Robert Bogdan. Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications.

Degree: 2016, University of Texas at Dallas

Traditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applications have almost exclusively employed the use of a charge-pump phase-locked loop (PLL), which… (more)

Subjects/Keywords: All-digital phase-locked loop; ADPLL; Time-to-digital converter (TDC); Digitally controlled oscillator (DCO)

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APA (6th Edition):

Staszewski, R. B. (2016). Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications. (Thesis). University of Texas at Dallas. Retrieved from http://hdl.handle.net/10197/8119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Staszewski, Robert Bogdan. “Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications.” 2016. Thesis, University of Texas at Dallas. Accessed November 13, 2019. http://hdl.handle.net/10197/8119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Staszewski, Robert Bogdan. “Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications.” 2016. Web. 13 Nov 2019.

Vancouver:

Staszewski RB. Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications. [Internet] [Thesis]. University of Texas at Dallas; 2016. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/10197/8119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Staszewski RB. Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications. [Thesis]. University of Texas at Dallas; 2016. Available from: http://hdl.handle.net/10197/8119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

10. Elkholy, Ahmed Mostafa Mohamed Attia. Digital enhancement techniques for fractional-N frequency synthesizers.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing… (more)

Subjects/Keywords: Phase-locked loops (PLLs); digital PLL; All-digital phase locked loop (ADPLL); fractional-N; Fractional divider, frequency synthesizer; Wide bandwidth; Bang-bang phase detector (BBPD); Digital-to-time converter (DTC); Least-mean square (LMS); Time-to-digtial converter (TDC); Time amplifier; Jitter; Digitally controlled oscillator (DCO); Frequency multiplier; Frequency tracking; Impulse sensitivity function (ISF); Injection locking; Multiplying injection-locked oscillator (MILO); Phase domain response (PDR); Phase noise; Pulse; Reference spur; Root mean square (rms) jitter; Sub-harmonic locking; Sub-sampling (SS)

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APA (6th Edition):

Elkholy, A. M. M. A. (2016). Digital enhancement techniques for fractional-N frequency synthesizers. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95573

Chicago Manual of Style (16th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed November 13, 2019. http://hdl.handle.net/2142/95573.

MLA Handbook (7th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Web. 13 Nov 2019.

Vancouver:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/2142/95573.

Council of Science Editors:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95573


Ryerson University

11. El-Hage, Mohamad. A New Phase-Locked Loop with Active Inductor Ring Oscillator.

Degree: 2004, Ryerson University

 Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO)… (more)

Subjects/Keywords: Phase-locked loops

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APA (6th Edition):

El-Hage, M. (2004). A New Phase-Locked Loop with Active Inductor Ring Oscillator. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A2455

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

El-Hage, Mohamad. “A New Phase-Locked Loop with Active Inductor Ring Oscillator.” 2004. Thesis, Ryerson University. Accessed November 13, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A2455.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

El-Hage, Mohamad. “A New Phase-Locked Loop with Active Inductor Ring Oscillator.” 2004. Web. 13 Nov 2019.

Vancouver:

El-Hage M. A New Phase-Locked Loop with Active Inductor Ring Oscillator. [Internet] [Thesis]. Ryerson University; 2004. [cited 2019 Nov 13]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2455.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

El-Hage M. A New Phase-Locked Loop with Active Inductor Ring Oscillator. [Thesis]. Ryerson University; 2004. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2455

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

12. Shum, Daniel K. Model and design of cmos phase-locked loop.

Degree: MS, Electrical and Computer Engineering, 1989, Oregon State University

 This thesis will examine the model and design technique of a self-contained analog CMOS Phase-Locked Loop. This system has an adaptable filter and demodulator for… (more)

Subjects/Keywords: Phase-locked loops

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APA (6th Edition):

Shum, D. K. (1989). Model and design of cmos phase-locked loop. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/38954

Chicago Manual of Style (16th Edition):

Shum, Daniel K. “Model and design of cmos phase-locked loop.” 1989. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/38954.

MLA Handbook (7th Edition):

Shum, Daniel K. “Model and design of cmos phase-locked loop.” 1989. Web. 13 Nov 2019.

Vancouver:

Shum DK. Model and design of cmos phase-locked loop. [Internet] [Masters thesis]. Oregon State University; 1989. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/38954.

Council of Science Editors:

Shum DK. Model and design of cmos phase-locked loop. [Masters Thesis]. Oregon State University; 1989. Available from: http://hdl.handle.net/1957/38954


University of Southern California

13. Aflatouni, Firooz. Electronically assisted relative and absolute phase control of semiconductor lasers.

Degree: PhD, Electrical Engineering, 2013, University of Southern California

 Electronically assisted precise phase control of the output of semiconductor lasers (SCLs) is explored in this thesis. Coherent power combining of multiple semiconductor lasers, phase(more)

Subjects/Keywords: laser; linewidth reduction; phase locked loops

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APA (6th Edition):

Aflatouni, F. (2013). Electronically assisted relative and absolute phase control of semiconductor lasers. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/675092/rec/2281

Chicago Manual of Style (16th Edition):

Aflatouni, Firooz. “Electronically assisted relative and absolute phase control of semiconductor lasers.” 2013. Doctoral Dissertation, University of Southern California. Accessed November 13, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/675092/rec/2281.

MLA Handbook (7th Edition):

Aflatouni, Firooz. “Electronically assisted relative and absolute phase control of semiconductor lasers.” 2013. Web. 13 Nov 2019.

Vancouver:

Aflatouni F. Electronically assisted relative and absolute phase control of semiconductor lasers. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2019 Nov 13]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/675092/rec/2281.

Council of Science Editors:

Aflatouni F. Electronically assisted relative and absolute phase control of semiconductor lasers. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/675092/rec/2281

14. Jung, Seokmin. Design of a low jitter digital PLL with low input frequency.

Degree: MS, iin Electrical and Computer Engineering, 2012, Oregon State University

 Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in… (more)

Subjects/Keywords: digital phase locked loop; Phase-locked loops  – Design and construction

…15 2.11 Digital phase accumulator… …16 2.12 Digital to phase converter in DPA… …critical example of such a support circuit is the phase-locked loop (PLL). PLL circuits… …emerged as an alternative to analog PLL. A digital loop filter is used in a DPLL with all… …signal. When phase is locked, the phase error is zero and control voltage remains stable, along… 

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APA (6th Edition):

Jung, S. (2012). Design of a low jitter digital PLL with low input frequency. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30105

Chicago Manual of Style (16th Edition):

Jung, Seokmin. “Design of a low jitter digital PLL with low input frequency.” 2012. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/30105.

MLA Handbook (7th Edition):

Jung, Seokmin. “Design of a low jitter digital PLL with low input frequency.” 2012. Web. 13 Nov 2019.

Vancouver:

Jung S. Design of a low jitter digital PLL with low input frequency. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/30105.

Council of Science Editors:

Jung S. Design of a low jitter digital PLL with low input frequency. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/30105


Oregon State University

15. Ok, Kerem. A stochastic time-to-digital converter for digital phase-locked loops.

Degree: MS, Electrical and Computer Engineering., 2005, Oregon State University

Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In… (more)

Subjects/Keywords: time-to-digital converter; Phase-locked loops.

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APA (6th Edition):

Ok, K. (2005). A stochastic time-to-digital converter for digital phase-locked loops. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/482

Chicago Manual of Style (16th Edition):

Ok, Kerem. “A stochastic time-to-digital converter for digital phase-locked loops.” 2005. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/482.

MLA Handbook (7th Edition):

Ok, Kerem. “A stochastic time-to-digital converter for digital phase-locked loops.” 2005. Web. 13 Nov 2019.

Vancouver:

Ok K. A stochastic time-to-digital converter for digital phase-locked loops. [Internet] [Masters thesis]. Oregon State University; 2005. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/482.

Council of Science Editors:

Ok K. A stochastic time-to-digital converter for digital phase-locked loops. [Masters Thesis]. Oregon State University; 2005. Available from: http://hdl.handle.net/1957/482


NSYSU

16. Juan, Sung-lin. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power; digitally controlled oscillator; successive approximation register; digital frequency detector; all digital phase-locked loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Juan, S. (2015). Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Thesis, NSYSU. Accessed November 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Web. 13 Nov 2019.

Vancouver:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Nov 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Xie, Shan-yang. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power schmitt trigger inverter; digitally controlled oscillator; all digital phase-locked loop; digital frequency detector; successive approximation register

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APA (6th Edition):

Xie, S. (2018). Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Thesis, NSYSU. Accessed November 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Web. 13 Nov 2019.

Vancouver:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Nov 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

18. Brownlee, Merrick. Low noise clocking for high speed serial links.

Degree: PhD, Electrical and Computer Engineering, 2006, Oregon State University

 As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore,… (more)

Subjects/Keywords: Phase Locked Loop; Phase-locked loops

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APA (6th Edition):

Brownlee, M. (2006). Low noise clocking for high speed serial links. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/3506

Chicago Manual of Style (16th Edition):

Brownlee, Merrick. “Low noise clocking for high speed serial links.” 2006. Doctoral Dissertation, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/3506.

MLA Handbook (7th Edition):

Brownlee, Merrick. “Low noise clocking for high speed serial links.” 2006. Web. 13 Nov 2019.

Vancouver:

Brownlee M. Low noise clocking for high speed serial links. [Internet] [Doctoral dissertation]. Oregon State University; 2006. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/3506.

Council of Science Editors:

Brownlee M. Low noise clocking for high speed serial links. [Doctoral Dissertation]. Oregon State University; 2006. Available from: http://hdl.handle.net/1957/3506


Oregon State University

19. Wu, Ting. Design techniques for PVT tolerant phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2007, Oregon State University

 The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to… (more)

Subjects/Keywords: phase-locked loop; Phase-locked loops

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APA (6th Edition):

Wu, T. (2007). Design techniques for PVT tolerant phase-locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/3866

Chicago Manual of Style (16th Edition):

Wu, Ting. “Design techniques for PVT tolerant phase-locked loops.” 2007. Doctoral Dissertation, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/3866.

MLA Handbook (7th Edition):

Wu, Ting. “Design techniques for PVT tolerant phase-locked loops.” 2007. Web. 13 Nov 2019.

Vancouver:

Wu T. Design techniques for PVT tolerant phase-locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2007. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/3866.

Council of Science Editors:

Wu T. Design techniques for PVT tolerant phase-locked loops. [Doctoral Dissertation]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/3866


University College Cork

20. Ó Tuama, Cillian. Interaction of additive and quantization noises in digital PLLs.

Degree: 2014, University College Cork

Phase-locked loops (PLLs) are a crucial component in modern communications systems. Comprising of a phase-detector, linear filter, and controllable oscillator, they are widely used in… (more)

Subjects/Keywords: Nonlinear dynamics; Phase jitter; Phase-locked loops; Noise; Difference equations

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APA (6th Edition):

Ó Tuama, C. (2014). Interaction of additive and quantization noises in digital PLLs. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/1831

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ó Tuama, Cillian. “Interaction of additive and quantization noises in digital PLLs.” 2014. Thesis, University College Cork. Accessed November 13, 2019. http://hdl.handle.net/10468/1831.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ó Tuama, Cillian. “Interaction of additive and quantization noises in digital PLLs.” 2014. Web. 13 Nov 2019.

Vancouver:

Ó Tuama C. Interaction of additive and quantization noises in digital PLLs. [Internet] [Thesis]. University College Cork; 2014. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/10468/1831.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ó Tuama C. Interaction of additive and quantization noises in digital PLLs. [Thesis]. University College Cork; 2014. Available from: http://hdl.handle.net/10468/1831

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

21. Lin, Ming-Lang. Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes.

Degree: PhD, 2010, University of Edinburgh

 Data conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and… (more)

Subjects/Keywords: 005.7; irregular sampling; phase-locked loops; frequency synthesizer

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APA (6th Edition):

Lin, M. (2010). Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/4627

Chicago Manual of Style (16th Edition):

Lin, Ming-Lang. “Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes.” 2010. Doctoral Dissertation, University of Edinburgh. Accessed November 13, 2019. http://hdl.handle.net/1842/4627.

MLA Handbook (7th Edition):

Lin, Ming-Lang. “Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes.” 2010. Web. 13 Nov 2019.

Vancouver:

Lin M. Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes. [Internet] [Doctoral dissertation]. University of Edinburgh; 2010. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1842/4627.

Council of Science Editors:

Lin M. Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes. [Doctoral Dissertation]. University of Edinburgh; 2010. Available from: http://hdl.handle.net/1842/4627

22. Uttarwar, Tushar. A digital multiplying delay locked loop for high frequency clock generation.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks… (more)

Subjects/Keywords: PLL; Phase-locked loops

…resolution in digital circuits. 1.2 OVERVIEW OF MULTIPLYING DELAY LOCKED LOOPS Efforts have been… …Digital MDLL …..7 2.1.1 Phase Noise Model of a Conventional… …multiplication has become a necessity for nearly all digital integrated circuits (ICs) in… …Locked Loops (MDLL) [5, 6, 7, 8] have been introduced recently as an… …PLL, to generate high frequency clock with very low jitter. 1.1 OVERVIEW OF PHASE LOCKED… 

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APA (6th Edition):

Uttarwar, T. (2011). A digital multiplying delay locked loop for high frequency clock generation. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/25739

Chicago Manual of Style (16th Edition):

Uttarwar, Tushar. “A digital multiplying delay locked loop for high frequency clock generation.” 2011. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/25739.

MLA Handbook (7th Edition):

Uttarwar, Tushar. “A digital multiplying delay locked loop for high frequency clock generation.” 2011. Web. 13 Nov 2019.

Vancouver:

Uttarwar T. A digital multiplying delay locked loop for high frequency clock generation. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/25739.

Council of Science Editors:

Uttarwar T. A digital multiplying delay locked loop for high frequency clock generation. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/25739

23. Shreeve, Robert. Substrate noise coupling in ring oscillator-based phase locked loops.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise… (more)

Subjects/Keywords: PLL; Phase-locked loops

…the power supply. An analog circuit block that is embedded in many IC’s is the phase locked… …substrate node to the PLL output phase (Spectre). The noise frequencies vary from 115 to… …transfer function from the substrate node to the PLL output phase (Spectre). The noise… …27 Simulated noise transfer function from the substrate node to the PLL output phase (… …noise . The magnitude and phase are extracted from a transient simulation… 

Page 1 Page 2 Page 3 Page 4 Page 5

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APA (6th Edition):

Shreeve, R. (2008). Substrate noise coupling in ring oscillator-based phase locked loops. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/8947

Chicago Manual of Style (16th Edition):

Shreeve, Robert. “Substrate noise coupling in ring oscillator-based phase locked loops.” 2008. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/8947.

MLA Handbook (7th Edition):

Shreeve, Robert. “Substrate noise coupling in ring oscillator-based phase locked loops.” 2008. Web. 13 Nov 2019.

Vancouver:

Shreeve R. Substrate noise coupling in ring oscillator-based phase locked loops. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/8947.

Council of Science Editors:

Shreeve R. Substrate noise coupling in ring oscillator-based phase locked loops. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/8947


The Ohio State University

24. Barat, Aakriti. Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis.

Degree: MS, Electrical and Computer Engineering, 2017, The Ohio State University

 An injection locked oscillator is a presented using wavelet analysis to evaluate the role of PLLs in RF transceivers. The goal is to evaluate injection… (more)

Subjects/Keywords: Electrical Engineering; Design, Phase Locked Loops, Wavelet Analysis

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APA (6th Edition):

Barat, A. (2017). Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685

Chicago Manual of Style (16th Edition):

Barat, Aakriti. “Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis.” 2017. Masters Thesis, The Ohio State University. Accessed November 13, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685.

MLA Handbook (7th Edition):

Barat, Aakriti. “Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis.” 2017. Web. 13 Nov 2019.

Vancouver:

Barat A. Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis. [Internet] [Masters thesis]. The Ohio State University; 2017. [cited 2019 Nov 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685.

Council of Science Editors:

Barat A. Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis. [Masters Thesis]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685


Carnegie Mellon University

25. Jackson, Thomas C. Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies.

Degree: 2017, Carnegie Mellon University

 In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to… (more)

Subjects/Keywords: Mixed Signal; Neurmorphic Computing; Oscillatory Neural Networks; Phase Locked Loops; RRAM

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APA (6th Edition):

Jackson, T. C. (2017). Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/1096

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jackson, Thomas C. “Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies.” 2017. Thesis, Carnegie Mellon University. Accessed November 13, 2019. http://repository.cmu.edu/dissertations/1096.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jackson, Thomas C. “Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies.” 2017. Web. 13 Nov 2019.

Vancouver:

Jackson TC. Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2019 Nov 13]. Available from: http://repository.cmu.edu/dissertations/1096.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jackson TC. Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/1096

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

26. Jarrett-Amor, Durand. Frequency calibration of the system clock of passive wireless microsystems.

Degree: 2017, Ryerson University

 This thesis presents a theoretical and simulated study of frequency calibration of the system clock of passive wireless microsystems. The proposed frequency calibration technique achieves… (more)

Subjects/Keywords: Phase-locked loops.; Passive components.; Oscillators, Electric.; Frequency synthesizers.

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APA (6th Edition):

Jarrett-Amor, D. (2017). Frequency calibration of the system clock of passive wireless microsystems. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6876

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jarrett-Amor, Durand. “Frequency calibration of the system clock of passive wireless microsystems.” 2017. Thesis, Ryerson University. Accessed November 13, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6876.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jarrett-Amor, Durand. “Frequency calibration of the system clock of passive wireless microsystems.” 2017. Web. 13 Nov 2019.

Vancouver:

Jarrett-Amor D. Frequency calibration of the system clock of passive wireless microsystems. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Nov 13]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6876.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jarrett-Amor D. Frequency calibration of the system clock of passive wireless microsystems. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6876

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

27. Zhou, Yushi. Injection-lock and reconfigurable charge-domain sampling mixers/filters for data communications over wireless channels.

Degree: 2015, Ryerson University

 This thesis provides a theoretical and experimental study of injection locking and reconfigurable charge-domain sampling mixers and filters for data communications over wireless channels. On… (more)

Subjects/Keywords: Phase locked loops.; Harmonic oscillators.; Radio frequency oscillators.; Wireless communication systems.

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APA (6th Edition):

Zhou, Y. (2015). Injection-lock and reconfigurable charge-domain sampling mixers/filters for data communications over wireless channels. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A3684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Yushi. “Injection-lock and reconfigurable charge-domain sampling mixers/filters for data communications over wireless channels.” 2015. Thesis, Ryerson University. Accessed November 13, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A3684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Yushi. “Injection-lock and reconfigurable charge-domain sampling mixers/filters for data communications over wireless channels.” 2015. Web. 13 Nov 2019.

Vancouver:

Zhou Y. Injection-lock and reconfigurable charge-domain sampling mixers/filters for data communications over wireless channels. [Internet] [Thesis]. Ryerson University; 2015. [cited 2019 Nov 13]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou Y. Injection-lock and reconfigurable charge-domain sampling mixers/filters for data communications over wireless channels. [Thesis]. Ryerson University; 2015. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

28. Inberg, R. Brandon. Enhanced step mode FTIR position control.

Degree: College of Engineering, 2005, Montana State University

 This thesis presents a modification to a typical Fourier transform infrared (FTIR) spectrometer to achieve finer spatial sampling and increased frequency range for step-scan experiments… (more)

Subjects/Keywords: Phase-locked loops.; Spectrum analysis.

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APA (6th Edition):

Inberg, R. B. (2005). Enhanced step mode FTIR position control. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Inberg, R Brandon. “Enhanced step mode FTIR position control.” 2005. Thesis, Montana State University. Accessed November 13, 2019. https://scholarworks.montana.edu/xmlui/handle/1/1536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Inberg, R Brandon. “Enhanced step mode FTIR position control.” 2005. Web. 13 Nov 2019.

Vancouver:

Inberg RB. Enhanced step mode FTIR position control. [Internet] [Thesis]. Montana State University; 2005. [cited 2019 Nov 13]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Inberg RB. Enhanced step mode FTIR position control. [Thesis]. Montana State University; 2005. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. George, Edmond (Edmond Fernandez). Semi-digital PLL architecture for ultra low bandwidth applications.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area… (more)

Subjects/Keywords: PLL; Phase-locked loops

…3 2 Background on Phase Locked Loops 5 2.1 Introduction to PLL… …Chapter 1: Introduction 1.1 Area of focus Phase Locked Loops(PLLs) are used in a wide… …Circuit design of low bandwidth semi-digital PLL 4.1 Loop components . . . . . 4.1.1 Phase… …semi-digital PLL . . . . . . . . . . . . . . . . . . . . 22 4.1 Phase Frequency Detector… …Locked Loops 2.1 Introduction to PLL A PLL is a feedback system consisting of a Voltage… 

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APA (6th Edition):

George, E. (. F. (2013). Semi-digital PLL architecture for ultra low bandwidth applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37710

Chicago Manual of Style (16th Edition):

George, Edmond (Edmond Fernandez). “Semi-digital PLL architecture for ultra low bandwidth applications.” 2013. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/37710.

MLA Handbook (7th Edition):

George, Edmond (Edmond Fernandez). “Semi-digital PLL architecture for ultra low bandwidth applications.” 2013. Web. 13 Nov 2019.

Vancouver:

George E(F. Semi-digital PLL architecture for ultra low bandwidth applications. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/37710.

Council of Science Editors:

George E(F. Semi-digital PLL architecture for ultra low bandwidth applications. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37710


Oregon State University

30. Bhagavatheeswaran, Shanthi, S. Design methodology for low-jitter phase-locked loops.

Degree: MS, Electrical and Computer Engineering, 2001, Oregon State University

 This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate… (more)

Subjects/Keywords: Phase-locked loops  – Computer simulation

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APA (6th Edition):

Bhagavatheeswaran, Shanthi, S. (2001). Design methodology for low-jitter phase-locked loops. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32786

Chicago Manual of Style (16th Edition):

Bhagavatheeswaran, Shanthi, S. “Design methodology for low-jitter phase-locked loops.” 2001. Masters Thesis, Oregon State University. Accessed November 13, 2019. http://hdl.handle.net/1957/32786.

MLA Handbook (7th Edition):

Bhagavatheeswaran, Shanthi, S. “Design methodology for low-jitter phase-locked loops.” 2001. Web. 13 Nov 2019.

Vancouver:

Bhagavatheeswaran, Shanthi S. Design methodology for low-jitter phase-locked loops. [Internet] [Masters thesis]. Oregon State University; 2001. [cited 2019 Nov 13]. Available from: http://hdl.handle.net/1957/32786.

Council of Science Editors:

Bhagavatheeswaran, Shanthi S. Design methodology for low-jitter phase-locked loops. [Masters Thesis]. Oregon State University; 2001. Available from: http://hdl.handle.net/1957/32786

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