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You searched for subject:(ASIC). Showing records 1 – 30 of 262 total matches.

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Linköping University

1. Lothian, Angus; Härnqvist, Ivar; Jakobsson, Adam; Westerlund, Arvid; Goding, Felix; Wahlman, Jacob; Scott, Kevin. B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC.

Degree: Computer and Information Science, 2020, Linköping University

  Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte… (more)

Subjects/Keywords: B-ASIC; ASIC; ASIC verktygslåda; Python ASIC; Python-bibliotek; programvaruteknik; mjukvaruutveckling; programvaruutveckling; Software Engineering; Programvaruteknik

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APA (6th Edition):

Lothian, Angus; Härnqvist, Ivar; Jakobsson, Adam; Westerlund, Arvid; Goding, Felix; Wahlman, Jacob; Scott, K. (2020). B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lothian, Angus; Härnqvist, Ivar; Jakobsson, Adam; Westerlund, Arvid; Goding, Felix; Wahlman, Jacob; Scott, Kevin. “B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC.” 2020. Thesis, Linköping University. Accessed August 12, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lothian, Angus; Härnqvist, Ivar; Jakobsson, Adam; Westerlund, Arvid; Goding, Felix; Wahlman, Jacob; Scott, Kevin. “B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC.” 2020. Web. 12 Aug 2020.

Vancouver:

Lothian, Angus; Härnqvist, Ivar; Jakobsson, Adam; Westerlund, Arvid; Goding, Felix; Wahlman, Jacob; Scott K. B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC. [Internet] [Thesis]. Linköping University; 2020. [cited 2020 Aug 12]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lothian, Angus; Härnqvist, Ivar; Jakobsson, Adam; Westerlund, Arvid; Goding, Felix; Wahlman, Jacob; Scott K. B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC. [Thesis]. Linköping University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

2. DUTTA, MADHULIKA. DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY.

Degree: MS, Engineering : Electrical Engineering, 2003, University of Cincinnati

 The need for immediate health monitoring, arising in situations like war or emergency call for the development of devices that do instant clinical screening to… (more)

Subjects/Keywords: biosensor; ASIC

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APA (6th Edition):

DUTTA, M. (2003). DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572

Chicago Manual of Style (16th Edition):

DUTTA, MADHULIKA. “DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY.” 2003. Masters Thesis, University of Cincinnati. Accessed August 12, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.

MLA Handbook (7th Edition):

DUTTA, MADHULIKA. “DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY.” 2003. Web. 12 Aug 2020.

Vancouver:

DUTTA M. DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY. [Internet] [Masters thesis]. University of Cincinnati; 2003. [cited 2020 Aug 12]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.

Council of Science Editors:

DUTTA M. DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY. [Masters Thesis]. University of Cincinnati; 2003. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572


Universitat Politècnica de València

3. Marín Tobón, César Augusto. PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog.

Degree: 2017, Universitat Politècnica de València

 ALICE (A Large Ion Collider Experiment) is the heavy-ion experiment at the Large Hadron Collider (LHC) at CERN. As an important part of its upgrade… (more)

Subjects/Keywords: Microelectronics; ASIC; Pixel detectors; Readout

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APA (6th Edition):

Marín Tobón, C. A. (2017). PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog. (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/86154

Chicago Manual of Style (16th Edition):

Marín Tobón, César Augusto. “PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog. ” 2017. Doctoral Dissertation, Universitat Politècnica de València. Accessed August 12, 2020. http://hdl.handle.net/10251/86154.

MLA Handbook (7th Edition):

Marín Tobón, César Augusto. “PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog. ” 2017. Web. 12 Aug 2020.

Vancouver:

Marín Tobón CA. PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog. [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2017. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/10251/86154.

Council of Science Editors:

Marín Tobón CA. PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog. [Doctoral Dissertation]. Universitat Politècnica de València; 2017. Available from: http://hdl.handle.net/10251/86154


Cornell University

4. Lakeman, Joseph. An Fpga Based Test Bench With High Speed Data Acquisition For Mixed Signal Applications .

Degree: 2015, Cornell University

 Although multiple data link protocols that can handle 10's of Gbps have been developed over the years, engineers in the test industry either rely on… (more)

Subjects/Keywords: FPGA; ASIC Testing; Data Acquisition

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APA (6th Edition):

Lakeman, J. (2015). An Fpga Based Test Bench With High Speed Data Acquisition For Mixed Signal Applications . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/41111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lakeman, Joseph. “An Fpga Based Test Bench With High Speed Data Acquisition For Mixed Signal Applications .” 2015. Thesis, Cornell University. Accessed August 12, 2020. http://hdl.handle.net/1813/41111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lakeman, Joseph. “An Fpga Based Test Bench With High Speed Data Acquisition For Mixed Signal Applications .” 2015. Web. 12 Aug 2020.

Vancouver:

Lakeman J. An Fpga Based Test Bench With High Speed Data Acquisition For Mixed Signal Applications . [Internet] [Thesis]. Cornell University; 2015. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/1813/41111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lakeman J. An Fpga Based Test Bench With High Speed Data Acquisition For Mixed Signal Applications . [Thesis]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/41111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

5. Kim, Jin Hee. Synthesizable FPGA Fabrics.

Degree: 2016, University of Toronto

With increasing effort required for custom layout in deep-submicron technologies, we consider implementing field-programmable gate arrays (FPGAs) using standard cells. First, we extend the open-source… (more)

Subjects/Keywords: ASIC; FPGA; VTR; 0464

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APA (6th Edition):

Kim, J. H. (2016). Synthesizable FPGA Fabrics. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/72701

Chicago Manual of Style (16th Edition):

Kim, Jin Hee. “Synthesizable FPGA Fabrics.” 2016. Masters Thesis, University of Toronto. Accessed August 12, 2020. http://hdl.handle.net/1807/72701.

MLA Handbook (7th Edition):

Kim, Jin Hee. “Synthesizable FPGA Fabrics.” 2016. Web. 12 Aug 2020.

Vancouver:

Kim JH. Synthesizable FPGA Fabrics. [Internet] [Masters thesis]. University of Toronto; 2016. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/1807/72701.

Council of Science Editors:

Kim JH. Synthesizable FPGA Fabrics. [Masters Thesis]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/72701

6. Andrianjohany, Nomena Gabriel. Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative : Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening.

Degree: Docteur es, Sciences pour l'ingénieur. Micro et Nanoélectronique, 2018, Aix Marseille Université

La forte densité d'intégration et la miniaturisation des composants électroniques les rendent de plus en plus sensibles aux effets singuliers. Cette sensibilité est observée dans… (more)

Subjects/Keywords: See; Asic; Spice; Prédiction; Méthodologie; See; Asic; Spice; Prediction; Methodology

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APA (6th Edition):

Andrianjohany, N. G. (2018). Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative : Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2018AIXM0099

Chicago Manual of Style (16th Edition):

Andrianjohany, Nomena Gabriel. “Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative : Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening.” 2018. Doctoral Dissertation, Aix Marseille Université. Accessed August 12, 2020. http://www.theses.fr/2018AIXM0099.

MLA Handbook (7th Edition):

Andrianjohany, Nomena Gabriel. “Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative : Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening.” 2018. Web. 12 Aug 2020.

Vancouver:

Andrianjohany NG. Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative : Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening. [Internet] [Doctoral dissertation]. Aix Marseille Université 2018. [cited 2020 Aug 12]. Available from: http://www.theses.fr/2018AIXM0099.

Council of Science Editors:

Andrianjohany NG. Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative : Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening. [Doctoral Dissertation]. Aix Marseille Université 2018. Available from: http://www.theses.fr/2018AIXM0099

7. Ulman, Shrutin A. Asic for biomedical applications; -.

Degree: Physics, 2004, Goa University

None

Appendix p.178 - 180

Advisors/Committee Members: Bhattacharyya, A B.

Subjects/Keywords: applications; Asic; biomedical

Page 1

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APA (6th Edition):

Ulman, S. A. (2004). Asic for biomedical applications; -. (Thesis). Goa University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/35674

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ulman, Shrutin A. “Asic for biomedical applications; -.” 2004. Thesis, Goa University. Accessed August 12, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/35674.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ulman, Shrutin A. “Asic for biomedical applications; -.” 2004. Web. 12 Aug 2020.

Vancouver:

Ulman SA. Asic for biomedical applications; -. [Internet] [Thesis]. Goa University; 2004. [cited 2020 Aug 12]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/35674.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ulman SA. Asic for biomedical applications; -. [Thesis]. Goa University; 2004. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/35674

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

8. Kratzer, Eric Martin. Characterization of acid sensing ion channel (ASIC) in mouse olfactory bulb.

Degree: PhD, Molecular and Cellular Biology, 2007, Oregon State University

 This study examined the role of acid- sensing ion channels (ASICs) in interneuron synaptic modulation. ASICS are ultra fine discriminators of acidic conditions in the… (more)

Subjects/Keywords: ASIC; Ion channels

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APA (6th Edition):

Kratzer, E. M. (2007). Characterization of acid sensing ion channel (ASIC) in mouse olfactory bulb. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7807

Chicago Manual of Style (16th Edition):

Kratzer, Eric Martin. “Characterization of acid sensing ion channel (ASIC) in mouse olfactory bulb.” 2007. Doctoral Dissertation, Oregon State University. Accessed August 12, 2020. http://hdl.handle.net/1957/7807.

MLA Handbook (7th Edition):

Kratzer, Eric Martin. “Characterization of acid sensing ion channel (ASIC) in mouse olfactory bulb.” 2007. Web. 12 Aug 2020.

Vancouver:

Kratzer EM. Characterization of acid sensing ion channel (ASIC) in mouse olfactory bulb. [Internet] [Doctoral dissertation]. Oregon State University; 2007. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/1957/7807.

Council of Science Editors:

Kratzer EM. Characterization of acid sensing ion channel (ASIC) in mouse olfactory bulb. [Doctoral Dissertation]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/7807


University of California – San Francisco

9. Bohlen, Christopher. Venom-derived toxins as biochemical and pharmacological probes of pain pathway.

Degree: Neuroscience, 2012, University of California – San Francisco

 Venoms often target vital processes to cause paralysis or death, but many types of venom also elicit notoriously intense pain. While these pain-producing effects can… (more)

Subjects/Keywords: Neurosciences; ASIC; pain; toxin; TRPV1; venom

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APA (6th Edition):

Bohlen, C. (2012). Venom-derived toxins as biochemical and pharmacological probes of pain pathway. (Thesis). University of California – San Francisco. Retrieved from http://www.escholarship.org/uc/item/2wx6v5w9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bohlen, Christopher. “Venom-derived toxins as biochemical and pharmacological probes of pain pathway.” 2012. Thesis, University of California – San Francisco. Accessed August 12, 2020. http://www.escholarship.org/uc/item/2wx6v5w9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bohlen, Christopher. “Venom-derived toxins as biochemical and pharmacological probes of pain pathway.” 2012. Web. 12 Aug 2020.

Vancouver:

Bohlen C. Venom-derived toxins as biochemical and pharmacological probes of pain pathway. [Internet] [Thesis]. University of California – San Francisco; 2012. [cited 2020 Aug 12]. Available from: http://www.escholarship.org/uc/item/2wx6v5w9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bohlen C. Venom-derived toxins as biochemical and pharmacological probes of pain pathway. [Thesis]. University of California – San Francisco; 2012. Available from: http://www.escholarship.org/uc/item/2wx6v5w9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

10. Gianelli, Alberto. A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier.

Degree: 2018, University of Illinois – Chicago

 In this thesis an ASIC design of an hardware GMM-Based Speaker Classifier is presented.The Classifier is a fundamental component of a Speaker Identification system, that… (more)

Subjects/Keywords: GMM; speaker recognition; low power; ASIC

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APA (6th Edition):

Gianelli, A. (2018). A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/22958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gianelli, Alberto. “A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier.” 2018. Thesis, University of Illinois – Chicago. Accessed August 12, 2020. http://hdl.handle.net/10027/22958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gianelli, Alberto. “A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier.” 2018. Web. 12 Aug 2020.

Vancouver:

Gianelli A. A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier. [Internet] [Thesis]. University of Illinois – Chicago; 2018. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/10027/22958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gianelli A. A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier. [Thesis]. University of Illinois – Chicago; 2018. Available from: http://hdl.handle.net/10027/22958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Holstensson, Oskar. Study of Interferer Canceling Systems in a Software Defined Radio Receiver.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  This thesis describes the work related to an interferer rejection system employing frequency analysis and cancellation through phase-opposed signal injection. The first device in… (more)

Subjects/Keywords: ASIC; FFT; Interferer Cancellation; RF; SDR; VHDL

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APA (6th Edition):

Holstensson, O. (2013). Study of Interferer Canceling Systems in a Software Defined Radio Receiver. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Holstensson, Oskar. “Study of Interferer Canceling Systems in a Software Defined Radio Receiver.” 2013. Thesis, Linköping UniversityLinköping University. Accessed August 12, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Holstensson, Oskar. “Study of Interferer Canceling Systems in a Software Defined Radio Receiver.” 2013. Web. 12 Aug 2020.

Vancouver:

Holstensson O. Study of Interferer Canceling Systems in a Software Defined Radio Receiver. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Aug 12]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Holstensson O. Study of Interferer Canceling Systems in a Software Defined Radio Receiver. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Zhou, Yuteng. Computer Vision System-On-Chip Designs for Intelligent Vehicles.

Degree: PhD, 2018, Worcester Polytechnic Institute

  Intelligent vehicle technologies are growing rapidly that can enhance road safety, improve transport efficiency, and aid driver operations through sensors and intelligence. Advanced driver… (more)

Subjects/Keywords: FPGA; computer vision; deep learning; ASIC

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APA (6th Edition):

Zhou, Y. (2018). Computer Vision System-On-Chip Designs for Intelligent Vehicles. (Doctoral Dissertation). Worcester Polytechnic Institute. Retrieved from etd-042418-153258 ; https://digitalcommons.wpi.edu/etd-dissertations/162

Chicago Manual of Style (16th Edition):

Zhou, Yuteng. “Computer Vision System-On-Chip Designs for Intelligent Vehicles.” 2018. Doctoral Dissertation, Worcester Polytechnic Institute. Accessed August 12, 2020. etd-042418-153258 ; https://digitalcommons.wpi.edu/etd-dissertations/162.

MLA Handbook (7th Edition):

Zhou, Yuteng. “Computer Vision System-On-Chip Designs for Intelligent Vehicles.” 2018. Web. 12 Aug 2020.

Vancouver:

Zhou Y. Computer Vision System-On-Chip Designs for Intelligent Vehicles. [Internet] [Doctoral dissertation]. Worcester Polytechnic Institute; 2018. [cited 2020 Aug 12]. Available from: etd-042418-153258 ; https://digitalcommons.wpi.edu/etd-dissertations/162.

Council of Science Editors:

Zhou Y. Computer Vision System-On-Chip Designs for Intelligent Vehicles. [Doctoral Dissertation]. Worcester Polytechnic Institute; 2018. Available from: etd-042418-153258 ; https://digitalcommons.wpi.edu/etd-dissertations/162


Georgia Tech

13. Toreyin, Hakan. Design of a low-power interface circuitry for a vestibular prosthesis system.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The human vestibular system is responsible for maintaining balance and orientation, and stabilizing gaze during head motion. Head motion is sensed by vestibular sensors and… (more)

Subjects/Keywords: Vestibular prosthesis ASIC; Analog signal processing

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APA (6th Edition):

Toreyin, H. (2014). Design of a low-power interface circuitry for a vestibular prosthesis system. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54018

Chicago Manual of Style (16th Edition):

Toreyin, Hakan. “Design of a low-power interface circuitry for a vestibular prosthesis system.” 2014. Doctoral Dissertation, Georgia Tech. Accessed August 12, 2020. http://hdl.handle.net/1853/54018.

MLA Handbook (7th Edition):

Toreyin, Hakan. “Design of a low-power interface circuitry for a vestibular prosthesis system.” 2014. Web. 12 Aug 2020.

Vancouver:

Toreyin H. Design of a low-power interface circuitry for a vestibular prosthesis system. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/1853/54018.

Council of Science Editors:

Toreyin H. Design of a low-power interface circuitry for a vestibular prosthesis system. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54018


University of North Texas

14. Simpson, Zachary P. Optimization of RSA Cryptography for FPGA and ASIC Applications.

Degree: 2019, University of North Texas

 RSA cryptography is one of the most widely used cryptosystems in the world. FPGA/ASIC implementations for the classic RSA cryptosystem have high resource utilization due… (more)

Subjects/Keywords: FPGA; ASIC; RSA; Engineering, Electronics and Electrical

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Simpson, Z. P. (2019). Optimization of RSA Cryptography for FPGA and ASIC Applications. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc1609146/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Simpson, Zachary P. “Optimization of RSA Cryptography for FPGA and ASIC Applications.” 2019. Thesis, University of North Texas. Accessed August 12, 2020. https://digital.library.unt.edu/ark:/67531/metadc1609146/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Simpson, Zachary P. “Optimization of RSA Cryptography for FPGA and ASIC Applications.” 2019. Web. 12 Aug 2020.

Vancouver:

Simpson ZP. Optimization of RSA Cryptography for FPGA and ASIC Applications. [Internet] [Thesis]. University of North Texas; 2019. [cited 2020 Aug 12]. Available from: https://digital.library.unt.edu/ark:/67531/metadc1609146/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Simpson ZP. Optimization of RSA Cryptography for FPGA and ASIC Applications. [Thesis]. University of North Texas; 2019. Available from: https://digital.library.unt.edu/ark:/67531/metadc1609146/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Paris-Sud – Paris XI

15. Chen, Yingtao. Simulations and electronics development for the LHAASO experiment : Simulations et développement d’électronique pour l’expérience LHAASO.

Degree: Docteur es, Physique, 2015, Université Paris-Sud – Paris XI

Le travail de thèse porte sur l'étude de l'électronique front-end pour le télescope WFCTA (Wide Field of View Cherenkov Telescope Array,) qui est l'un des… (more)

Subjects/Keywords: Electronique front-end; ASIC; PMT; WFCTA; LHAASO; Front-end electronics; ASIC; PMT; WFCTA; LHAASO

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2015). Simulations and electronics development for the LHAASO experiment : Simulations et développement d’électronique pour l’expérience LHAASO. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2015PA112147

Chicago Manual of Style (16th Edition):

Chen, Yingtao. “Simulations and electronics development for the LHAASO experiment : Simulations et développement d’électronique pour l’expérience LHAASO.” 2015. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed August 12, 2020. http://www.theses.fr/2015PA112147.

MLA Handbook (7th Edition):

Chen, Yingtao. “Simulations and electronics development for the LHAASO experiment : Simulations et développement d’électronique pour l’expérience LHAASO.” 2015. Web. 12 Aug 2020.

Vancouver:

Chen Y. Simulations and electronics development for the LHAASO experiment : Simulations et développement d’électronique pour l’expérience LHAASO. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2015. [cited 2020 Aug 12]. Available from: http://www.theses.fr/2015PA112147.

Council of Science Editors:

Chen Y. Simulations and electronics development for the LHAASO experiment : Simulations et développement d’électronique pour l’expérience LHAASO. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2015. Available from: http://www.theses.fr/2015PA112147

16. -3078-9498. EDA design for Microscale Modular Assembled ASIC (M2A2) circuits.

Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin

 As the semiconductor industry has driven down the minimum feature size to well below 50nm, the mask cost to make devices has skyrocketed. The cost… (more)

Subjects/Keywords: ASIC; Structured ASIC; M2A2; FPGA; Low volume ASIC; VLSI

…87 6.1 ASIC Standard Cell Results… …98 6.8 Comparison of M2A2 and ASIC Performance… …104 viii List of Tables Table 1: ASIC vs. FPGA Cost and Performance Comparison… …5 Table 2: ASIC Design Specifications… …11 Table 3: ASIC Standard Cell Design QoR… 

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APA (6th Edition):

-3078-9498. (2017). EDA design for Microscale Modular Assembled ASIC (M2A2) circuits. (Masters Thesis). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/5481

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-3078-9498. “EDA design for Microscale Modular Assembled ASIC (M2A2) circuits.” 2017. Masters Thesis, University of Texas – Austin. Accessed August 12, 2020. http://dx.doi.org/10.26153/tsw/5481.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-3078-9498. “EDA design for Microscale Modular Assembled ASIC (M2A2) circuits.” 2017. Web. 12 Aug 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-3078-9498. EDA design for Microscale Modular Assembled ASIC (M2A2) circuits. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2020 Aug 12]. Available from: http://dx.doi.org/10.26153/tsw/5481.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-3078-9498. EDA design for Microscale Modular Assembled ASIC (M2A2) circuits. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://dx.doi.org/10.26153/tsw/5481

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

17. Massolino, Pedro Maat Costa. Projeto e avaliação de um co-processador  criptográfico pós-quântico.

Degree: Mestrado, Sistemas Digitais, 2014, University of São Paulo

Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como… (more)

Subjects/Keywords: ASIC; ASIC; Circuitos digitais; Códigos corretores de erro; Criptografia; Cryptography; Digital circuits; Error correcting codes; FPGA; FPGA; SoC; SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Massolino, P. M. C. (2014). Projeto e avaliação de um co-processador  criptográfico pós-quântico. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3141/tde-22042015-171235/ ;

Chicago Manual of Style (16th Edition):

Massolino, Pedro Maat Costa. “Projeto e avaliação de um co-processador  criptográfico pós-quântico.” 2014. Masters Thesis, University of São Paulo. Accessed August 12, 2020. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-22042015-171235/ ;.

MLA Handbook (7th Edition):

Massolino, Pedro Maat Costa. “Projeto e avaliação de um co-processador  criptográfico pós-quântico.” 2014. Web. 12 Aug 2020.

Vancouver:

Massolino PMC. Projeto e avaliação de um co-processador  criptográfico pós-quântico. [Internet] [Masters thesis]. University of São Paulo; 2014. [cited 2020 Aug 12]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3141/tde-22042015-171235/ ;.

Council of Science Editors:

Massolino PMC. Projeto e avaliação de um co-processador  criptográfico pós-quântico. [Masters Thesis]. University of São Paulo; 2014. Available from: http://www.teses.usp.br/teses/disponiveis/3/3141/tde-22042015-171235/ ;


Universidade do Rio Grande do Norte

18. Duarte, José Marcelo Lima. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .

Degree: 2012, Universidade do Rio Grande do Norte

 The use of Multiple Input Multiple Output (MIMO) systems has permitted the recent evolution of wireless communication standards. The Spatial Multiplexing MIMO technique, in particular,… (more)

Subjects/Keywords: MIMO; deteccão; demodulacão; processamento digital de sinais; arquitetura; VLSI; ASIC; FPGA; MIMO; detection; demodulation; digital signal processing; architecture; VLSI; ASIC; FPGA

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APA (6th Edition):

Duarte, J. M. L. (2012). Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18575

Chicago Manual of Style (16th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed August 12, 2020. http://repositorio.ufrn.br/handle/123456789/18575.

MLA Handbook (7th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Web. 12 Aug 2020.

Vancouver:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2012. [cited 2020 Aug 12]. Available from: http://repositorio.ufrn.br/handle/123456789/18575.

Council of Science Editors:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/18575


Universidade Federal de Santa Maria

19. Leonardo Londero de Oliveira. ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS.

Degree: 2009, Universidade Federal de Santa Maria

This thesis presents contributions to node localization in mobile sensor networks. Considering the importance of localization algorithms in identifying the location of an event in… (more)

Subjects/Keywords: ASIC; algoritmo de localização; redes de sensores móveis; ENGENHARIA ELETRICA; mobile sensor networks; localization algorithm; ASIC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, L. L. d. (2009). ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS. (Thesis). Universidade Federal de Santa Maria. Retrieved from http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=2915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Leonardo Londero de. “ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS.” 2009. Thesis, Universidade Federal de Santa Maria. Accessed August 12, 2020. http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=2915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Leonardo Londero de. “ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS.” 2009. Web. 12 Aug 2020.

Vancouver:

Oliveira LLd. ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS. [Internet] [Thesis]. Universidade Federal de Santa Maria; 2009. [cited 2020 Aug 12]. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=2915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira LLd. ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS. [Thesis]. Universidade Federal de Santa Maria; 2009. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=2915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

20. Duarte, José Marcelo Lima. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .

Degree: 2012, Universidade do Rio Grande do Norte

 The use of Multiple Input Multiple Output (MIMO) systems has permitted the recent evolution of wireless communication standards. The Spatial Multiplexing MIMO technique, in particular,… (more)

Subjects/Keywords: MIMO; deteccão; demodulacão; processamento digital de sinais; arquitetura; VLSI; ASIC; FPGA; MIMO; detection; demodulation; digital signal processing; architecture; VLSI; ASIC; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Duarte, J. M. L. (2012). Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18575

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed August 12, 2020. http://repositorio.ufrn.br/handle/123456789/18575.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Duarte, José Marcelo Lima. “Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave .” 2012. Web. 12 Aug 2020.

Vancouver:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2020 Aug 12]. Available from: http://repositorio.ufrn.br/handle/123456789/18575.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Duarte JML. Algoritmos e Arquiteturas VLSI para Detectores MIMO com Decisão Suave . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/18575

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Cherif, Zouha. Modelling and characterization of physically unclonable functions : Modélisation et caractérisation des fonctions non clonables physiquement.

Degree: Docteur es, Microélectronique, 2014, Saint-Etienne

Les fonctions non clonables physiquement, appelées PUF (Physically Unclonable Functions), représentent une technologie innovante qui permet de résoudre certains problèmes de sécurité et d’identification. Comme… (more)

Subjects/Keywords: Fonctions non clonables physiquement; ASIC; FPGA; Authentification; Clé de chiffrement; Physically unclonable functions; ASIC; FPGA; Authentication; Encryption key

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cherif, Z. (2014). Modelling and characterization of physically unclonable functions : Modélisation et caractérisation des fonctions non clonables physiquement. (Doctoral Dissertation). Saint-Etienne. Retrieved from http://www.theses.fr/2014STET4005

Chicago Manual of Style (16th Edition):

Cherif, Zouha. “Modelling and characterization of physically unclonable functions : Modélisation et caractérisation des fonctions non clonables physiquement.” 2014. Doctoral Dissertation, Saint-Etienne. Accessed August 12, 2020. http://www.theses.fr/2014STET4005.

MLA Handbook (7th Edition):

Cherif, Zouha. “Modelling and characterization of physically unclonable functions : Modélisation et caractérisation des fonctions non clonables physiquement.” 2014. Web. 12 Aug 2020.

Vancouver:

Cherif Z. Modelling and characterization of physically unclonable functions : Modélisation et caractérisation des fonctions non clonables physiquement. [Internet] [Doctoral dissertation]. Saint-Etienne; 2014. [cited 2020 Aug 12]. Available from: http://www.theses.fr/2014STET4005.

Council of Science Editors:

Cherif Z. Modelling and characterization of physically unclonable functions : Modélisation et caractérisation des fonctions non clonables physiquement. [Doctoral Dissertation]. Saint-Etienne; 2014. Available from: http://www.theses.fr/2014STET4005


Université Paris-Sud – Paris XI

22. Michalowska, Alicja. Étude et développement d’ASIC de lecture de détecteurs matriciels en CdTe pour application spatiale en technologie sub-micrométrique : Studies and development of a readout ASIC for pixelated CdTe detectors for space applications.

Degree: Docteur es, Physique, 2013, Université Paris-Sud – Paris XI

 Le travail présenté dans ce manuscrit a été effectué au sein de l’équipe de microélectronique de l’Institut de Recherche sur les lois Fondamentales de l’Univers… (more)

Subjects/Keywords: Circuit de lecture; Electronique frontale; ASIC; Tellurure de cadmium; Readout electronics; Front-end; ASIC; Cadmium Telluride

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Michalowska, A. (2013). Étude et développement d’ASIC de lecture de détecteurs matriciels en CdTe pour application spatiale en technologie sub-micrométrique : Studies and development of a readout ASIC for pixelated CdTe detectors for space applications. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2013PA112332

Chicago Manual of Style (16th Edition):

Michalowska, Alicja. “Étude et développement d’ASIC de lecture de détecteurs matriciels en CdTe pour application spatiale en technologie sub-micrométrique : Studies and development of a readout ASIC for pixelated CdTe detectors for space applications.” 2013. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed August 12, 2020. http://www.theses.fr/2013PA112332.

MLA Handbook (7th Edition):

Michalowska, Alicja. “Étude et développement d’ASIC de lecture de détecteurs matriciels en CdTe pour application spatiale en technologie sub-micrométrique : Studies and development of a readout ASIC for pixelated CdTe detectors for space applications.” 2013. Web. 12 Aug 2020.

Vancouver:

Michalowska A. Étude et développement d’ASIC de lecture de détecteurs matriciels en CdTe pour application spatiale en technologie sub-micrométrique : Studies and development of a readout ASIC for pixelated CdTe detectors for space applications. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2013. [cited 2020 Aug 12]. Available from: http://www.theses.fr/2013PA112332.

Council of Science Editors:

Michalowska A. Étude et développement d’ASIC de lecture de détecteurs matriciels en CdTe pour application spatiale en technologie sub-micrométrique : Studies and development of a readout ASIC for pixelated CdTe detectors for space applications. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2013. Available from: http://www.theses.fr/2013PA112332

23. Jacquot, Florian. Migraine et sensibilisation centrale : Rôles de l'amygdale dans les troubles sensoriels et anxio/dépressifs dans un modèle de migraine chez le rat. : Migraine and central sensitization : Role of the amygdala in sensory disorders and anxiety/depression in a reat model of migraine.

Degree: Docteur es, Neurosciences, 2014, Clermont-Ferrand 1

La migraine est un désordre neurovasculaire caractérisé par des crises récurrentes de céphalée accompagnées de troubles neurologiques variables dont l'allodynie cutanée.Chez un petit nombre de… (more)

Subjects/Keywords: Migraine; Amygdale médiane; Anxiété/dépression; ASIC 1A; Migraine; Medial amygdala; Behiavor; Anxiety/depression; ASIC 1A; 570; 610

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jacquot, F. (2014). Migraine et sensibilisation centrale : Rôles de l'amygdale dans les troubles sensoriels et anxio/dépressifs dans un modèle de migraine chez le rat. : Migraine and central sensitization : Role of the amygdala in sensory disorders and anxiety/depression in a reat model of migraine. (Doctoral Dissertation). Clermont-Ferrand 1. Retrieved from http://www.theses.fr/2014CLF1DD03

Chicago Manual of Style (16th Edition):

Jacquot, Florian. “Migraine et sensibilisation centrale : Rôles de l'amygdale dans les troubles sensoriels et anxio/dépressifs dans un modèle de migraine chez le rat. : Migraine and central sensitization : Role of the amygdala in sensory disorders and anxiety/depression in a reat model of migraine.” 2014. Doctoral Dissertation, Clermont-Ferrand 1. Accessed August 12, 2020. http://www.theses.fr/2014CLF1DD03.

MLA Handbook (7th Edition):

Jacquot, Florian. “Migraine et sensibilisation centrale : Rôles de l'amygdale dans les troubles sensoriels et anxio/dépressifs dans un modèle de migraine chez le rat. : Migraine and central sensitization : Role of the amygdala in sensory disorders and anxiety/depression in a reat model of migraine.” 2014. Web. 12 Aug 2020.

Vancouver:

Jacquot F. Migraine et sensibilisation centrale : Rôles de l'amygdale dans les troubles sensoriels et anxio/dépressifs dans un modèle de migraine chez le rat. : Migraine and central sensitization : Role of the amygdala in sensory disorders and anxiety/depression in a reat model of migraine. [Internet] [Doctoral dissertation]. Clermont-Ferrand 1; 2014. [cited 2020 Aug 12]. Available from: http://www.theses.fr/2014CLF1DD03.

Council of Science Editors:

Jacquot F. Migraine et sensibilisation centrale : Rôles de l'amygdale dans les troubles sensoriels et anxio/dépressifs dans un modèle de migraine chez le rat. : Migraine and central sensitization : Role of the amygdala in sensory disorders and anxiety/depression in a reat model of migraine. [Doctoral Dissertation]. Clermont-Ferrand 1; 2014. Available from: http://www.theses.fr/2014CLF1DD03

24. Benjelloun, Zineb. Contribution à l'amélioration des performances d'une chaîne de mesure de la fréquence cardiaque en milieu bruité : Contribution to the improvement of the performance of a heart rate detector in noisy environment.

Degree: Docteur es, Mécanique, physique, micro et nanoélectronique, 2017, Aix Marseille Université

Les activités liées au développement d’objets connectés munis d’intelligence embarquée ont connu un essor considérable ces dernières années, en particulier pour les applications médicales. Dans… (more)

Subjects/Keywords: Asic; Cmos; Détection des battements cardiaques; Ecg; Gilbert; Multiplieur; Snr; Asic; Cmos; Heartbeat Detection; Ecg; Gilbert; Multiplier; Snr

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Benjelloun, Z. (2017). Contribution à l'amélioration des performances d'une chaîne de mesure de la fréquence cardiaque en milieu bruité : Contribution to the improvement of the performance of a heart rate detector in noisy environment. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2017AIXM0638

Chicago Manual of Style (16th Edition):

Benjelloun, Zineb. “Contribution à l'amélioration des performances d'une chaîne de mesure de la fréquence cardiaque en milieu bruité : Contribution to the improvement of the performance of a heart rate detector in noisy environment.” 2017. Doctoral Dissertation, Aix Marseille Université. Accessed August 12, 2020. http://www.theses.fr/2017AIXM0638.

MLA Handbook (7th Edition):

Benjelloun, Zineb. “Contribution à l'amélioration des performances d'une chaîne de mesure de la fréquence cardiaque en milieu bruité : Contribution to the improvement of the performance of a heart rate detector in noisy environment.” 2017. Web. 12 Aug 2020.

Vancouver:

Benjelloun Z. Contribution à l'amélioration des performances d'une chaîne de mesure de la fréquence cardiaque en milieu bruité : Contribution to the improvement of the performance of a heart rate detector in noisy environment. [Internet] [Doctoral dissertation]. Aix Marseille Université 2017. [cited 2020 Aug 12]. Available from: http://www.theses.fr/2017AIXM0638.

Council of Science Editors:

Benjelloun Z. Contribution à l'amélioration des performances d'une chaîne de mesure de la fréquence cardiaque en milieu bruité : Contribution to the improvement of the performance of a heart rate detector in noisy environment. [Doctoral Dissertation]. Aix Marseille Université 2017. Available from: http://www.theses.fr/2017AIXM0638


Brno University of Technology

25. Walletzký, Ondřej. Implementace jádra 8-bitového mikrokontroléru do FPGA a ASIC: Implementation of 8-bit microprocessor into FPGA chip.

Degree: 2019, Brno University of Technology

 This thesis deals with design of microprocessor compatible with one of 8-bit microcontrollers manufactured by Microchip company. Theoretical part of this thesis analyzes architectures of… (more)

Subjects/Keywords: PIC; Microchip; architektura; FPGA; ASIC; mikrokontrolér; návrh; implementace; PIC; Microchip; architecture; FPGA; ASIC; microcontroller; design; implementation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Walletzký, O. (2019). Implementace jádra 8-bitového mikrokontroléru do FPGA a ASIC: Implementation of 8-bit microprocessor into FPGA chip. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/34149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Walletzký, Ondřej. “Implementace jádra 8-bitového mikrokontroléru do FPGA a ASIC: Implementation of 8-bit microprocessor into FPGA chip.” 2019. Thesis, Brno University of Technology. Accessed August 12, 2020. http://hdl.handle.net/11012/34149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Walletzký, Ondřej. “Implementace jádra 8-bitového mikrokontroléru do FPGA a ASIC: Implementation of 8-bit microprocessor into FPGA chip.” 2019. Web. 12 Aug 2020.

Vancouver:

Walletzký O. Implementace jádra 8-bitového mikrokontroléru do FPGA a ASIC: Implementation of 8-bit microprocessor into FPGA chip. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/11012/34149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Walletzký O. Implementace jádra 8-bitového mikrokontroléru do FPGA a ASIC: Implementation of 8-bit microprocessor into FPGA chip. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/34149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Soukup, Luděk. Návrh a realizace matematických operací v obvodech FPGA: Design and realization of mathematical operations in FPGA circuits.

Degree: 2019, Brno University of Technology

 This bachelor’s thesis deals with the issue of realization of mathematical operations in digital circuits with a focus on FPGA and ASIC architectures. The attention… (more)

Subjects/Keywords: VHDL; FPGA; ASIC; Matematické operace; Goniometrické funkce; Spartan-3; VHDL; FPGA; ASIC; Mathematical operations; Trigonometric functions; Spartan-3

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soukup, L. (2019). Návrh a realizace matematických operací v obvodech FPGA: Design and realization of mathematical operations in FPGA circuits. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/830

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Soukup, Luděk. “Návrh a realizace matematických operací v obvodech FPGA: Design and realization of mathematical operations in FPGA circuits.” 2019. Thesis, Brno University of Technology. Accessed August 12, 2020. http://hdl.handle.net/11012/830.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Soukup, Luděk. “Návrh a realizace matematických operací v obvodech FPGA: Design and realization of mathematical operations in FPGA circuits.” 2019. Web. 12 Aug 2020.

Vancouver:

Soukup L. Návrh a realizace matematických operací v obvodech FPGA: Design and realization of mathematical operations in FPGA circuits. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/11012/830.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soukup L. Návrh a realizace matematických operací v obvodech FPGA: Design and realization of mathematical operations in FPGA circuits. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/830

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

27. Sýkora, Michal. Implementace modulární aritmetiky do obvodů FPGA a ASIC: Implementation of modular arithmetic in FPGAs and ASICs.

Degree: 2019, Brno University of Technology

 This thesis is focused on analysis, design and implementation of modular arithmetic in FPGAs and ASICs. Its main objective is to create a C++/SystemC library,… (more)

Subjects/Keywords: ASIC; FPGA; Modulárna aritmetika; Modulárne násobenie; Montgomeryho redukcia; SystemC; ASIC; FPGA; Modular arithmetic; Modular multiplication; Montgomery reduction; SystemC

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APA (6th Edition):

Sýkora, M. (2019). Implementace modulární aritmetiky do obvodů FPGA a ASIC: Implementation of modular arithmetic in FPGAs and ASICs. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/41548

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sýkora, Michal. “Implementace modulární aritmetiky do obvodů FPGA a ASIC: Implementation of modular arithmetic in FPGAs and ASICs.” 2019. Thesis, Brno University of Technology. Accessed August 12, 2020. http://hdl.handle.net/11012/41548.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sýkora, Michal. “Implementace modulární aritmetiky do obvodů FPGA a ASIC: Implementation of modular arithmetic in FPGAs and ASICs.” 2019. Web. 12 Aug 2020.

Vancouver:

Sýkora M. Implementace modulární aritmetiky do obvodů FPGA a ASIC: Implementation of modular arithmetic in FPGAs and ASICs. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 12]. Available from: http://hdl.handle.net/11012/41548.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sýkora M. Implementace modulární aritmetiky do obvodů FPGA a ASIC: Implementation of modular arithmetic in FPGAs and ASICs. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/41548

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

28. Perumalla, Anvesh Kumar. A Genetic Algorithm for ASIC Floorplanning.

Degree: MSEE, Electrical Engineering, 2016, Wright State University

 Semiconductor integrated circuits (ICs) have become key components in almost everyaspect of our daily lives. From simple home appliances to extremely sophisticatedaerospace systems, we have… (more)

Subjects/Keywords: Electrical Engineering; ASIC; Floorplan; Genetic Algorithm; Simulated Evolution; SoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Perumalla, A. K. (2016). A Genetic Algorithm for ASIC Floorplanning. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006

Chicago Manual of Style (16th Edition):

Perumalla, Anvesh Kumar. “A Genetic Algorithm for ASIC Floorplanning.” 2016. Masters Thesis, Wright State University. Accessed August 12, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.

MLA Handbook (7th Edition):

Perumalla, Anvesh Kumar. “A Genetic Algorithm for ASIC Floorplanning.” 2016. Web. 12 Aug 2020.

Vancouver:

Perumalla AK. A Genetic Algorithm for ASIC Floorplanning. [Internet] [Masters thesis]. Wright State University; 2016. [cited 2020 Aug 12]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.

Council of Science Editors:

Perumalla AK. A Genetic Algorithm for ASIC Floorplanning. [Masters Thesis]. Wright State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006


The Ohio State University

29. Hupe, Ryan Craig. Investigating the Performance of the Interferometric Trigger for Future Flights of the Antarctic Impulsive Transient Antenna.

Degree: PhD, Physics, 2015, The Ohio State University

 One of the primary unanswered questions in the field of astrophysics is the source of high-energy cosmic rays. Decades of searching by many different experiments… (more)

Subjects/Keywords: Physics; ANITA, trigger, interoferometry, digitization, FPGA, design, calibration, firmware, ASIC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hupe, R. C. (2015). Investigating the Performance of the Interferometric Trigger for Future Flights of the Antarctic Impulsive Transient Antenna. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1448982588

Chicago Manual of Style (16th Edition):

Hupe, Ryan Craig. “Investigating the Performance of the Interferometric Trigger for Future Flights of the Antarctic Impulsive Transient Antenna.” 2015. Doctoral Dissertation, The Ohio State University. Accessed August 12, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1448982588.

MLA Handbook (7th Edition):

Hupe, Ryan Craig. “Investigating the Performance of the Interferometric Trigger for Future Flights of the Antarctic Impulsive Transient Antenna.” 2015. Web. 12 Aug 2020.

Vancouver:

Hupe RC. Investigating the Performance of the Interferometric Trigger for Future Flights of the Antarctic Impulsive Transient Antenna. [Internet] [Doctoral dissertation]. The Ohio State University; 2015. [cited 2020 Aug 12]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1448982588.

Council of Science Editors:

Hupe RC. Investigating the Performance of the Interferometric Trigger for Future Flights of the Antarctic Impulsive Transient Antenna. [Doctoral Dissertation]. The Ohio State University; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1448982588


UCLA

30. Toriyama, Yuta. High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes.

Degree: Electrical Engineering, 2016, UCLA

 Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the… (more)

Subjects/Keywords: Electrical engineering; ASIC; Digital Architecture; LDPC; Min-Max; Nonbinary; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Toriyama, Y. (2016). High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/42c0g73r

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Toriyama, Yuta. “High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes.” 2016. Thesis, UCLA. Accessed August 12, 2020. http://www.escholarship.org/uc/item/42c0g73r.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Toriyama, Yuta. “High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes.” 2016. Web. 12 Aug 2020.

Vancouver:

Toriyama Y. High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes. [Internet] [Thesis]. UCLA; 2016. [cited 2020 Aug 12]. Available from: http://www.escholarship.org/uc/item/42c0g73r.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Toriyama Y. High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes. [Thesis]. UCLA; 2016. Available from: http://www.escholarship.org/uc/item/42c0g73r

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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