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You searched for subject:(ADPLL). Showing records 1 – 29 of 29 total matches.

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Delft University of Technology

1. Effendrik, P. (author). Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS.

Degree: 2011, Delft University of Technology

WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access. To anticipate… (more)

Subjects/Keywords: WiMAX; ADPLL; CMOS

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APA (6th Edition):

Effendrik, P. (. (2011). Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:0957ee62-0d58-4a93-b5ad-40cad54b895d

Chicago Manual of Style (16th Edition):

Effendrik, P (author). “Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS.” 2011. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:0957ee62-0d58-4a93-b5ad-40cad54b895d.

MLA Handbook (7th Edition):

Effendrik, P (author). “Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS.” 2011. Web. 19 Oct 2020.

Vancouver:

Effendrik P(. Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:0957ee62-0d58-4a93-b5ad-40cad54b895d.

Council of Science Editors:

Effendrik P(. Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:0957ee62-0d58-4a93-b5ad-40cad54b895d

2. Butt, Hadiyah. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It… (more)

Subjects/Keywords: ADPLL; PLL; DCO; TDC

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APA (6th Edition):

Butt, H. (2013). Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Butt, Hadiyah. “Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band.” 2013. Thesis, Linköping UniversityLinköping University. Accessed October 19, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Butt, Hadiyah. “Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band.” 2013. Web. 19 Oct 2020.

Vancouver:

Butt H. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Butt H. Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

3. Jiang, W. (author). ADPLL Design for WiMAX.

Degree: 2011, Delft University of Technology

The frequency synthesizer, which functions as a local oscillator, is a critical block in the transceiver. It needs to meet very stringent specifications and consume… (more)

Subjects/Keywords: ADPLL; WiMAX; Frequency synthesizer; CMOS

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APA (6th Edition):

Jiang, W. (. (2011). ADPLL Design for WiMAX. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:abe493a5-49d3-4822-8186-9ed1b15d3eaf

Chicago Manual of Style (16th Edition):

Jiang, W (author). “ADPLL Design for WiMAX.” 2011. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:abe493a5-49d3-4822-8186-9ed1b15d3eaf.

MLA Handbook (7th Edition):

Jiang, W (author). “ADPLL Design for WiMAX.” 2011. Web. 19 Oct 2020.

Vancouver:

Jiang W(. ADPLL Design for WiMAX. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:abe493a5-49d3-4822-8186-9ed1b15d3eaf.

Council of Science Editors:

Jiang W(. ADPLL Design for WiMAX. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:abe493a5-49d3-4822-8186-9ed1b15d3eaf


Delft University of Technology

4. Wu, L. (author). An Ultra-Low-Power ADPLL for BLE Applications.

Degree: 2014, Delft University of Technology

In recent years, wireless personal area network (WPAN) applications have triggered the needs for low-cost and low-power PLLs which also provide good performance. All-digital phased-locked… (more)

Subjects/Keywords: frequency synthesizer; ADPLL; ultra-low-power; DTC

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APA (6th Edition):

Wu, L. (. (2014). An Ultra-Low-Power ADPLL for BLE Applications. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c2897087-1a85-4cbe-918b-12b0c0837792

Chicago Manual of Style (16th Edition):

Wu, L (author). “An Ultra-Low-Power ADPLL for BLE Applications.” 2014. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:c2897087-1a85-4cbe-918b-12b0c0837792.

MLA Handbook (7th Edition):

Wu, L (author). “An Ultra-Low-Power ADPLL for BLE Applications.” 2014. Web. 19 Oct 2020.

Vancouver:

Wu L(. An Ultra-Low-Power ADPLL for BLE Applications. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:c2897087-1a85-4cbe-918b-12b0c0837792.

Council of Science Editors:

Wu L(. An Ultra-Low-Power ADPLL for BLE Applications. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:c2897087-1a85-4cbe-918b-12b0c0837792


University of Michigan

5. Park, Young Min. A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 As CMOS processes scale and digital gates become faster, it is practical to implement precisely-timed digital circuits switching in the GHz range. As a result,… (more)

Subjects/Keywords: All-digital; Synthesis; ADPLL; TDC; UWB Transmitter; Electrical Engineering; Engineering

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APA (6th Edition):

Park, Y. M. (2011). A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86573

Chicago Manual of Style (16th Edition):

Park, Young Min. “A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits.” 2011. Doctoral Dissertation, University of Michigan. Accessed October 19, 2020. http://hdl.handle.net/2027.42/86573.

MLA Handbook (7th Edition):

Park, Young Min. “A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits.” 2011. Web. 19 Oct 2020.

Vancouver:

Park YM. A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2027.42/86573.

Council of Science Editors:

Park YM. A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86573


NSYSU

6. Huang, Chi-Chung. Design and Implementation of A Personal Gateway for Body Area Networks.

Degree: PhD, Electrical Engineering, 2009, NSYSU

 In this thesis, we propose a personal gateway for wireless body area network(WBAN). By using wireless communication and a proper WBAN topology, patientsâ physiological signal… (more)

Subjects/Keywords: personal gateway; body area networks; mixed-voltage; BPM; ZigBee; ADPLL

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APA (6th Edition):

Huang, C. (2009). Design and Implementation of A Personal Gateway for Body Area Networks. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-150819

Chicago Manual of Style (16th Edition):

Huang, Chi-Chung. “Design and Implementation of A Personal Gateway for Body Area Networks.” 2009. Doctoral Dissertation, NSYSU. Accessed October 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-150819.

MLA Handbook (7th Edition):

Huang, Chi-Chung. “Design and Implementation of A Personal Gateway for Body Area Networks.” 2009. Web. 19 Oct 2020.

Vancouver:

Huang C. Design and Implementation of A Personal Gateway for Body Area Networks. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2020 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-150819.

Council of Science Editors:

Huang C. Design and Implementation of A Personal Gateway for Body Area Networks. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-150819

7. Wali, Naveen. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The… (more)

Subjects/Keywords: ADPLL; TDC; DPLL; PLL

…Block diagram of TDC based ADPLL [8]. . . . . . . . . . . . . . . Block diagram of… …accumulator based ADPLL [8]. . . . . . . . . . . Block diagram time-to-digital converter… …Oscillator DPLL Digital Phase Locked Loop ADPLL All-Digital Phase Locked Loop TDC Time to Digital… …have been linked only to all-digital phase locked loop (ADPLL) where, a TDC acts as… …in the ADPLL system. The constraint with the above said architectures is that it consumes… 

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APA (6th Edition):

Wali, N. (2013). Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wali, Naveen. “Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band.” 2013. Thesis, Linköping UniversityLinköping University. Accessed October 19, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wali, Naveen. “Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band.” 2013. Web. 19 Oct 2020.

Vancouver:

Wali N. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wali N. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

8. Chen, P. (author). DTC and TDC IC Design for Ultra-Low-Power ADPLL.

Degree: 2014, Delft University of Technology

The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the… (more)

Subjects/Keywords: Fractional-N ADPLL; DTC; ultra-low-power; sigma-delta TDC

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APA (6th Edition):

Chen, P. (. (2014). DTC and TDC IC Design for Ultra-Low-Power ADPLL. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2ec38599-4844-4979-ad0f-b4380b2f84df

Chicago Manual of Style (16th Edition):

Chen, P (author). “DTC and TDC IC Design for Ultra-Low-Power ADPLL.” 2014. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:2ec38599-4844-4979-ad0f-b4380b2f84df.

MLA Handbook (7th Edition):

Chen, P (author). “DTC and TDC IC Design for Ultra-Low-Power ADPLL.” 2014. Web. 19 Oct 2020.

Vancouver:

Chen P(. DTC and TDC IC Design for Ultra-Low-Power ADPLL. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:2ec38599-4844-4979-ad0f-b4380b2f84df.

Council of Science Editors:

Chen P(. DTC and TDC IC Design for Ultra-Low-Power ADPLL. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:2ec38599-4844-4979-ad0f-b4380b2f84df


California State University – Sacramento

9. Ahmad, Riaz. Design of a digitally controlled oscillator for an integrated circuit phase-locked loop.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 The project focuses on the design and simulation of a digitally-controlled oscillator (DCO) for an all-digital phase-locked loop in a 180nm CMOS process. A ring… (more)

Subjects/Keywords: Oscillator for ADPLL; Differential ring oscillator; Cross-coupled inverters

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APA (6th Edition):

Ahmad, R. (2017). Design of a digitally controlled oscillator for an integrated circuit phase-locked loop. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/194217

Chicago Manual of Style (16th Edition):

Ahmad, Riaz. “Design of a digitally controlled oscillator for an integrated circuit phase-locked loop.” 2017. Masters Thesis, California State University – Sacramento. Accessed October 19, 2020. http://hdl.handle.net/10211.3/194217.

MLA Handbook (7th Edition):

Ahmad, Riaz. “Design of a digitally controlled oscillator for an integrated circuit phase-locked loop.” 2017. Web. 19 Oct 2020.

Vancouver:

Ahmad R. Design of a digitally controlled oscillator for an integrated circuit phase-locked loop. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/10211.3/194217.

Council of Science Editors:

Ahmad R. Design of a digitally controlled oscillator for an integrated circuit phase-locked loop. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/194217


University of Vermont

10. Jiang, Bo. A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration.

Degree: PhD, Electrical Engineering, 2016, University of Vermont

  The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide… (more)

Subjects/Keywords: ADPLL; Jitter; On chip measurement; Phase noise; PLL; Wide band; Electrical and Electronics

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APA (6th Edition):

Jiang, B. (2016). A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration. (Doctoral Dissertation). University of Vermont. Retrieved from https://scholarworks.uvm.edu/graddis/562

Chicago Manual of Style (16th Edition):

Jiang, Bo. “A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration.” 2016. Doctoral Dissertation, University of Vermont. Accessed October 19, 2020. https://scholarworks.uvm.edu/graddis/562.

MLA Handbook (7th Edition):

Jiang, Bo. “A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration.” 2016. Web. 19 Oct 2020.

Vancouver:

Jiang B. A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration. [Internet] [Doctoral dissertation]. University of Vermont; 2016. [cited 2020 Oct 19]. Available from: https://scholarworks.uvm.edu/graddis/562.

Council of Science Editors:

Jiang B. A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration. [Doctoral Dissertation]. University of Vermont; 2016. Available from: https://scholarworks.uvm.edu/graddis/562


Northeastern University

11. Zhao, Jun. A low power CMOS design of an all digital phase locked loop.

Degree: PhD, Department of Electrical and Computer Engineering, 2011, Northeastern University

 This dissertation presents a proposed all digital phase locked loop and a digitally controlled oscillator with low power consumption for fractional-N frequency synthesis applications. The… (more)

Subjects/Keywords: eElectrical engineering; digital phase locked loop; ADPLL; PLL; Electrical and Computer Engineering

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APA (6th Edition):

Zhao, J. (2011). A low power CMOS design of an all digital phase locked loop. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20001051

Chicago Manual of Style (16th Edition):

Zhao, Jun. “A low power CMOS design of an all digital phase locked loop.” 2011. Doctoral Dissertation, Northeastern University. Accessed October 19, 2020. http://hdl.handle.net/2047/d20001051.

MLA Handbook (7th Edition):

Zhao, Jun. “A low power CMOS design of an all digital phase locked loop.” 2011. Web. 19 Oct 2020.

Vancouver:

Zhao J. A low power CMOS design of an all digital phase locked loop. [Internet] [Doctoral dissertation]. Northeastern University; 2011. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2047/d20001051.

Council of Science Editors:

Zhao J. A low power CMOS design of an all digital phase locked loop. [Doctoral Dissertation]. Northeastern University; 2011. Available from: http://hdl.handle.net/2047/d20001051

12. Staszewski, Robert Bogdan. Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications.

Degree: 2016, University of Texas at Dallas

Traditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applications have almost exclusively employed the use of a charge-pump phase-locked loop (PLL), which… (more)

Subjects/Keywords: All-digital phase-locked loop; ADPLL; Time-to-digital converter (TDC); Digitally controlled oscillator (DCO)

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APA (6th Edition):

Staszewski, R. B. (2016). Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications. (Thesis). University of Texas at Dallas. Retrieved from http://hdl.handle.net/10197/8119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Staszewski, Robert Bogdan. “Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications.” 2016. Thesis, University of Texas at Dallas. Accessed October 19, 2020. http://hdl.handle.net/10197/8119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Staszewski, Robert Bogdan. “Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications.” 2016. Web. 19 Oct 2020.

Vancouver:

Staszewski RB. Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications. [Internet] [Thesis]. University of Texas at Dallas; 2016. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/10197/8119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Staszewski RB. Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications. [Thesis]. University of Texas at Dallas; 2016. Available from: http://hdl.handle.net/10197/8119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

13. Gao, Y. (author). Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs.

Degree: 2014, Delft University of Technology

This thesis deals with the design of a duty-cycled, fractional-N and low-noise Phase Locked Loop (PLL) used for Ultra-Wideband applications in 40 nm process. This… (more)

Subjects/Keywords: UWB; Duty-Cycled; ADPLL; DCPLL; Instantaneous Start-up; LC DCO; Fractional-N; DTC

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APA (6th Edition):

Gao, Y. (. (2014). Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:38e6e348-6f77-4867-989a-7814dab12f6b

Chicago Manual of Style (16th Edition):

Gao, Y (author). “Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs.” 2014. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:38e6e348-6f77-4867-989a-7814dab12f6b.

MLA Handbook (7th Edition):

Gao, Y (author). “Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs.” 2014. Web. 19 Oct 2020.

Vancouver:

Gao Y(. Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:38e6e348-6f77-4867-989a-7814dab12f6b.

Council of Science Editors:

Gao Y(. Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:38e6e348-6f77-4867-989a-7814dab12f6b


University of Illinois – Urbana-Champaign

14. Liu, Yubo. Design of all digital phase-locked loop in serial link communication.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 The speed of wireline and wireless communication systems has been increasing aggressively over the past decade. Multi-GHz clocks are in demand more than ever. In… (more)

Subjects/Keywords: phase-locked loop (PLL); serial link; all digital phase-locked loop (ADPLL); jitter

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APA (6th Edition):

Liu, Y. (2015). Design of all digital phase-locked loop in serial link communication. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed October 19, 2020. http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Web. 19 Oct 2020.

Vancouver:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Tavakol, A. (author). Digitally Controlled Oscillator for WiMAX in 40 nm.

Degree: 2012, Delft University of Technology

This document describes the design and implementation of a digitally controlled oscillator for WiMAX application in 40 nm. This system contains two main blocks of… (more)

Subjects/Keywords: DCO; frequency divider; WiMAX; LC Oscillator; ADPLL

…low-area frequency synthesizers in new technologies. ADPLL has the minimum number of RF… …The tuning voltage is the ADPLL are the frequency command word, FCW and the reference clock… …DCO topologies which can be used in an ADPLL. LC oscillators are among the most used… …oscillator is based on a series of specifications which is dictated by the ADPLL design. Tuning… …specifications which determine the performance of the DCO and the ADPLL. Specific requirements on each… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tavakol, A. (. (2012). Digitally Controlled Oscillator for WiMAX in 40 nm. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6f4a55cc-e40e-40c8-af0f-8222a72c43b4

Chicago Manual of Style (16th Edition):

Tavakol, A (author). “Digitally Controlled Oscillator for WiMAX in 40 nm.” 2012. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:6f4a55cc-e40e-40c8-af0f-8222a72c43b4.

MLA Handbook (7th Edition):

Tavakol, A (author). “Digitally Controlled Oscillator for WiMAX in 40 nm.” 2012. Web. 19 Oct 2020.

Vancouver:

Tavakol A(. Digitally Controlled Oscillator for WiMAX in 40 nm. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:6f4a55cc-e40e-40c8-af0f-8222a72c43b4.

Council of Science Editors:

Tavakol A(. Digitally Controlled Oscillator for WiMAX in 40 nm. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:6f4a55cc-e40e-40c8-af0f-8222a72c43b4

16. Wang, B. (author). Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL.

Degree: Master of Microelectronics, 2014, Delft University of Technology

Master of Microelectronics

Microelectronics & Computer Engineering

Electrical Engineering, Mathematics and Computer Science

Advisors/Committee Members: Staszewski, R.B. (mentor), Liu, Y.H. (mentor).

Subjects/Keywords: DTC; TDC; ADPLL; ultra-low power; CMOS

…6 7 8 2 System analysis of ADPLL 9 2-1 Frequency Synthesis Techniques –PLL… …State of Art All-digital PLL (ADPLL) . . . . . . . . . . . . . . . . . . . 10 12 2… …1-3 Challenge for ultra-low power ADPLL . . . . . . . . . . . . . . . . . . . 17 2-2… …Phase prediction DTC assisted snapshot TDC based ADPLL . . . . . . . . . . . 17 2-2-1… …Principle of phase-prediction ADPLL . . . . . . . . . . . . . . . . . . . . 18 3 Digital-to-Time… 

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APA (6th Edition):

Wang, B. (. (2014). Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d

Chicago Manual of Style (16th Edition):

Wang, B (author). “Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL.” 2014. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d.

MLA Handbook (7th Edition):

Wang, B (author). “Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL.” 2014. Web. 19 Oct 2020.

Vancouver:

Wang B(. Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d.

Council of Science Editors:

Wang B(. Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:ea10ff84-a257-4712-b9ab-8cdf13b23a4d

17. Chillara, V.K. (author). An Ultra-Low-Power ADPLL for WPAN Applications.

Degree: 2013, Delft University of Technology

RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios.… (more)

Subjects/Keywords: ADPLL; frequency synthesis; ultra-low-power

…2-1-1 Divider-less ADPLL . . . . . . . . . . . . . . . . . . . . . 2-1-2 Divider-based… …ADPLL . . . . . . . . . . . . . . . . . . . . 2-1-3 Comparison of divider-less and divider… …operating frequency of TDC . . . . . . . . . 2-5 DTC-assisted snapshot TDC based ADPLL… …1 ADPLL test plan . . . . . . . . . . . . . . . . 5-2 Measurement results… …Architecture of divider-less ADPLL. . . . . . . . . . . . . . . . . . . . Architecture of divider… 

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APA (6th Edition):

Chillara, V. K. (. (2013). An Ultra-Low-Power ADPLL for WPAN Applications. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:53911767-cf72-4441-885b-d3dc6b7949d8

Chicago Manual of Style (16th Edition):

Chillara, V K (author). “An Ultra-Low-Power ADPLL for WPAN Applications.” 2013. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:53911767-cf72-4441-885b-d3dc6b7949d8.

MLA Handbook (7th Edition):

Chillara, V K (author). “An Ultra-Low-Power ADPLL for WPAN Applications.” 2013. Web. 19 Oct 2020.

Vancouver:

Chillara VK(. An Ultra-Low-Power ADPLL for WPAN Applications. [Internet] [Masters thesis]. Delft University of Technology; 2013. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:53911767-cf72-4441-885b-d3dc6b7949d8.

Council of Science Editors:

Chillara VK(. An Ultra-Low-Power ADPLL for WPAN Applications. [Masters Thesis]. Delft University of Technology; 2013. Available from: http://resolver.tudelft.nl/uuid:53911767-cf72-4441-885b-d3dc6b7949d8

18. Muppala, Prashanth. High-frequency wide-range all digital phase locked loop in 90nm CMOS.

Degree: MSEgr, Electrical Engineering, 2011, Wright State University

 This thesis presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) in 90 nm CMOS process with 1.2 V power supply. It… (more)

Subjects/Keywords: Electrical Engineering; all digital phase locked loop; ADPLL; CMOS

…x28;ADPLL) are discussed in [7, 8]. A new DCO implemented in 0.13µm, 1.2V… …fast settling time ADPLL with tuning word estimating and presetting is specified in [11… …x5D;. Most of the research on ADPLL‟s [12-17] so far discusses about narrow range… …the ADPLL. In this thesis, an all-digital phase locked loop with a high-resolution and wide… …used to obtain the frequency and phase acquisition. The components of the ADPLL design: DCO… 

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APA (6th Edition):

Muppala, P. (2011). High-frequency wide-range all digital phase locked loop in 90nm CMOS. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049

Chicago Manual of Style (16th Edition):

Muppala, Prashanth. “High-frequency wide-range all digital phase locked loop in 90nm CMOS.” 2011. Masters Thesis, Wright State University. Accessed October 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.

MLA Handbook (7th Edition):

Muppala, Prashanth. “High-frequency wide-range all digital phase locked loop in 90nm CMOS.” 2011. Web. 19 Oct 2020.

Vancouver:

Muppala P. High-frequency wide-range all digital phase locked loop in 90nm CMOS. [Internet] [Masters thesis]. Wright State University; 2011. [cited 2020 Oct 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.

Council of Science Editors:

Muppala P. High-frequency wide-range all digital phase locked loop in 90nm CMOS. [Masters Thesis]. Wright State University; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049


Carnegie Mellon University

19. Hussein, Ahmed. Design Techniques for Low Spur Wide Tuning All-Digital Millimeter-Wave Frequency Synthesizers.

Degree: 2017, Carnegie Mellon University

Subjects/Keywords: ADPLL; DCO; Frequency Synthesizers; mm-wave; mm-wave dividers; TDC

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APA (6th Edition):

Hussein, A. (2017). Design Techniques for Low Spur Wide Tuning All-Digital Millimeter-Wave Frequency Synthesizers. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/801

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hussein, Ahmed. “Design Techniques for Low Spur Wide Tuning All-Digital Millimeter-Wave Frequency Synthesizers.” 2017. Thesis, Carnegie Mellon University. Accessed October 19, 2020. http://repository.cmu.edu/dissertations/801.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hussein, Ahmed. “Design Techniques for Low Spur Wide Tuning All-Digital Millimeter-Wave Frequency Synthesizers.” 2017. Web. 19 Oct 2020.

Vancouver:

Hussein A. Design Techniques for Low Spur Wide Tuning All-Digital Millimeter-Wave Frequency Synthesizers. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2020 Oct 19]. Available from: http://repository.cmu.edu/dissertations/801.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hussein A. Design Techniques for Low Spur Wide Tuning All-Digital Millimeter-Wave Frequency Synthesizers. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/801

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

20. Chen, Xing. Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems.

Degree: PhD, Electrical Engineering, 2019, University of Michigan

 Advances in ultra-low power (ULP) circuit technologies are expanding the IoT applications in our daily life. However, wireless connectivity, small form factor and long lifetime… (more)

Subjects/Keywords: Phase noise and jitter; frequency synthesizer; ADPLL; ultra low power wireless integrated system; ring oscillator based bluetooth low energy transmitter; crystal-less wireless edge node; Electrical Engineering; Engineering

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APA (6th Edition):

Chen, X. (2019). Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/153420

Chicago Manual of Style (16th Edition):

Chen, Xing. “Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems.” 2019. Doctoral Dissertation, University of Michigan. Accessed October 19, 2020. http://hdl.handle.net/2027.42/153420.

MLA Handbook (7th Edition):

Chen, Xing. “Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems.” 2019. Web. 19 Oct 2020.

Vancouver:

Chen X. Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2019. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2027.42/153420.

Council of Science Editors:

Chen X. Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems. [Doctoral Dissertation]. University of Michigan; 2019. Available from: http://hdl.handle.net/2027.42/153420

21. Vlachogiannakis, G. (author). Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications.

Degree: 2013, Delft University of Technology

Despite their high degree of reconfigurability and friendliness to technology scaling, traditional ADPLL-based frequency synthesizers tend to come at the price of increased power consumption… (more)

Subjects/Keywords: ADPLL; phase pPrediction; DTC-TDC; fractional-N; frequency synthesizer

ADPLL . . . . . . . . 4.11.2 LC-DCO ADPLL… …element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main ADPLL… …phase signals in an accumulator-based ADPLL with F CW = 2.25 under lock… …Frequency domain model of an ADPLL. . . . . . . . . . . . . . . . . . . . Magnitude response of… …contributions of TDC and DCO in an ADPLL with bad quality DCO and typical TDC and the closed loop… 

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APA (6th Edition):

Vlachogiannakis, G. (. (2013). Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6e721958-0a75-4b2d-b4f3-94cb91f8080e

Chicago Manual of Style (16th Edition):

Vlachogiannakis, G (author). “Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications.” 2013. Masters Thesis, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:6e721958-0a75-4b2d-b4f3-94cb91f8080e.

MLA Handbook (7th Edition):

Vlachogiannakis, G (author). “Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications.” 2013. Web. 19 Oct 2020.

Vancouver:

Vlachogiannakis G(. Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications. [Internet] [Masters thesis]. Delft University of Technology; 2013. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:6e721958-0a75-4b2d-b4f3-94cb91f8080e.

Council of Science Editors:

Vlachogiannakis G(. Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications. [Masters Thesis]. Delft University of Technology; 2013. Available from: http://resolver.tudelft.nl/uuid:6e721958-0a75-4b2d-b4f3-94cb91f8080e


Northeastern University

22. Kim, Moon Seok. 0.18μm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter.

Degree: MS, Department of Electrical and Computer Engineering, 2012, Northeastern University

 The objective of the thesis is to design a novel ADPLL with local passive interpolation time-to-digital (LPI-TDC) based on a tri-state inverter for clock synchronization,… (more)

Subjects/Keywords: ADPLL; Local Passive Interpolation TDC; Low Power; LPI-TDC; Time-to-Digital Converter (TDC); Tri-state Inverter; Computer Engineering; Digital Circuits; Electrical and Computer Engineering; Engineering

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APA (6th Edition):

Kim, M. S. (2012). 0.18μm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002892

Chicago Manual of Style (16th Edition):

Kim, Moon Seok. “0.18μm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter.” 2012. Masters Thesis, Northeastern University. Accessed October 19, 2020. http://hdl.handle.net/2047/d20002892.

MLA Handbook (7th Edition):

Kim, Moon Seok. “0.18μm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter.” 2012. Web. 19 Oct 2020.

Vancouver:

Kim MS. 0.18μm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter. [Internet] [Masters thesis]. Northeastern University; 2012. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2047/d20002892.

Council of Science Editors:

Kim MS. 0.18μm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter. [Masters Thesis]. Northeastern University; 2012. Available from: http://hdl.handle.net/2047/d20002892


KTH

23. Shen, Jue. Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop.

Degree: Information and Communication Technology (ICT), 2011, KTH

  With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system… (more)

Subjects/Keywords: All Digital Phase-Locked Loop (ADPLL); Quantization Step; Non-linear quantization effect; Non-linear PLL noise model; Phase Noise; Matlab Modeling; Verilog Behavior Modeling.

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APA (6th Edition):

Shen, J. (2011). Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shen, Jue. “Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop.” 2011. Thesis, KTH. Accessed October 19, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shen, Jue. “Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop.” 2011. Web. 19 Oct 2020.

Vancouver:

Shen J. Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop. [Internet] [Thesis]. KTH; 2011. [cited 2020 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shen J. Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop. [Thesis]. KTH; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. -1648-3847. Design of a 3 GHz fine resolution LC DCO.

Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin

 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12… (more)

Subjects/Keywords: Digitally controlled oscillator (DCO); All-digital-PLL (ADPLL); LC oscillator; Fine tuning

…22 Chapter 5 DCO Simulation in Ideal ADPLL Model… …27 5.1. ADPLL Architecture… …35 Appendix B Verilog-A Model of ADPLL… …25 Figure 5.1: Architecture of an ADPLL… …27 Figure 5.2: Frequency domain model of ADPLL… 

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APA (6th Edition):

-1648-3847. (2017). Design of a 3 GHz fine resolution LC DCO. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/62896

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-1648-3847. “Design of a 3 GHz fine resolution LC DCO.” 2017. Masters Thesis, University of Texas – Austin. Accessed October 19, 2020. http://hdl.handle.net/2152/62896.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-1648-3847. “Design of a 3 GHz fine resolution LC DCO.” 2017. Web. 19 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-1648-3847. Design of a 3 GHz fine resolution LC DCO. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2152/62896.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-1648-3847. Design of a 3 GHz fine resolution LC DCO. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/62896

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

25. Bouloc, Jeremy. Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique : On IGBT's fault diagnosis in voltage source inverter-fed induction motor drives -analysis of electrical signals-.

Degree: Docteur es, Micro et nanoélectronique, 2012, Aix Marseille Université

Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est… (more)

Subjects/Keywords: Microscopie à force atomique (AFM); Capteur de force haute fréquence; Résolution atomique; Microscopie à force atomique sans contact à modulation de fréquence (FM-AFM); Boucle à verrouillage de phase (PLL); Atomic force microscopy (AFM); Atomic resolution; Non-contact frequency modulated atomic force microscopy (FM-AFM); Phase locked loop (PLL); All digital phase locked loop (ADPLL); High frequency force sensor

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APA (6th Edition):

Bouloc, J. (2012). Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique : On IGBT's fault diagnosis in voltage source inverter-fed induction motor drives -analysis of electrical signals-. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2012AIXM4307

Chicago Manual of Style (16th Edition):

Bouloc, Jeremy. “Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique : On IGBT's fault diagnosis in voltage source inverter-fed induction motor drives -analysis of electrical signals-.” 2012. Doctoral Dissertation, Aix Marseille Université. Accessed October 19, 2020. http://www.theses.fr/2012AIXM4307.

MLA Handbook (7th Edition):

Bouloc, Jeremy. “Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique : On IGBT's fault diagnosis in voltage source inverter-fed induction motor drives -analysis of electrical signals-.” 2012. Web. 19 Oct 2020.

Vancouver:

Bouloc J. Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique : On IGBT's fault diagnosis in voltage source inverter-fed induction motor drives -analysis of electrical signals-. [Internet] [Doctoral dissertation]. Aix Marseille Université 2012. [cited 2020 Oct 19]. Available from: http://www.theses.fr/2012AIXM4307.

Council of Science Editors:

Bouloc J. Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique : On IGBT's fault diagnosis in voltage source inverter-fed induction motor drives -analysis of electrical signals-. [Doctoral Dissertation]. Aix Marseille Université 2012. Available from: http://www.theses.fr/2012AIXM4307


Delft University of Technology

26. Shahmohammadi, M. RF CMOS Oscillators for Cellular Applications.

Degree: 2016, Delft University of Technology

Subjects/Keywords: RF; oscillator; 1/f noise up-conversion; impulse sensitivity function; wide tuning range; Colpitts oscillator; coupled oscillators; all-digital phase-locked loop (ADPLL)

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APA (6th Edition):

Shahmohammadi, M. (2016). RF CMOS Oscillators for Cellular Applications. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; 10.4233/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:isbn:978-94-6233-477-9 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114

Chicago Manual of Style (16th Edition):

Shahmohammadi, M. “RF CMOS Oscillators for Cellular Applications.” 2016. Doctoral Dissertation, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; 10.4233/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:isbn:978-94-6233-477-9 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114.

MLA Handbook (7th Edition):

Shahmohammadi, M. “RF CMOS Oscillators for Cellular Applications.” 2016. Web. 19 Oct 2020.

Vancouver:

Shahmohammadi M. RF CMOS Oscillators for Cellular Applications. [Internet] [Doctoral dissertation]. Delft University of Technology; 2016. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; 10.4233/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:isbn:978-94-6233-477-9 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114.

Council of Science Editors:

Shahmohammadi M. RF CMOS Oscillators for Cellular Applications. [Doctoral Dissertation]. Delft University of Technology; 2016. Available from: http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; 10.4233/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; urn:isbn:978-94-6233-477-9 ; urn:NBN:nl:ui:24-uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114 ; http://resolver.tudelft.nl/uuid:f7b33aaa-6b21-4f8a-9fd7-022bec55f114


Texas A&M University

27. Turker, Didem 1981-. Frequency Synthesis in Wireless and Wireline Systems.

Degree: PhD, Electrical Engineering, 2010, Texas A&M University

 First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is… (more)

Subjects/Keywords: wireline systems; wireless systems; TDC; DCO; DPLL; ADPLL; digital PLL; all digital PLL; delay model; DCVSL; VCO; ring oscillator; prescaler; dual modulus prescaler; frequency divider; PLL; frequency synthesizer; Frequency Synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Turker, D. 1. (2010). Frequency Synthesis in Wireless and Wireline Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148459

Chicago Manual of Style (16th Edition):

Turker, Didem 1981-. “Frequency Synthesis in Wireless and Wireline Systems.” 2010. Doctoral Dissertation, Texas A&M University. Accessed October 19, 2020. http://hdl.handle.net/1969.1/148459.

MLA Handbook (7th Edition):

Turker, Didem 1981-. “Frequency Synthesis in Wireless and Wireline Systems.” 2010. Web. 19 Oct 2020.

Vancouver:

Turker D1. Frequency Synthesis in Wireless and Wireline Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2010. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/1969.1/148459.

Council of Science Editors:

Turker D1. Frequency Synthesis in Wireless and Wireline Systems. [Doctoral Dissertation]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/148459


Delft University of Technology

28. Babaie, M. Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications.

Degree: 2016, Delft University of Technology

Subjects/Keywords: RF; mm-wave; transmitter; oscillator; class-F; phase noise; impulse sensitivity function; switched-mode power amplifier; Class-E/F; transformer; Bluetooth Low Energy; Low voltage; low power; all-digital phase-locked loop (ADPLL)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Babaie, M. (2016). Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 10.4233/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:isbn:978-94-6233-305-5 ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f

Chicago Manual of Style (16th Edition):

Babaie, M. “Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications.” 2016. Doctoral Dissertation, Delft University of Technology. Accessed October 19, 2020. http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 10.4233/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:isbn:978-94-6233-305-5 ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f.

MLA Handbook (7th Edition):

Babaie, M. “Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications.” 2016. Web. 19 Oct 2020.

Vancouver:

Babaie M. Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications. [Internet] [Doctoral dissertation]. Delft University of Technology; 2016. [cited 2020 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 10.4233/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:isbn:978-94-6233-305-5 ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f.

Council of Science Editors:

Babaie M. Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications. [Doctoral Dissertation]. Delft University of Technology; 2016. Available from: http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; 10.4233/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; urn:isbn:978-94-6233-305-5 ; urn:NBN:nl:ui:24-uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f ; http://resolver.tudelft.nl/uuid:456a2f0e-529d-4bd8-91e0-4dba4f623f0f


University of Illinois – Urbana-Champaign

29. Elkholy, Ahmed Mostafa Mohamed Attia. Digital enhancement techniques for fractional-N frequency synthesizers.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing… (more)

Subjects/Keywords: Phase-locked loops (PLLs); digital PLL; All-digital phase locked loop (ADPLL); fractional-N; Fractional divider, frequency synthesizer; Wide bandwidth; Bang-bang phase detector (BBPD); Digital-to-time converter (DTC); Least-mean square (LMS); Time-to-digtial converter (TDC); Time amplifier; Jitter; Digitally controlled oscillator (DCO); Frequency multiplier; Frequency tracking; Impulse sensitivity function (ISF); Injection locking; Multiplying injection-locked oscillator (MILO); Phase domain response (PDR); Phase noise; Pulse; Reference spur; Root mean square (rms) jitter; Sub-harmonic locking; Sub-sampling (SS)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Elkholy, A. M. M. A. (2016). Digital enhancement techniques for fractional-N frequency synthesizers. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95573

Chicago Manual of Style (16th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 19, 2020. http://hdl.handle.net/2142/95573.

MLA Handbook (7th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Web. 19 Oct 2020.

Vancouver:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 19]. Available from: http://hdl.handle.net/2142/95573.

Council of Science Editors:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95573

.