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You searched for subject:(ADC). Showing records 1 – 30 of 478 total matches.

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Oregon State University

1. Muhlestein, Jason, Russell. Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques.

Degree: PhD, 2017, Oregon State University

 The internet-of-things is a growing market segment which is based on an array of portable communication devices with high power efficiency. Advanced semiconductor technology can… (more)

Subjects/Keywords: ADC

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APA (6th Edition):

Muhlestein, Jason, R. (2017). Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/61673

Chicago Manual of Style (16th Edition):

Muhlestein, Jason, Russell. “Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques.” 2017. Doctoral Dissertation, Oregon State University. Accessed June 04, 2020. http://hdl.handle.net/1957/61673.

MLA Handbook (7th Edition):

Muhlestein, Jason, Russell. “Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques.” 2017. Web. 04 Jun 2020.

Vancouver:

Muhlestein, Jason R. Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques. [Internet] [Doctoral dissertation]. Oregon State University; 2017. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1957/61673.

Council of Science Editors:

Muhlestein, Jason R. Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques. [Doctoral Dissertation]. Oregon State University; 2017. Available from: http://hdl.handle.net/1957/61673


University of Texas – Austin

2. Gulati, Paridhi. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.

Degree: MSin Engineering, Electrical and Computer Engineering, 2016, University of Texas – Austin

 A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the… (more)

Subjects/Keywords: Pipelined ADC; SAR ADC

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APA (6th Edition):

Gulati, P. (2016). A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65964

Chicago Manual of Style (16th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Masters Thesis, University of Texas – Austin. Accessed June 04, 2020. http://hdl.handle.net/2152/65964.

MLA Handbook (7th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Web. 04 Jun 2020.

Vancouver:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/2152/65964.

Council of Science Editors:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/65964


Dalhousie University

3. Ceekala, Mithun. STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2013, Dalhousie University

 This thesis presents a new architecture of stochastic Analog-to-Digital converter (ADC). A standard Stochastic ADC uses comparator random offset as the trip point while all… (more)

Subjects/Keywords: stochastic ADC

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APA (6th Edition):

Ceekala, M. (2013). STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/21911

Chicago Manual of Style (16th Edition):

Ceekala, Mithun. “STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS.” 2013. Masters Thesis, Dalhousie University. Accessed June 04, 2020. http://hdl.handle.net/10222/21911.

MLA Handbook (7th Edition):

Ceekala, Mithun. “STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS.” 2013. Web. 04 Jun 2020.

Vancouver:

Ceekala M. STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS. [Internet] [Masters thesis]. Dalhousie University; 2013. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/10222/21911.

Council of Science Editors:

Ceekala M. STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS. [Masters Thesis]. Dalhousie University; 2013. Available from: http://hdl.handle.net/10222/21911


NSYSU

4. Fan, Gang-Jin. A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison.

Degree: Master, Electrical Engineering, 2005, NSYSU

 A 3.3V 8-bit 250MSample/sec synchronous comparison current-mode analog to digital converter is described in this thesis. The high bits and low bits are realized by… (more)

Subjects/Keywords: ADC

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APA (6th Edition):

Fan, G. (2005). A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fan, Gang-Jin. “A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison.” 2005. Thesis, NSYSU. Accessed June 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fan, Gang-Jin. “A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison.” 2005. Web. 04 Jun 2020.

Vancouver:

Fan G. A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison. [Internet] [Thesis]. NSYSU; 2005. [cited 2020 Jun 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fan G. A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison. [Thesis]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

5. Jamalizavareh, Shiva. Jitter Suppression Techniques for High Speed Communication Systems.

Degree: PhD, Electrical Engineering, 2019, University of Minnesota

 The drive towards fast and robust communication has resulted in an increased focus on high frequency analog and digital transceivers. One of the major challenges… (more)

Subjects/Keywords: ADC; Jitter

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APA (6th Edition):

Jamalizavareh, S. (2019). Jitter Suppression Techniques for High Speed Communication Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/211765

Chicago Manual of Style (16th Edition):

Jamalizavareh, Shiva. “Jitter Suppression Techniques for High Speed Communication Systems.” 2019. Doctoral Dissertation, University of Minnesota. Accessed June 04, 2020. http://hdl.handle.net/11299/211765.

MLA Handbook (7th Edition):

Jamalizavareh, Shiva. “Jitter Suppression Techniques for High Speed Communication Systems.” 2019. Web. 04 Jun 2020.

Vancouver:

Jamalizavareh S. Jitter Suppression Techniques for High Speed Communication Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2019. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/11299/211765.

Council of Science Editors:

Jamalizavareh S. Jitter Suppression Techniques for High Speed Communication Systems. [Doctoral Dissertation]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/211765


Linköping University

6. Radhakrishnan, Venkataraman. Design of a low power analog to digital converter in a 130nmCMOS technology.

Degree: Electronics System, 2011, Linköping University

  Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the… (more)

Subjects/Keywords: pipeline ADC; fully differential; CLS ADC

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APA (6th Edition):

Radhakrishnan, V. (2011). Design of a low power analog to digital converter in a 130nmCMOS technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Radhakrishnan, Venkataraman. “Design of a low power analog to digital converter in a 130nmCMOS technology.” 2011. Thesis, Linköping University. Accessed June 04, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Radhakrishnan, Venkataraman. “Design of a low power analog to digital converter in a 130nmCMOS technology.” 2011. Web. 04 Jun 2020.

Vancouver:

Radhakrishnan V. Design of a low power analog to digital converter in a 130nmCMOS technology. [Internet] [Thesis]. Linköping University; 2011. [cited 2020 Jun 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Radhakrishnan V. Design of a low power analog to digital converter in a 130nmCMOS technology. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Crasso, Anthony. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.

Degree: MS, 2013, Worcester Polytechnic Institute

 In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized… (more)

Subjects/Keywords: Calibration; Flash; ADC

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APA (6th Edition):

Crasso, A. (2013). Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Crasso, Anthony. “Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.” 2013. Thesis, Worcester Polytechnic Institute. Accessed June 04, 2020. etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Crasso, Anthony. “Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.” 2013. Web. 04 Jun 2020.

Vancouver:

Crasso A. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. [Internet] [Thesis]. Worcester Polytechnic Institute; 2013. [cited 2020 Jun 04]. Available from: etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Crasso A. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. [Thesis]. Worcester Polytechnic Institute; 2013. Available from: etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

8. Gianelli, Christopher David. One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Florida

 This work considers the problem of estimating the parameters of a noisy signal which has been quantized to one-bit via a time-varying thresholding operation. This… (more)

Subjects/Keywords: adc  – engineering  – estimation

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APA (6th Edition):

Gianelli, C. D. (2019). One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation. (Doctoral Dissertation). University of Florida. Retrieved from https://ufdc.ufl.edu/UFE0055945

Chicago Manual of Style (16th Edition):

Gianelli, Christopher David. “One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation.” 2019. Doctoral Dissertation, University of Florida. Accessed June 04, 2020. https://ufdc.ufl.edu/UFE0055945.

MLA Handbook (7th Edition):

Gianelli, Christopher David. “One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation.” 2019. Web. 04 Jun 2020.

Vancouver:

Gianelli CD. One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation. [Internet] [Doctoral dissertation]. University of Florida; 2019. [cited 2020 Jun 04]. Available from: https://ufdc.ufl.edu/UFE0055945.

Council of Science Editors:

Gianelli CD. One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation. [Doctoral Dissertation]. University of Florida; 2019. Available from: https://ufdc.ufl.edu/UFE0055945

9. Thangamani, Manivannan. The design of an all-digital VCO-based ADC in a 65nm CMOS technology.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  This thesis explores the study and design of an all-digital VCO-based ADC in a 65 nm CMOS technology. As the CMOS process enters the… (more)

Subjects/Keywords: VCO-ADC; VCO-bsaed ADC; Time-based quantizer; all-digital ADC; VCO; FDC

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APA (6th Edition):

Thangamani, M. (2014). The design of an all-digital VCO-based ADC in a 65nm CMOS technology. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Thangamani, Manivannan. “The design of an all-digital VCO-based ADC in a 65nm CMOS technology.” 2014. Thesis, Linköping UniversityLinköping University. Accessed June 04, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Thangamani, Manivannan. “The design of an all-digital VCO-based ADC in a 65nm CMOS technology.” 2014. Web. 04 Jun 2020.

Vancouver:

Thangamani M. The design of an all-digital VCO-based ADC in a 65nm CMOS technology. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2020 Jun 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Thangamani M. The design of an all-digital VCO-based ADC in a 65nm CMOS technology. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

10. Ravikumar, Dinesh. Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB.

Degree: MS, Electrical and Computer Engineering, 2016, The Ohio State University

 High Speed Analog to Digital Converters (ADCs) are being widely used in digital communication, digital oscilloscopes and fast data acquisition systems since they provide the… (more)

Subjects/Keywords: Electrical Engineering; ADC Modeling

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APA (6th Edition):

Ravikumar, D. (2016). Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228

Chicago Manual of Style (16th Edition):

Ravikumar, Dinesh. “Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB.” 2016. Masters Thesis, The Ohio State University. Accessed June 04, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228.

MLA Handbook (7th Edition):

Ravikumar, Dinesh. “Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB.” 2016. Web. 04 Jun 2020.

Vancouver:

Ravikumar D. Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB. [Internet] [Masters thesis]. The Ohio State University; 2016. [cited 2020 Jun 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228.

Council of Science Editors:

Ravikumar D. Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB. [Masters Thesis]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228


Oregon State University

11. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC(more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed June 04, 2020. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 04 Jun 2020.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


Delft University of Technology

12. Hu, W. A 9-bit 33MHz Hybrid SAR Single-slope ADC :.

Degree: 2015, Delft University of Technology

 In this work a 9-bit, 33MHz hybrid SAR single-slope ADC for element-level digitization in 2D ultrasound transducer arrays is presented. This hybrid architecture consists of… (more)

Subjects/Keywords: ADC; Hybrid SAR single-slope

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APA (6th Edition):

Hu, W. (2015). A 9-bit 33MHz Hybrid SAR Single-slope ADC :. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842

Chicago Manual of Style (16th Edition):

Hu, W. “A 9-bit 33MHz Hybrid SAR Single-slope ADC :.” 2015. Masters Thesis, Delft University of Technology. Accessed June 04, 2020. http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842.

MLA Handbook (7th Edition):

Hu, W. “A 9-bit 33MHz Hybrid SAR Single-slope ADC :.” 2015. Web. 04 Jun 2020.

Vancouver:

Hu W. A 9-bit 33MHz Hybrid SAR Single-slope ADC :. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Jun 04]. Available from: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842.

Council of Science Editors:

Hu W. A 9-bit 33MHz Hybrid SAR Single-slope ADC :. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842


University of Texas – Austin

13. Bayoumy, Mostafa Elsayed. A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash… (more)

Subjects/Keywords: Pipeline ADC; 1.5-bit stage

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APA (6th Edition):

Bayoumy, M. E. (2013). A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24010

Chicago Manual of Style (16th Edition):

Bayoumy, Mostafa Elsayed. “A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage.” 2013. Masters Thesis, University of Texas – Austin. Accessed June 04, 2020. http://hdl.handle.net/2152/24010.

MLA Handbook (7th Edition):

Bayoumy, Mostafa Elsayed. “A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage.” 2013. Web. 04 Jun 2020.

Vancouver:

Bayoumy ME. A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/2152/24010.

Council of Science Editors:

Bayoumy ME. A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24010

14. Hallström, Claes. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor… (more)

Subjects/Keywords: adc; sar; digital calibration

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APA (6th Edition):

Hallström, C. (2013). Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hallström, Claes. “Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.” 2013. Thesis, Linköping UniversityLinköping University. Accessed June 04, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hallström, Claes. “Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.” 2013. Web. 04 Jun 2020.

Vancouver:

Hallström C. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Jun 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hallström C. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

15. Thouta, Santosh Kumar. Mono to stereo synthesizer implementation on FPGA.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 The main objective of this project is to design a synthesizer that can convert mono audio signal into stereo audio signal. This synthesizer proves to… (more)

Subjects/Keywords: DSP; ADC; Digital filter

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APA (6th Edition):

Thouta, S. K. (2011). Mono to stereo synthesizer implementation on FPGA. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/991

Chicago Manual of Style (16th Edition):

Thouta, Santosh Kumar. “Mono to stereo synthesizer implementation on FPGA.” 2011. Masters Thesis, California State University – Sacramento. Accessed June 04, 2020. http://hdl.handle.net/10211.9/991.

MLA Handbook (7th Edition):

Thouta, Santosh Kumar. “Mono to stereo synthesizer implementation on FPGA.” 2011. Web. 04 Jun 2020.

Vancouver:

Thouta SK. Mono to stereo synthesizer implementation on FPGA. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/10211.9/991.

Council of Science Editors:

Thouta SK. Mono to stereo synthesizer implementation on FPGA. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/991


The Ohio State University

16. Ng, Sheung Yan. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.

Degree: PhD, Electrical and Computer Engineering, 2009, The Ohio State University

  This dissertation focuses on the circuit design techniques for an asynchronous sigma delta Analog to Digital Converter (ADC). The key advantage of this ADC(more)

Subjects/Keywords: Electrical Engineering; asynchronous sigma delta ADC; synchronous sigma delta ADC

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APA (6th Edition):

Ng, S. Y. (2009). A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906

Chicago Manual of Style (16th Edition):

Ng, Sheung Yan. “A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.” 2009. Doctoral Dissertation, The Ohio State University. Accessed June 04, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

MLA Handbook (7th Edition):

Ng, Sheung Yan. “A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.” 2009. Web. 04 Jun 2020.

Vancouver:

Ng SY. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. [Internet] [Doctoral dissertation]. The Ohio State University; 2009. [cited 2020 Jun 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

Council of Science Editors:

Ng SY. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. [Doctoral Dissertation]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906


Wright State University

17. Wang, Mingzhen. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.

Degree: PhD, Engineering PhD, 2007, Wright State University

 Wang, Mingzhen, Ph.D, Engineering Ph.D Program, Department of Electrical Engineering, Wright State University, 2007. High-Speed Low-Voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip With… (more)

Subjects/Keywords: tmp_output; ADC; flash ADC; CLK; CMOS; Outputs; comparator

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APA (6th Edition):

Wang, M. (2007). High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482

Chicago Manual of Style (16th Edition):

Wang, Mingzhen. “High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.” 2007. Doctoral Dissertation, Wright State University. Accessed June 04, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

MLA Handbook (7th Edition):

Wang, Mingzhen. “High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.” 2007. Web. 04 Jun 2020.

Vancouver:

Wang M. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. [Internet] [Doctoral dissertation]. Wright State University; 2007. [cited 2020 Jun 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

Council of Science Editors:

Wang M. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. [Doctoral Dissertation]. Wright State University; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482


NSYSU

18. Huang, Hui-wen. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage… (more)

Subjects/Keywords: Dynamic Comparator; Bootstrapped Switch; Successive Approximation ADC; Binary Search ADC

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APA (6th Edition):

Huang, H. (2015). A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed June 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 04 Jun 2020.

Vancouver:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Jun 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

19. Castro Scorsi, Rafael. A data interface for ultra high speed ADC integrated circuits.

Degree: MSin Engineering, Electrical and Computer Engineering, 2011, University of Texas – Austin

 Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in… (more)

Subjects/Keywords: High speed ADC; 10 gigabit ethernet; ADC interface

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APA (6th Edition):

Castro Scorsi, R. (2011). A data interface for ultra high speed ADC integrated circuits. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/22769

Chicago Manual of Style (16th Edition):

Castro Scorsi, Rafael. “A data interface for ultra high speed ADC integrated circuits.” 2011. Masters Thesis, University of Texas – Austin. Accessed June 04, 2020. http://hdl.handle.net/2152/22769.

MLA Handbook (7th Edition):

Castro Scorsi, Rafael. “A data interface for ultra high speed ADC integrated circuits.” 2011. Web. 04 Jun 2020.

Vancouver:

Castro Scorsi R. A data interface for ultra high speed ADC integrated circuits. [Internet] [Masters thesis]. University of Texas – Austin; 2011. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/2152/22769.

Council of Science Editors:

Castro Scorsi R. A data interface for ultra high speed ADC integrated circuits. [Masters Thesis]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/22769


Duke University

20. Aleksanyan, Arnak. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .

Degree: 2011, Duke University

  Many medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto… (more)

Subjects/Keywords: Electrical Engineering; delta-sigma adc; low power sensor; programmable adc; rfid

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APA (6th Edition):

Aleksanyan, A. (2011). Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/3956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aleksanyan, Arnak. “Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .” 2011. Thesis, Duke University. Accessed June 04, 2020. http://hdl.handle.net/10161/3956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aleksanyan, Arnak. “Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .” 2011. Web. 04 Jun 2020.

Vancouver:

Aleksanyan A. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . [Internet] [Thesis]. Duke University; 2011. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/10161/3956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aleksanyan A. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . [Thesis]. Duke University; 2011. Available from: http://hdl.handle.net/10161/3956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed June 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 04 Jun 2020.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Jun 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

22. Briseno Vidrios, Carlos Jesus. Design of Highly Efficient Analog-To-Digital Converters.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 The demand of higher data rates in communication systems is reflected in the constant evolution of communication standards. LTE-A and WiFi 802.11ac promote the use… (more)

Subjects/Keywords: Analog-to-digital conversion; continuous-time sigma-delta modulators; High resolution ADCs; Low power ADC; MASH ADC architectures; cascaded ADC; Subranging ADC; multi bit quantizer; current buffer; current mode; pipeline

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APA (6th Edition):

Briseno Vidrios, C. J. (2016). Design of Highly Efficient Analog-To-Digital Converters. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156918

Chicago Manual of Style (16th Edition):

Briseno Vidrios, Carlos Jesus. “Design of Highly Efficient Analog-To-Digital Converters.” 2016. Doctoral Dissertation, Texas A&M University. Accessed June 04, 2020. http://hdl.handle.net/1969.1/156918.

MLA Handbook (7th Edition):

Briseno Vidrios, Carlos Jesus. “Design of Highly Efficient Analog-To-Digital Converters.” 2016. Web. 04 Jun 2020.

Vancouver:

Briseno Vidrios CJ. Design of Highly Efficient Analog-To-Digital Converters. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1969.1/156918.

Council of Science Editors:

Briseno Vidrios CJ. Design of Highly Efficient Analog-To-Digital Converters. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156918


Texas A&M University

23. Rashidi, Negar. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 The demand for higher data rates in receivers with carrier aggregation (CA) such as LTE, increases the efforts to integrate large number of wireless services… (more)

Subjects/Keywords: Sigma Delta Modulator; ADC; Jitter tolerant; calibration

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APA (6th Edition):

Rashidi, N. (2016). Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161272

Chicago Manual of Style (16th Edition):

Rashidi, Negar. “Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator.” 2016. Doctoral Dissertation, Texas A&M University. Accessed June 04, 2020. http://hdl.handle.net/1969.1/161272.

MLA Handbook (7th Edition):

Rashidi, Negar. “Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator.” 2016. Web. 04 Jun 2020.

Vancouver:

Rashidi N. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1969.1/161272.

Council of Science Editors:

Rashidi N. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/161272


University of Alberta

24. Larocque, Matthew. ADC and T2 response to radiotherapy in a human tumour xenograft model.

Degree: PhD, Department of Physics, 2010, University of Alberta

 A 9.4 T magnetic resonance imaging (MRI) system was used to evaluate the response of a human tumour xenograft model to radiation therapy. The apparent… (more)

Subjects/Keywords: tumour response; radiotherapy; T2; ADC; xenograft

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APA (6th Edition):

Larocque, M. (2010). ADC and T2 response to radiotherapy in a human tumour xenograft model. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/8c97kq49n

Chicago Manual of Style (16th Edition):

Larocque, Matthew. “ADC and T2 response to radiotherapy in a human tumour xenograft model.” 2010. Doctoral Dissertation, University of Alberta. Accessed June 04, 2020. https://era.library.ualberta.ca/files/8c97kq49n.

MLA Handbook (7th Edition):

Larocque, Matthew. “ADC and T2 response to radiotherapy in a human tumour xenograft model.” 2010. Web. 04 Jun 2020.

Vancouver:

Larocque M. ADC and T2 response to radiotherapy in a human tumour xenograft model. [Internet] [Doctoral dissertation]. University of Alberta; 2010. [cited 2020 Jun 04]. Available from: https://era.library.ualberta.ca/files/8c97kq49n.

Council of Science Editors:

Larocque M. ADC and T2 response to radiotherapy in a human tumour xenograft model. [Doctoral Dissertation]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/8c97kq49n


Oregon State University

25. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed June 04, 2020. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 04 Jun 2020.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709


The Ohio State University

26. Sivakumar, Balasubramanian. A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control.

Degree: MS, Electrical and Computer Engineering, 2008, The Ohio State University

  As communications and data processing equipments are being pushed to higher speeds and into the digital domain, it becomes necessary that they are complemented… (more)

Subjects/Keywords: Electrical Engineering; ADC; Subranging; Digital Control

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APA (6th Edition):

Sivakumar, B. (2008). A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191

Chicago Manual of Style (16th Edition):

Sivakumar, Balasubramanian. “A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control.” 2008. Masters Thesis, The Ohio State University. Accessed June 04, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.

MLA Handbook (7th Edition):

Sivakumar, Balasubramanian. “A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control.” 2008. Web. 04 Jun 2020.

Vancouver:

Sivakumar B. A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control. [Internet] [Masters thesis]. The Ohio State University; 2008. [cited 2020 Jun 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.

Council of Science Editors:

Sivakumar B. A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control. [Masters Thesis]. The Ohio State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191


University of Akron

27. Karnati, Nikhil Reddy. A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs.

Degree: MSin Engineering, Electrical Engineering, 2011, University of Akron

 The current thesis presents the design and implementation of a power-efficient poly-phase decimation filter for Sigma-delta ADCs. A cascade of Cascaded-Integrator Comb (CIC) filter and… (more)

Subjects/Keywords: Electrical Engineering; Sigma-delta ADC; decimation filter

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APA (6th Edition):

Karnati, N. R. (2011). A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811

Chicago Manual of Style (16th Edition):

Karnati, Nikhil Reddy. “A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs.” 2011. Masters Thesis, University of Akron. Accessed June 04, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811.

MLA Handbook (7th Edition):

Karnati, Nikhil Reddy. “A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs.” 2011. Web. 04 Jun 2020.

Vancouver:

Karnati NR. A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs. [Internet] [Masters thesis]. University of Akron; 2011. [cited 2020 Jun 04]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811.

Council of Science Editors:

Karnati NR. A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs. [Masters Thesis]. University of Akron; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811

28. Tasaki, Akiko. Differential Diagnosis of Uterine Smooth Muscle Tumors using Diffusion-Weighted Imaging : Correlations with the Apparent Diffusion Coefficient and Cell Density : 子宮平滑筋腫瘍におけるDWIの有用性 : ADCと細胞密度との相関について.

Degree: 博士(医学), 2015, Niigata University / 新潟大学

学位の種類: 博士(医学). 報告番号: 甲第3973号. 学位記番号: 新大院博(医)甲第619号. 学位授与年月日: 平成27年3月23日

Abdominal Imaging. Article first published online: 21 December 2014.

Purpose: To investigate the utility of the apparent… (more)

Subjects/Keywords: Leiomyoma; Leiomyosarcoma; DWI/ADC; Correlation; Cell density

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APA (6th Edition):

Tasaki, A. (2015). Differential Diagnosis of Uterine Smooth Muscle Tumors using Diffusion-Weighted Imaging : Correlations with the Apparent Diffusion Coefficient and Cell Density : 子宮平滑筋腫瘍におけるDWIの有用性 : ADCと細胞密度との相関について. (Thesis). Niigata University / 新潟大学. Retrieved from http://hdl.handle.net/10191/32257

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tasaki, Akiko. “Differential Diagnosis of Uterine Smooth Muscle Tumors using Diffusion-Weighted Imaging : Correlations with the Apparent Diffusion Coefficient and Cell Density : 子宮平滑筋腫瘍におけるDWIの有用性 : ADCと細胞密度との相関について.” 2015. Thesis, Niigata University / 新潟大学. Accessed June 04, 2020. http://hdl.handle.net/10191/32257.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tasaki, Akiko. “Differential Diagnosis of Uterine Smooth Muscle Tumors using Diffusion-Weighted Imaging : Correlations with the Apparent Diffusion Coefficient and Cell Density : 子宮平滑筋腫瘍におけるDWIの有用性 : ADCと細胞密度との相関について.” 2015. Web. 04 Jun 2020.

Vancouver:

Tasaki A. Differential Diagnosis of Uterine Smooth Muscle Tumors using Diffusion-Weighted Imaging : Correlations with the Apparent Diffusion Coefficient and Cell Density : 子宮平滑筋腫瘍におけるDWIの有用性 : ADCと細胞密度との相関について. [Internet] [Thesis]. Niigata University / 新潟大学; 2015. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/10191/32257.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tasaki A. Differential Diagnosis of Uterine Smooth Muscle Tumors using Diffusion-Weighted Imaging : Correlations with the Apparent Diffusion Coefficient and Cell Density : 子宮平滑筋腫瘍におけるDWIの有用性 : ADCと細胞密度との相関について. [Thesis]. Niigata University / 新潟大学; 2015. Available from: http://hdl.handle.net/10191/32257

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

29. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed June 04, 2020. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 04 Jun 2020.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


Oregon State University

30. Prabha, Praveen. Design techniques for VCO based digital sensor readout circuits.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design… (more)

Subjects/Keywords: VCO based ADC; Voltage-controlled oscillators

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prabha, P. (2014). Design techniques for VCO based digital sensor readout circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/46796

Chicago Manual of Style (16th Edition):

Prabha, Praveen. “Design techniques for VCO based digital sensor readout circuits.” 2014. Masters Thesis, Oregon State University. Accessed June 04, 2020. http://hdl.handle.net/1957/46796.

MLA Handbook (7th Edition):

Prabha, Praveen. “Design techniques for VCO based digital sensor readout circuits.” 2014. Web. 04 Jun 2020.

Vancouver:

Prabha P. Design techniques for VCO based digital sensor readout circuits. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2020 Jun 04]. Available from: http://hdl.handle.net/1957/46796.

Council of Science Editors:

Prabha P. Design techniques for VCO based digital sensor readout circuits. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46796

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