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You searched for subject:(6T SRAM). Showing records 1 – 6 of 6 total matches.

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Wright State University

1. Keerthi, Rajasekhar. STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY.

Degree: MSEgr, Electrical Engineering, 2007, Wright State University

 The transistor mismatch can be described as two closely placed identical transistors have important differences in their electrical parameters as threshold voltage, body factor and… (more)

Subjects/Keywords: sram; 7T SRAM; 6T SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Keerthi, R. (2007). STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920

Chicago Manual of Style (16th Edition):

Keerthi, Rajasekhar. “STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY.” 2007. Masters Thesis, Wright State University. Accessed October 16, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920.

MLA Handbook (7th Edition):

Keerthi, Rajasekhar. “STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY.” 2007. Web. 16 Oct 2019.

Vancouver:

Keerthi R. STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY. [Internet] [Masters thesis]. Wright State University; 2007. [cited 2019 Oct 16]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920.

Council of Science Editors:

Keerthi R. STABILITY AND STATIC NOISE MARGIN ANALYSIS OF STATIC RANDOM ACCESS MEMORY. [Masters Thesis]. Wright State University; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1195600920


Linköping University

2. Yeknami, Ali Fazli. Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology.

Degree: Electrical Engineering, 2008, Linköping University

  This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache application. The objectives are to reduce power consumption through scaling the supply… (more)

Subjects/Keywords: SRAM; traditional 6T; asymmetric 6T; memory; SNM; cell; Electronics; Elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeknami, A. F. (2008). Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeknami, Ali Fazli. “Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology.” 2008. Thesis, Linköping University. Accessed October 16, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeknami, Ali Fazli. “Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology.” 2008. Web. 16 Oct 2019.

Vancouver:

Yeknami AF. Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology. [Internet] [Thesis]. Linköping University; 2008. [cited 2019 Oct 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeknami AF. Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology. [Thesis]. Linköping University; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

3. Mookerjea, Saurabh Amitabha. BAND-TO-BAND TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER LOGIC AND MEMORY APPLICATIONS: DESIGN,FABRICATION AND CHARACTERIZATION.

Degree: PhD, Electrical Engineering, 2010, Penn State University

 Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric… (more)

Subjects/Keywords: MILLER CAPACITANCE; HETERO-JUNCTION; HOMO-JUNCTION; TFET; 6T SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mookerjea, S. A. (2010). BAND-TO-BAND TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER LOGIC AND MEMORY APPLICATIONS: DESIGN,FABRICATION AND CHARACTERIZATION. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/11324

Chicago Manual of Style (16th Edition):

Mookerjea, Saurabh Amitabha. “BAND-TO-BAND TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER LOGIC AND MEMORY APPLICATIONS: DESIGN,FABRICATION AND CHARACTERIZATION.” 2010. Doctoral Dissertation, Penn State University. Accessed October 16, 2019. https://etda.libraries.psu.edu/catalog/11324.

MLA Handbook (7th Edition):

Mookerjea, Saurabh Amitabha. “BAND-TO-BAND TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER LOGIC AND MEMORY APPLICATIONS: DESIGN,FABRICATION AND CHARACTERIZATION.” 2010. Web. 16 Oct 2019.

Vancouver:

Mookerjea SA. BAND-TO-BAND TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER LOGIC AND MEMORY APPLICATIONS: DESIGN,FABRICATION AND CHARACTERIZATION. [Internet] [Doctoral dissertation]. Penn State University; 2010. [cited 2019 Oct 16]. Available from: https://etda.libraries.psu.edu/catalog/11324.

Council of Science Editors:

Mookerjea SA. BAND-TO-BAND TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER LOGIC AND MEMORY APPLICATIONS: DESIGN,FABRICATION AND CHARACTERIZATION. [Doctoral Dissertation]. Penn State University; 2010. Available from: https://etda.libraries.psu.edu/catalog/11324


University of Saskatchewan

4. Radhakrishnan, Govindakrishnan. Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology.

Degree: 2014, University of Saskatchewan

 Technology scaling of CMOS devices has made the integrated circuits vulnerable to single event radiation effects. Scaling of CMOS Static RAM (SRAM) has led to… (more)

Subjects/Keywords: Keyword 1; SEMU, Keyword 2; 6T SRAM; Keyword 3; SEU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Radhakrishnan, G. (2014). Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/ETD-2014-08-1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Radhakrishnan, Govindakrishnan. “Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology.” 2014. Thesis, University of Saskatchewan. Accessed October 16, 2019. http://hdl.handle.net/10388/ETD-2014-08-1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Radhakrishnan, Govindakrishnan. “Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology.” 2014. Web. 16 Oct 2019.

Vancouver:

Radhakrishnan G. Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology. [Internet] [Thesis]. University of Saskatchewan; 2014. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10388/ETD-2014-08-1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Radhakrishnan G. Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology. [Thesis]. University of Saskatchewan; 2014. Available from: http://hdl.handle.net/10388/ETD-2014-08-1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

5. [No author]. Design Techniques and Tradeoffs of FinFET SRAM Memories .

Degree: 2013, Washington State University

 Nine novel eight-transistor (8T) FinFET SRAM cell schemes using different shorted gate (SG) or low power (LP) FinFET configurations are studied and evaluated comprehensively in… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; 6T SRAM; 8T SRAM; FinFET; High Performance; Low Leakage Current; Near-Threshold Operation

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APA (6th Edition):

author], [. (2013). Design Techniques and Tradeoffs of FinFET SRAM Memories . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/4752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Design Techniques and Tradeoffs of FinFET SRAM Memories .” 2013. Thesis, Washington State University. Accessed October 16, 2019. http://hdl.handle.net/2376/4752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Design Techniques and Tradeoffs of FinFET SRAM Memories .” 2013. Web. 16 Oct 2019.

Vancouver:

author] [. Design Techniques and Tradeoffs of FinFET SRAM Memories . [Internet] [Thesis]. Washington State University; 2013. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/2376/4752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Design Techniques and Tradeoffs of FinFET SRAM Memories . [Thesis]. Washington State University; 2013. Available from: http://hdl.handle.net/2376/4752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Torrens Caldentey, Gabriel. Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas.

Degree: Departament de Física, 2012, Universitat de les Illes Balears

 Els efectes de la radiació en circuits electrònics es coneixen des dels inicis de la carrera espacial als anys 60, ja que fora de l’atmosfera… (more)

Subjects/Keywords: memorias, SRAM, 6T, 8T, CMOS, robustez, radiación, tolerancia, mitigación, soft error, single event upset, SEU, single event effect, SEE, SER, carga crítica, Qcrit, diseño, layout, partículas alfa, estabilidad, SNM, MBU, MCU; memories, SRAM, 6T, 8T, CMOS, robustness, radiation, tolerance, mitigation, soft error, single event upset, SEU, single event effect, SEE, SER, critical charge, Qcrit, design, layout, alpha particles, stability, SNM, MBU, MCU; memòries, SRAM, 6T, 8T, CMOS, robustesa, radiació, tolerància, mitigació, soft error, single event upset, SEU, single event effect, SEE, SER, càrrega crítica, Qcrit, disseny, layout, partícules alfa, estabilitat, SNM, MBU, MCU; Tecnología Electrónica; 53

…33 3.1.1.1. Escritura de una celda SRAM 6T… …35 3.1.1.2. Lectura de una celda SRAM 6T… …Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas… …21 2.2.5. Radiaciones causantes de SEUs en memorias SRAM a nivel de tierra… …29 MEMORIAS SRAM. ESTRUCTURA, FIABILIDAD, VARIABILIDAD E INTERACCIÓN CON LA RADIACIÓN… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Torrens Caldentey, G. (2012). Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas. (Thesis). Universitat de les Illes Balears. Retrieved from http://hdl.handle.net/10803/97291

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Torrens Caldentey, Gabriel. “Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas.” 2012. Thesis, Universitat de les Illes Balears. Accessed October 16, 2019. http://hdl.handle.net/10803/97291.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Torrens Caldentey, Gabriel. “Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas.” 2012. Web. 16 Oct 2019.

Vancouver:

Torrens Caldentey G. Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas. [Internet] [Thesis]. Universitat de les Illes Balears; 2012. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10803/97291.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Torrens Caldentey G. Estudio de eventos transitorios inducidos por radiación en memorias SRAM nanométricas. [Thesis]. Universitat de les Illes Balears; 2012. Available from: http://hdl.handle.net/10803/97291

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.