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You searched for subject:(45nm). Showing records 1 – 6 of 6 total matches.

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1. Aggrawal, Himanshu. High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization.

Degree: MS, Engineering, 2015, Rice University

 Last few decades have seen a puissant desire for fast communication links that has shaped the evolution of high-speed circuits and silicon- based technology. This… (more)

Subjects/Keywords: Track and hold Amplifier; Sampler; CMOS; 45nm; Directional Modulation; Secure Communication; Localization; Radar; Pulse

…3.10 Chip micrograph in 45nm. . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 34 34… …T/H) architecture with active cancellation, which is fabricated in IBM 45nm CMOS SOI… 

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APA (6th Edition):

Aggrawal, H. (2015). High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/87740

Chicago Manual of Style (16th Edition):

Aggrawal, Himanshu. “High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization.” 2015. Masters Thesis, Rice University. Accessed May 30, 2020. http://hdl.handle.net/1911/87740.

MLA Handbook (7th Edition):

Aggrawal, Himanshu. “High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization.” 2015. Web. 30 May 2020.

Vancouver:

Aggrawal H. High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization. [Internet] [Masters thesis]. Rice University; 2015. [cited 2020 May 30]. Available from: http://hdl.handle.net/1911/87740.

Council of Science Editors:

Aggrawal H. High-speed Track and Hold Amplifiers in CMOS for Enabling Pulse-based Direct Modulation, Secure Communication and Precision Localization. [Masters Thesis]. Rice University; 2015. Available from: http://hdl.handle.net/1911/87740


Indian Institute of Science

2. Ajayan, K R. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.

Degree: 2014, Indian Institute of Science

 Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As… (more)

Subjects/Keywords: Metal Oxide Semiconductors (MOS); Digital Integrated Circuits; Complementary Metal Oxide Semiconductors (CMOS); N-type Metal-Oxide Semiconductors (NMOS); P-type Metal-Oxide Semiconductors (PMOS); Metal Oxode Semiconductor Device Modeling; Look Up Table Model (LUT); Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET); MOSFET Models; BSIM Models; Variability Aware Device Modeling; Integrated Circuit Modeling; Circuit Design; 45nm Analog CMOS Technology; Electrical Communication Engineering

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APA (6th Edition):

Ajayan, K. R. (2014). Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Thesis, Indian Institute of Science. Accessed May 30, 2020. http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Web. 30 May 2020.

Vancouver:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2020 May 30]. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

3. Li, L. 45nm Extraction and verification flow with SPACE:.

Degree: 2009, Delft University of Technology

 As CMOS technology progresses to the 45nm generation and below, lots of changes are developed on material, process and structure, such as, metal gates, high-k… (more)

Subjects/Keywords: SPACE; 45nm model; extraction & verification

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APA (6th Edition):

Li, L. (2009). 45nm Extraction and verification flow with SPACE:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:d6e74f6e-ed5c-4641-ae0e-c50e0676e63a

Chicago Manual of Style (16th Edition):

Li, L. “45nm Extraction and verification flow with SPACE:.” 2009. Masters Thesis, Delft University of Technology. Accessed May 30, 2020. http://resolver.tudelft.nl/uuid:d6e74f6e-ed5c-4641-ae0e-c50e0676e63a.

MLA Handbook (7th Edition):

Li, L. “45nm Extraction and verification flow with SPACE:.” 2009. Web. 30 May 2020.

Vancouver:

Li L. 45nm Extraction and verification flow with SPACE:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 May 30]. Available from: http://resolver.tudelft.nl/uuid:d6e74f6e-ed5c-4641-ae0e-c50e0676e63a.

Council of Science Editors:

Li L. 45nm Extraction and verification flow with SPACE:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:d6e74f6e-ed5c-4641-ae0e-c50e0676e63a


University of Texas – Austin

4. Naganathan, Vignesh. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.

Degree: MSin Engineering, Electrical and Computer Engineering, 2015, University of Texas – Austin

 Binary adders form a major part in various arithmetic logical operation units including multipliers, dividers and digital signal processors. Parallel prefix adders represent a set… (more)

Subjects/Keywords: Parallel prefix adders; CMOS 32nm; CMOS 45nm

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APA (6th Edition):

Naganathan, V. (2015). A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32303

Chicago Manual of Style (16th Edition):

Naganathan, Vignesh. “A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.” 2015. Masters Thesis, University of Texas – Austin. Accessed May 30, 2020. http://hdl.handle.net/2152/32303.

MLA Handbook (7th Edition):

Naganathan, Vignesh. “A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology.” 2015. Web. 30 May 2020.

Vancouver:

Naganathan V. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. [Internet] [Masters thesis]. University of Texas – Austin; 2015. [cited 2020 May 30]. Available from: http://hdl.handle.net/2152/32303.

Council of Science Editors:

Naganathan V. A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology. [Masters Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32303


Delft University of Technology

5. Nigam, A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.

Degree: 2010, Delft University of Technology

 As we are moving toward nanometre technology, the variability in the circuit parameters and operating environment (Process, Voltage and Temperature (PVT)) are increasing, causing uncertainty… (more)

Subjects/Keywords: STA; SSTA; digital circuit; timing analysis; EDA; PVT; variation; Monte Carlo; 45nm; methodology; simulation; MODERN

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nigam, A. (2010). Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78

Chicago Manual of Style (16th Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Masters Thesis, Delft University of Technology. Accessed May 30, 2020. http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

MLA Handbook (7th Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Web. 30 May 2020.

Vancouver:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 May 30]. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

Council of Science Editors:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78


University of North Texas

6. Vadlmudi, Tripurasuparna. A nano-CMOS based universal voltage level converter for multi-VDD SoCs.

Degree: 2007, University of North Texas

 Power dissipation of integrated circuits is the most demanding issue for very large scale integration (VLSI) design engineers, especially for portable and mobile applications. Use… (more)

Subjects/Keywords: Level converter; power dissipation; reduction design; 90nm & 45nm technology; Electric current converters.; Metal oxide semiconductors, Complementary.; Integrated circuits  – Very large scale integration.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vadlmudi, T. (2007). A nano-CMOS based universal voltage level converter for multi-VDD SoCs. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc3602/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vadlmudi, Tripurasuparna. “A nano-CMOS based universal voltage level converter for multi-VDD SoCs.” 2007. Thesis, University of North Texas. Accessed May 30, 2020. https://digital.library.unt.edu/ark:/67531/metadc3602/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vadlmudi, Tripurasuparna. “A nano-CMOS based universal voltage level converter for multi-VDD SoCs.” 2007. Web. 30 May 2020.

Vancouver:

Vadlmudi T. A nano-CMOS based universal voltage level converter for multi-VDD SoCs. [Internet] [Thesis]. University of North Texas; 2007. [cited 2020 May 30]. Available from: https://digital.library.unt.edu/ark:/67531/metadc3602/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vadlmudi T. A nano-CMOS based universal voltage level converter for multi-VDD SoCs. [Thesis]. University of North Texas; 2007. Available from: https://digital.library.unt.edu/ark:/67531/metadc3602/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.