Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(4 2 counter). Showing records 1 – 3 of 3 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters

1. Varma, Nikhil Satheesh. Design and implementation of an approximate full adder and its use in FIR filters.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. To improve the speed and to reduce the complexity of the reduction tree a4:2 counter is introduced into the reduction tree. The reduction tree is designed using a bit-level optimized ILP problem which has the objective function to minimize the overall cost of the hardware used. For this purpose the layout design for a 4:2 counter has been developed and the cost function has been derived by comparing the complexity of the design against a standard FA design. The layout design for a 4:2 counter is implemented in a 65nm process using static CMOS logic style and DPL style. The average power consumption drawn from a 1V power supply, for the static CMOS design was found to be 16.8μWand for the DPL style it was 12.51μW. The worst case rise or fall time for the DPL logic was 350ps and for the static CMOS logic design it was found to be 260ps. The usage of the 4:2 counter in the reduction tree infused errors into the filter response, but it helped to reduce the number of pipeline stages and also to improve the speed of the partial product reduction.

Subjects/Keywords: FIR filters; bit-level optimization; 4:2 counter; static CMOS; DPL; 65nm process

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Varma, N. S. (2013). Design and implementation of an approximate full adder and its use in FIR filters. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varma, Nikhil Satheesh. “Design and implementation of an approximate full adder and its use in FIR filters.” 2013. Thesis, Linköping UniversityLinköping University. Accessed December 15, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varma, Nikhil Satheesh. “Design and implementation of an approximate full adder and its use in FIR filters.” 2013. Web. 15 Dec 2019.

Vancouver:

Varma NS. Design and implementation of an approximate full adder and its use in FIR filters. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2019 Dec 15]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varma NS. Design and implementation of an approximate full adder and its use in FIR filters. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Pretoria

2. Veale, Gerhardus Ignatius Potgieter. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC.

Degree: Electrical, Electronic and Computer Engineering, 2010, University of Pretoria

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. Advisors/Committee Members: Dr S Sinha (advisor).

Subjects/Keywords: Cml-to-cmos converter; Cml flicker noise; Fractional-n; Cmos pfd; Cml pfd; Cml 4-bit counter; Cml; Cml 2/3-prescaler; Ssb phase noise; Pulse-swallow counter; Low division; Programmable modulus accumulator; High voltage charge-pump; In-band phase noise; UCTD

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Veale, G. I. (2010). Low phase noise 2 GHz Fractional-N CMOS synthesizer IC. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/27921

Chicago Manual of Style (16th Edition):

Veale, Gerhardus Ignatius. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC.” 2010. Masters Thesis, University of Pretoria. Accessed December 15, 2019. http://hdl.handle.net/2263/27921.

MLA Handbook (7th Edition):

Veale, Gerhardus Ignatius. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC.” 2010. Web. 15 Dec 2019.

Vancouver:

Veale GI. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC. [Internet] [Masters thesis]. University of Pretoria; 2010. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2263/27921.

Council of Science Editors:

Veale GI. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC. [Masters Thesis]. University of Pretoria; 2010. Available from: http://hdl.handle.net/2263/27921


University of Pretoria

3. [No author]. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC .

Degree: 2010, University of Pretoria

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. Advisors/Committee Members: Dr S Sinha (advisor).

Subjects/Keywords: Cml-to-cmos converter; Cml flicker noise; Fractional-n; Cmos pfd; Cml pfd; Cml 4-bit counter; Cml; Cml 2/3-prescaler; Ssb phase noise; Pulse-swallow counter; Low division; Programmable modulus accumulator; High voltage charge-pump; In-band phase noise; UCTD

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2010). Low phase noise 2 GHz Fractional-N CMOS synthesizer IC . (Masters Thesis). University of Pretoria. Retrieved from http://upetd.up.ac.za/thesis/available/etd-09132010-162013/

Chicago Manual of Style (16th Edition):

author], [No. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC .” 2010. Masters Thesis, University of Pretoria. Accessed December 15, 2019. http://upetd.up.ac.za/thesis/available/etd-09132010-162013/.

MLA Handbook (7th Edition):

author], [No. “Low phase noise 2 GHz Fractional-N CMOS synthesizer IC .” 2010. Web. 15 Dec 2019.

Vancouver:

author] [. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC . [Internet] [Masters thesis]. University of Pretoria; 2010. [cited 2019 Dec 15]. Available from: http://upetd.up.ac.za/thesis/available/etd-09132010-162013/.

Council of Science Editors:

author] [. Low phase noise 2 GHz Fractional-N CMOS synthesizer IC . [Masters Thesis]. University of Pretoria; 2010. Available from: http://upetd.up.ac.za/thesis/available/etd-09132010-162013/

.