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You searched for subject:(3D integrated circuits ICs ). Showing records 1 – 30 of 15723 total matches.

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NSYSU

1. Li, Jun-jie. Effects of Ultrasonic Frequency Variation on the Micro Copper Bumps Friction Phenomena in the Couples-polishing Activation Bonding Process of 3D IC Package.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2013, NSYSU

 Since the development of high-density integrated circuits (ICs), numerous studies have used 3D IC bonding technology to reduce processing temperatures and increase reliability. However, numerous… (more)

Subjects/Keywords: couples-polishing activation bonding (CAB) process; 3D integrated circuits (ICs); copper-bonding process; ultrasonic vibration

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APA (6th Edition):

Li, J. (2013). Effects of Ultrasonic Frequency Variation on the Micro Copper Bumps Friction Phenomena in the Couples-polishing Activation Bonding Process of 3D IC Package. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-220336

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jun-jie. “Effects of Ultrasonic Frequency Variation on the Micro Copper Bumps Friction Phenomena in the Couples-polishing Activation Bonding Process of 3D IC Package.” 2013. Thesis, NSYSU. Accessed March 26, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-220336.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jun-jie. “Effects of Ultrasonic Frequency Variation on the Micro Copper Bumps Friction Phenomena in the Couples-polishing Activation Bonding Process of 3D IC Package.” 2013. Web. 26 Mar 2019.

Vancouver:

Li J. Effects of Ultrasonic Frequency Variation on the Micro Copper Bumps Friction Phenomena in the Couples-polishing Activation Bonding Process of 3D IC Package. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Mar 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-220336.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Effects of Ultrasonic Frequency Variation on the Micro Copper Bumps Friction Phenomena in the Couples-polishing Activation Bonding Process of 3D IC Package. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-220336

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Athikulwongse, Krit. Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier… (more)

Subjects/Keywords: TSV; 3D ICs; Placement; Three-dimensional integrated circuits; Integrated circuits; Integrated circuits Design and construction

…PLACEMENT FOR GATE-LEVEL DESIGN OF 3D ICS Three-dimensional (3D) integrated circuits… …offs, found in three-dimensional integrated circuits (3D ICs) that use through… …footprint without the need for new process generation. Stacking dies in 3D integrated circuits… …79 5.3.1 Power Analysis for 3D ICs . . . . . . . . . . . . . . . . . . . . . . 80 5.3.2… …3D (4 dies) designs for IWLS 2005 benchmarks and industrial circuits. The numbers… 

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APA (6th Edition):

Athikulwongse, K. (2012). Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45783

Chicago Manual of Style (16th Edition):

Athikulwongse, Krit. “Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts.” 2012. Doctoral Dissertation, Georgia Tech. Accessed March 26, 2019. http://hdl.handle.net/1853/45783.

MLA Handbook (7th Edition):

Athikulwongse, Krit. “Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts.” 2012. Web. 26 Mar 2019.

Vancouver:

Athikulwongse K. Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1853/45783.

Council of Science Editors:

Athikulwongse K. Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45783


University of Texas – Austin

3. Ugland, Ryan A. Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits.

Degree: Electrical and Computer Engineering, 2011, University of Texas – Austin

 The potential end of Moore's law has caused the semiconductor industry to investigate 3D integrated circuits as a way to continue to increase transistor density.… (more)

Subjects/Keywords: IEEE 1500; OR1200; 3D integrated circuits; TSV

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APA (6th Edition):

Ugland, R. A. (2011). Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-12-4471

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ugland, Ryan A. “Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits.” 2011. Thesis, University of Texas – Austin. Accessed March 26, 2019. http://hdl.handle.net/2152/ETD-UT-2011-12-4471.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ugland, Ryan A. “Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits.” 2011. Web. 26 Mar 2019.

Vancouver:

Ugland RA. Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits. [Internet] [Thesis]. University of Texas – Austin; 2011. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-12-4471.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ugland RA. Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits. [Thesis]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-12-4471

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

4. Falkenstern, Paul. Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs).

Degree: MS, Computer Science and Engineering, 2008, Penn State University

 Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing two-dimensional (2D) chip designs. Today's integrated chips face several problems, such as… (more)

Subjects/Keywords: OpenAccess; Scan Chains; Three Dimensional Integrated Chips (3D ICs); Floorplan; Power/Ground Network Synthesis

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APA (6th Edition):

Falkenstern, P. (2008). Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs). (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/9083

Chicago Manual of Style (16th Edition):

Falkenstern, Paul. “Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs).” 2008. Masters Thesis, Penn State University. Accessed March 26, 2019. https://etda.libraries.psu.edu/catalog/9083.

MLA Handbook (7th Edition):

Falkenstern, Paul. “Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs).” 2008. Web. 26 Mar 2019.

Vancouver:

Falkenstern P. Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs). [Internet] [Masters thesis]. Penn State University; 2008. [cited 2019 Mar 26]. Available from: https://etda.libraries.psu.edu/catalog/9083.

Council of Science Editors:

Falkenstern P. Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs). [Masters Thesis]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/9083


University of Arkansas

5. Murphree, Robert. A Silicon Carbide Power Management Solution for High Temperature Applications.

Degree: MSEE, 2017, University of Arkansas

  The increasing demand for discrete power devices capable of operating in high temperature and high voltage applications has spurred on the research of semiconductor… (more)

Subjects/Keywords: High Temperature; Integrated Circuits; Linear Regulator; Power Management; Silicon Carbide; Wide Bandgap ICs; Power and Energy

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APA (6th Edition):

Murphree, R. (2017). A Silicon Carbide Power Management Solution for High Temperature Applications. (Masters Thesis). University of Arkansas. Retrieved from http://scholarworks.uark.edu/etd/2542

Chicago Manual of Style (16th Edition):

Murphree, Robert. “A Silicon Carbide Power Management Solution for High Temperature Applications.” 2017. Masters Thesis, University of Arkansas. Accessed March 26, 2019. http://scholarworks.uark.edu/etd/2542.

MLA Handbook (7th Edition):

Murphree, Robert. “A Silicon Carbide Power Management Solution for High Temperature Applications.” 2017. Web. 26 Mar 2019.

Vancouver:

Murphree R. A Silicon Carbide Power Management Solution for High Temperature Applications. [Internet] [Masters thesis]. University of Arkansas; 2017. [cited 2019 Mar 26]. Available from: http://scholarworks.uark.edu/etd/2542.

Council of Science Editors:

Murphree R. A Silicon Carbide Power Management Solution for High Temperature Applications. [Masters Thesis]. University of Arkansas; 2017. Available from: http://scholarworks.uark.edu/etd/2542

6. Thomas tomasevic, Marc veljko. Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles : Substrate coupling study in Smart Power Mixed ICs for automotive application.

Degree: Docteur es, Micro et Nanosystèmes, 2017, Toulouse, INSA

Les circuits Smart Power, utilisés dans l’industrie automobile, se caractérisent par l’intégration sur une puce des parties de puissance avec des parties analogiques&numériques basse tension.… (more)

Subjects/Keywords: Couplage substrat de puissance; Compatibilité Électromagnétique des Circuits Intégrés; Circuits Smart Power; Conception microélectronique; Électronique analogique; Système de mesures sur puce; Power substrate coupling; Electromagnetic compatibility of ICs; Smart Power ICs; Integrated Circuit design-microelectronics; Analog electronics; On-chip measurement; 621.381; 621.381 5; 621.317

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APA (6th Edition):

Thomas tomasevic, M. v. (2017). Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles : Substrate coupling study in Smart Power Mixed ICs for automotive application. (Doctoral Dissertation). Toulouse, INSA. Retrieved from http://www.theses.fr/2017ISAT0002

Chicago Manual of Style (16th Edition):

Thomas tomasevic, Marc veljko. “Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles : Substrate coupling study in Smart Power Mixed ICs for automotive application.” 2017. Doctoral Dissertation, Toulouse, INSA. Accessed March 26, 2019. http://www.theses.fr/2017ISAT0002.

MLA Handbook (7th Edition):

Thomas tomasevic, Marc veljko. “Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles : Substrate coupling study in Smart Power Mixed ICs for automotive application.” 2017. Web. 26 Mar 2019.

Vancouver:

Thomas tomasevic Mv. Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles : Substrate coupling study in Smart Power Mixed ICs for automotive application. [Internet] [Doctoral dissertation]. Toulouse, INSA; 2017. [cited 2019 Mar 26]. Available from: http://www.theses.fr/2017ISAT0002.

Council of Science Editors:

Thomas tomasevic Mv. Etude des couplages substrats dans des circuits mixtes "Smart Power" pour applications automobiles : Substrate coupling study in Smart Power Mixed ICs for automotive application. [Doctoral Dissertation]. Toulouse, INSA; 2017. Available from: http://www.theses.fr/2017ISAT0002


Rutgers University

7. Ausoori, Raghuveer, 1985-. Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability:.

Degree: MS, Electrical and Computer Engineering, 2009, Rutgers University

 We present a radically new design for testability (DFT) algorithm, which inserts test points (TPs) and scanned flip-flops (SFFs) into large circuits to make them… (more)

Subjects/Keywords: Integrated circuits; Integrated circuits – Testing

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APA (6th Edition):

Ausoori, Raghuveer, 1. (2009). Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability:. (Masters Thesis). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000052257

Chicago Manual of Style (16th Edition):

Ausoori, Raghuveer, 1985-. “Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability:.” 2009. Masters Thesis, Rutgers University. Accessed March 26, 2019. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000052257.

MLA Handbook (7th Edition):

Ausoori, Raghuveer, 1985-. “Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability:.” 2009. Web. 26 Mar 2019.

Vancouver:

Ausoori, Raghuveer 1. Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability:. [Internet] [Masters thesis]. Rutgers University; 2009. [cited 2019 Mar 26]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000052257.

Council of Science Editors:

Ausoori, Raghuveer 1. Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability:. [Masters Thesis]. Rutgers University; 2009. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000052257


University of Utah

8. Lodder, Michael Alan. Biologically motivated predictions for dynamic power in VLSI circuits.

Degree: MS;, Electrical & Computer Engineering;, 2008, University of Utah

 As Very Large Scale Integrated (VLSI) circuits continue to shrink in size and increase in complexity, device design is increasingly power constrained. Currently, engineers must… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Lodder, M. A. (2008). Biologically motivated predictions for dynamic power in VLSI circuits. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158

Chicago Manual of Style (16th Edition):

Lodder, Michael Alan. “Biologically motivated predictions for dynamic power in VLSI circuits.” 2008. Masters Thesis, University of Utah. Accessed March 26, 2019. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158.

MLA Handbook (7th Edition):

Lodder, Michael Alan. “Biologically motivated predictions for dynamic power in VLSI circuits.” 2008. Web. 26 Mar 2019.

Vancouver:

Lodder MA. Biologically motivated predictions for dynamic power in VLSI circuits. [Internet] [Masters thesis]. University of Utah; 2008. [cited 2019 Mar 26]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158.

Council of Science Editors:

Lodder MA. Biologically motivated predictions for dynamic power in VLSI circuits. [Masters Thesis]. University of Utah; 2008. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158


University of Hong Kong

9. Huang, Kuan Hsiang, Nick. Electromagnetic compatibility modeling for integrated circuits.

Degree: PhD, 2014, University of Hong Kong

 The integrated circuit (IC) packaging electromagnetic compatibility (EMC)/signal integrity (SI)/power integrity (PI) problems have been broadly attested. But IC packaging electromagnetic interference (EMI) was seldom… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Huang, Kuan Hsiang, N. (2014). Electromagnetic compatibility modeling for integrated circuits. (Doctoral Dissertation). University of Hong Kong. Retrieved from Huang, K. H. N. [黃冠翔]. (2014). Electromagnetic compatibility modeling for integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5312345 ; http://dx.doi.org/10.5353/th_b5312345 ; http://hdl.handle.net/10722/206335

Chicago Manual of Style (16th Edition):

Huang, Kuan Hsiang, Nick. “Electromagnetic compatibility modeling for integrated circuits.” 2014. Doctoral Dissertation, University of Hong Kong. Accessed March 26, 2019. Huang, K. H. N. [黃冠翔]. (2014). Electromagnetic compatibility modeling for integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5312345 ; http://dx.doi.org/10.5353/th_b5312345 ; http://hdl.handle.net/10722/206335.

MLA Handbook (7th Edition):

Huang, Kuan Hsiang, Nick. “Electromagnetic compatibility modeling for integrated circuits.” 2014. Web. 26 Mar 2019.

Vancouver:

Huang, Kuan Hsiang N. Electromagnetic compatibility modeling for integrated circuits. [Internet] [Doctoral dissertation]. University of Hong Kong; 2014. [cited 2019 Mar 26]. Available from: Huang, K. H. N. [黃冠翔]. (2014). Electromagnetic compatibility modeling for integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5312345 ; http://dx.doi.org/10.5353/th_b5312345 ; http://hdl.handle.net/10722/206335.

Council of Science Editors:

Huang, Kuan Hsiang N. Electromagnetic compatibility modeling for integrated circuits. [Doctoral Dissertation]. University of Hong Kong; 2014. Available from: Huang, K. H. N. [黃冠翔]. (2014). Electromagnetic compatibility modeling for integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5312345 ; http://dx.doi.org/10.5353/th_b5312345 ; http://hdl.handle.net/10722/206335


Penn State University

10. Wu, Xiaoxia. Design Exploration for Three-dimensional Integrated Circuits (3DICs).

Degree: PhD, Computer Science and Engineering, 2010, Penn State University

 With technologies scaling, interconnect delay and power consumption has become dominant in deep submicron designs. Three-dimensional Integrated Circuits (3D ICs) have recently emerged as a… (more)

Subjects/Keywords: 3D ICs; hybrid cache; 3D testing; 3D EDA

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APA (6th Edition):

Wu, X. (2010). Design Exploration for Three-dimensional Integrated Circuits (3DICs). (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10517

Chicago Manual of Style (16th Edition):

Wu, Xiaoxia. “Design Exploration for Three-dimensional Integrated Circuits (3DICs).” 2010. Doctoral Dissertation, Penn State University. Accessed March 26, 2019. https://etda.libraries.psu.edu/catalog/10517.

MLA Handbook (7th Edition):

Wu, Xiaoxia. “Design Exploration for Three-dimensional Integrated Circuits (3DICs).” 2010. Web. 26 Mar 2019.

Vancouver:

Wu X. Design Exploration for Three-dimensional Integrated Circuits (3DICs). [Internet] [Doctoral dissertation]. Penn State University; 2010. [cited 2019 Mar 26]. Available from: https://etda.libraries.psu.edu/catalog/10517.

Council of Science Editors:

Wu X. Design Exploration for Three-dimensional Integrated Circuits (3DICs). [Doctoral Dissertation]. Penn State University; 2010. Available from: https://etda.libraries.psu.edu/catalog/10517


Georgia Tech

11. Sane, Hemant. Power supply noise analysis for 3D ICs using through-silicon-vias.

Degree: MS, Electrical and Computer Engineering, 2010, Georgia Tech

3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy… (more)

Subjects/Keywords: Noise analysis; TSV; RLC model; 3D; Systems integration; Three-dimensional display systems; Integrated circuits Noise

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APA (6th Edition):

Sane, H. (2010). Power supply noise analysis for 3D ICs using through-silicon-vias. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33875

Chicago Manual of Style (16th Edition):

Sane, Hemant. “Power supply noise analysis for 3D ICs using through-silicon-vias.” 2010. Masters Thesis, Georgia Tech. Accessed March 26, 2019. http://hdl.handle.net/1853/33875.

MLA Handbook (7th Edition):

Sane, Hemant. “Power supply noise analysis for 3D ICs using through-silicon-vias.” 2010. Web. 26 Mar 2019.

Vancouver:

Sane H. Power supply noise analysis for 3D ICs using through-silicon-vias. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1853/33875.

Council of Science Editors:

Sane H. Power supply noise analysis for 3D ICs using through-silicon-vias. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/33875


University of Southern California

12. Neela, Gopi. A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits.

Degree: PhD, Electrical Engineering, 2015, University of Southern California

 A three dimensional integrated circuit (3DIC) is formed by vertically stacking multiple active devices with high-bandwidth vertical interconnect. 3DIC technology achieves higher-density integration, better scalability,… (more)

Subjects/Keywords: 3DIC; 3D stacking; integrated circuits; TSV; bondpoints; logic partitioning; optimization; interconnects; assignment techniques

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APA (6th Edition):

Neela, G. (2015). A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/524437/rec/229

Chicago Manual of Style (16th Edition):

Neela, Gopi. “A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits.” 2015. Doctoral Dissertation, University of Southern California. Accessed March 26, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/524437/rec/229.

MLA Handbook (7th Edition):

Neela, Gopi. “A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits.” 2015. Web. 26 Mar 2019.

Vancouver:

Neela G. A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2015. [cited 2019 Mar 26]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/524437/rec/229.

Council of Science Editors:

Neela G. A logic partitioning framework and implementation optimizations for 3-dimensional integrated circuits. [Doctoral Dissertation]. University of Southern California; 2015. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/524437/rec/229


Universidade do Rio Grande do Sul

13. Sawicki, Sandro. Particionamento de células e pads de I/O em circuitos VLSI 3D.

Degree: 2009, Universidade do Rio Grande do Sul

A etapa de particionamento em circuitos VLSI 3D é fundamental na distribuição de células e blocos para as camadas do circuito, além de auxiliar na… (more)

Subjects/Keywords: 3D VLSI integrated circuits; Microeletrônica; 3D; Partitioning; Vlsi; Placement; I/O pads; Projeto : Circuitos integrados; Circuitos integrados; CAD

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APA (6th Edition):

Sawicki, S. (2009). Particionamento de células e pads de I/O em circuitos VLSI 3D. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/26502

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sawicki, Sandro. “Particionamento de células e pads de I/O em circuitos VLSI 3D.” 2009. Thesis, Universidade do Rio Grande do Sul. Accessed March 26, 2019. http://hdl.handle.net/10183/26502.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sawicki, Sandro. “Particionamento de células e pads de I/O em circuitos VLSI 3D.” 2009. Web. 26 Mar 2019.

Vancouver:

Sawicki S. Particionamento de células e pads de I/O em circuitos VLSI 3D. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2009. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/10183/26502.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sawicki S. Particionamento de células e pads de I/O em circuitos VLSI 3D. [Thesis]. Universidade do Rio Grande do Sul; 2009. Available from: http://hdl.handle.net/10183/26502

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

14. Yu, Ming. A hybrid numerical technique for analysis and design of microwave integrated circuits.

Degree: Department of Electrical and Computer Engineering, 2018, University of Victoria

 Miniature Hybrid Microwave Integrated Circuits (MHMIC's) in conjunction with Monolithic MIC's (MMIC's) play an important role in modern telecommunication systems. Accurate, fast and reliable analysis… (more)

Subjects/Keywords: Microwave integrated circuits; Hybrid integrated circuits

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APA (6th Edition):

Yu, M. (2018). A hybrid numerical technique for analysis and design of microwave integrated circuits. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/9444

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Ming. “A hybrid numerical technique for analysis and design of microwave integrated circuits.” 2018. Thesis, University of Victoria. Accessed March 26, 2019. https://dspace.library.uvic.ca//handle/1828/9444.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Ming. “A hybrid numerical technique for analysis and design of microwave integrated circuits.” 2018. Web. 26 Mar 2019.

Vancouver:

Yu M. A hybrid numerical technique for analysis and design of microwave integrated circuits. [Internet] [Thesis]. University of Victoria; 2018. [cited 2019 Mar 26]. Available from: https://dspace.library.uvic.ca//handle/1828/9444.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu M. A hybrid numerical technique for analysis and design of microwave integrated circuits. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/9444

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

15. Natu, Nitish Umesh. Design and prototyping of temperature resilient clock distribution networks.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of… (more)

Subjects/Keywords: 3D IC; Through silicon via; Clock distribution network (CDN); Skew; Propagation delay; Adaptive voltage; Controllable delay; FPGA; Test vehicle; ASIC buffer design; Three-dimensional integrated circuits; Integrated circuits

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APA (6th Edition):

Natu, N. U. (2014). Design and prototyping of temperature resilient clock distribution networks. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51812

Chicago Manual of Style (16th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Masters Thesis, Georgia Tech. Accessed March 26, 2019. http://hdl.handle.net/1853/51812.

MLA Handbook (7th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Web. 26 Mar 2019.

Vancouver:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1853/51812.

Council of Science Editors:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51812


Queens University

16. He, Shan. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .

Degree: Electrical and Computer Engineering, 2011, Queens University

 Analog circuits that operate with low voltage supply headroom generally suffer from poor linearity performance, poor noise performance, etc. However, with the aggressive scaling of… (more)

Subjects/Keywords: Linearity; Integrated Circuits

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APA (6th Edition):

He, S. (2011). Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/6746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

He, Shan. “Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .” 2011. Thesis, Queens University. Accessed March 26, 2019. http://hdl.handle.net/1974/6746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

He, Shan. “Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .” 2011. Web. 26 Mar 2019.

Vancouver:

He S. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . [Internet] [Thesis]. Queens University; 2011. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1974/6746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

He S. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . [Thesis]. Queens University; 2011. Available from: http://hdl.handle.net/1974/6746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Johannesburg

17. Lacquet, Beatrys Margaretha. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.

Degree: 2014, University of Johannesburg

M.Ing. (Electrical & Electronic Engineering Science)

Please refer to full text to view abstract

Subjects/Keywords: Integrated circuits; Semiconductors

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APA (6th Edition):

Lacquet, B. M. (2014). Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. (Thesis). University of Johannesburg. Retrieved from http://hdl.handle.net/10210/12197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lacquet, Beatrys Margaretha. “Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.” 2014. Thesis, University of Johannesburg. Accessed March 26, 2019. http://hdl.handle.net/10210/12197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lacquet, Beatrys Margaretha. “Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.” 2014. Web. 26 Mar 2019.

Vancouver:

Lacquet BM. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. [Internet] [Thesis]. University of Johannesburg; 2014. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/10210/12197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lacquet BM. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. [Thesis]. University of Johannesburg; 2014. Available from: http://hdl.handle.net/10210/12197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Latrobe University

18. Radfar, Mohsen. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.

Degree: PhD, 2013, Latrobe University

Thesis (Ph.D.) - La Trobe University, 2013

Submission note: "A thesis submitted in total fulfilment of the requirements for the degree of Doctor of Philosophy… (more)

Subjects/Keywords: Integrated circuits.; Integrated circuits  – Design and construction.; Low voltage integrated circuits.

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APA (6th Edition):

Radfar, M. (2013). Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. (Doctoral Dissertation). Latrobe University. Retrieved from http://hdl.handle.net/1959.9/513567

Chicago Manual of Style (16th Edition):

Radfar, Mohsen. “Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.” 2013. Doctoral Dissertation, Latrobe University. Accessed March 26, 2019. http://hdl.handle.net/1959.9/513567.

MLA Handbook (7th Edition):

Radfar, Mohsen. “Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.” 2013. Web. 26 Mar 2019.

Vancouver:

Radfar M. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. [Internet] [Doctoral dissertation]. Latrobe University; 2013. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1959.9/513567.

Council of Science Editors:

Radfar M. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. [Doctoral Dissertation]. Latrobe University; 2013. Available from: http://hdl.handle.net/1959.9/513567


Ryerson University

19. Al-Obaidy, Furat. IC testing using thermal image based on intelligent classification methods.

Degree: 2016, Ryerson University

 The goal of this thesis is to propose an algorithm which would can locate the defect IC on the PCB during their manufacturing phase based… (more)

Subjects/Keywords: Integrated circuits  – Thermal properties  – Testing  – Thermographic methods; Integrated circuits  – Testing; Integrated circuits  – Fault tolerance; Integrated circuits; Printed circuits  – Testing; Printed circuits

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APA (6th Edition):

Al-Obaidy, F. (2016). IC testing using thermal image based on intelligent classification methods. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Al-Obaidy, Furat. “IC testing using thermal image based on intelligent classification methods.” 2016. Thesis, Ryerson University. Accessed March 26, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A5822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Al-Obaidy, Furat. “IC testing using thermal image based on intelligent classification methods.” 2016. Web. 26 Mar 2019.

Vancouver:

Al-Obaidy F. IC testing using thermal image based on intelligent classification methods. [Internet] [Thesis]. Ryerson University; 2016. [cited 2019 Mar 26]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Al-Obaidy F. IC testing using thermal image based on intelligent classification methods. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

20. Sabado, Francis Corpuz. Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits.

Degree: PhD, 2017, University of Arkansas

  This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL… (more)

Subjects/Keywords: 3D IC; Asynchronous; Integrated Circuit; MTNCL; NCL; Three-dimensional; Computer Sciences; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Sabado, F. C. (2017). Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits. (Doctoral Dissertation). University of Arkansas. Retrieved from http://scholarworks.uark.edu/etd/2584

Chicago Manual of Style (16th Edition):

Sabado, Francis Corpuz. “Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits.” 2017. Doctoral Dissertation, University of Arkansas. Accessed March 26, 2019. http://scholarworks.uark.edu/etd/2584.

MLA Handbook (7th Edition):

Sabado, Francis Corpuz. “Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits.” 2017. Web. 26 Mar 2019.

Vancouver:

Sabado FC. Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2019 Mar 26]. Available from: http://scholarworks.uark.edu/etd/2584.

Council of Science Editors:

Sabado FC. Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: http://scholarworks.uark.edu/etd/2584


Georgia Tech

21. Healy, Michael Benjamin. Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures.

Degree: MS, Electrical and Computer Engineering, 2006, Georgia Tech

 The main objective of this thesis is to develop a physical design tool that is capable of being used by microarchitects to evaluate the impact… (more)

Subjects/Keywords: Temperature; Performance; 3D integrated circuits; Thermal distribution; Floorplanning

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APA (6th Edition):

Healy, M. B. (2006). Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/10562

Chicago Manual of Style (16th Edition):

Healy, Michael Benjamin. “Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures.” 2006. Masters Thesis, Georgia Tech. Accessed March 26, 2019. http://hdl.handle.net/1853/10562.

MLA Handbook (7th Edition):

Healy, Michael Benjamin. “Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures.” 2006. Web. 26 Mar 2019.

Vancouver:

Healy MB. Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures. [Internet] [Masters thesis]. Georgia Tech; 2006. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1853/10562.

Council of Science Editors:

Healy MB. Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures. [Masters Thesis]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/10562


NSYSU

22. Zheng, Yi-Xue. Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 This thesis proposes a synthesis methodology which is capable of fault-tolerance and deadlock-free for constructing a custom NoC topology in 3D ICs. In this thesis,… (more)

Subjects/Keywords: 3D ICs; deadlock-free; topology; fault tolerant; Network-on-Chip

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APA (6th Edition):

Zheng, Y. (2011). Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zheng, Yi-Xue. “Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits.” 2011. Thesis, NSYSU. Accessed March 26, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zheng, Yi-Xue. “Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits.” 2011. Web. 26 Mar 2019.

Vancouver:

Zheng Y. Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Mar 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zheng Y. Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

23. Wan, Zhimin. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.

Degree: PhD, Mechanical Engineering, 2016, Georgia Tech

 Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking… (more)

Subjects/Keywords: Microfluidic cooling; Pin fin; 3D ICs; Microfabrication; Flow boiling

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APA (6th Edition):

Wan, Z. (2016). Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55480

Chicago Manual of Style (16th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed March 26, 2019. http://hdl.handle.net/1853/55480.

MLA Handbook (7th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Web. 26 Mar 2019.

Vancouver:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1853/55480.

Council of Science Editors:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55480


University of Minnesota

24. Cai, Liuchun. Advanced architectures for next generation wireless integrated circuits.

Degree: PhD, Electrical Engineering, 2009, University of Minnesota

 In this thesis, we present and discuss two advanced architectures of wireless integrated circuits. In the first part of this thesis we will focus on… (more)

Subjects/Keywords: 3D ICs; Inductorless; LNA; Mixer; PLL; Receiver; Electrical Engineering

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APA (6th Edition):

Cai, L. (2009). Advanced architectures for next generation wireless integrated circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/54305

Chicago Manual of Style (16th Edition):

Cai, Liuchun. “Advanced architectures for next generation wireless integrated circuits.” 2009. Doctoral Dissertation, University of Minnesota. Accessed March 26, 2019. http://purl.umn.edu/54305.

MLA Handbook (7th Edition):

Cai, Liuchun. “Advanced architectures for next generation wireless integrated circuits.” 2009. Web. 26 Mar 2019.

Vancouver:

Cai L. Advanced architectures for next generation wireless integrated circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2009. [cited 2019 Mar 26]. Available from: http://purl.umn.edu/54305.

Council of Science Editors:

Cai L. Advanced architectures for next generation wireless integrated circuits. [Doctoral Dissertation]. University of Minnesota; 2009. Available from: http://purl.umn.edu/54305


University of Alberta

25. Skorka, Orit. Vertically-Integrated CMOS Technology for Third-Generation Image Sensors.

Degree: PhD, Department of Electrical and Computer Engineering, 2011, University of Alberta

 Over the past four decades, CCDs and CMOS active-pixel sensors have defined the first and second generations of electronic image sensors, respectively. They are the… (more)

Subjects/Keywords: vertically-integrated ICs; electronic imaging; image sensors; photodetectors; digital cameras

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APA (6th Edition):

Skorka, O. (2011). Vertically-Integrated CMOS Technology for Third-Generation Image Sensors. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/0z708x980

Chicago Manual of Style (16th Edition):

Skorka, Orit. “Vertically-Integrated CMOS Technology for Third-Generation Image Sensors.” 2011. Doctoral Dissertation, University of Alberta. Accessed March 26, 2019. https://era.library.ualberta.ca/files/0z708x980.

MLA Handbook (7th Edition):

Skorka, Orit. “Vertically-Integrated CMOS Technology for Third-Generation Image Sensors.” 2011. Web. 26 Mar 2019.

Vancouver:

Skorka O. Vertically-Integrated CMOS Technology for Third-Generation Image Sensors. [Internet] [Doctoral dissertation]. University of Alberta; 2011. [cited 2019 Mar 26]. Available from: https://era.library.ualberta.ca/files/0z708x980.

Council of Science Editors:

Skorka O. Vertically-Integrated CMOS Technology for Third-Generation Image Sensors. [Doctoral Dissertation]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/0z708x980


Université de Grenoble

26. Brocard, Mélanie. Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits.

Degree: Docteur es, Sciences et technologie industrielles, 2013, Université de Grenoble

Ces dernières années ont vu l'émergence d'un nouveaux concept dans le domaine de la microélectronique pour répondre aux besoins grandissant en termes de performances et… (more)

Subjects/Keywords: Vias traversant le silicium (TSV); Circuit intégrés 3D; Couplage substrat; Modélisation électrique; Simulation électriques; Transistors MOS; Through silicon via (TSV); 3D integrated circuits; Substrate coupling; Modeling; Electrical simulation; MOS transistors

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APA (6th Edition):

Brocard, M. (2013). Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2013GRENT049

Chicago Manual of Style (16th Edition):

Brocard, Mélanie. “Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits.” 2013. Doctoral Dissertation, Université de Grenoble. Accessed March 26, 2019. http://www.theses.fr/2013GRENT049.

MLA Handbook (7th Edition):

Brocard, Mélanie. “Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits.” 2013. Web. 26 Mar 2019.

Vancouver:

Brocard M. Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits. [Internet] [Doctoral dissertation]. Université de Grenoble; 2013. [cited 2019 Mar 26]. Available from: http://www.theses.fr/2013GRENT049.

Council of Science Editors:

Brocard M. Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D. : Caracterization and analysis of substrate coupling between TSV and transistors in 3D integrated circuits. [Doctoral Dissertation]. Université de Grenoble; 2013. Available from: http://www.theses.fr/2013GRENT049


Georgia Tech

27. Sekar, Deepak Chandra. Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2008, Georgia Tech

 A high-performance 2D or 3D integrated circuit typically has (i) ratio of delay of a 1mm wire to delay of a nMOS transistor > 500,… (more)

Subjects/Keywords: Interconnects; 3D integration; Integrated circuits; Interconnects (Integrated circuit technology); Electrodiffusion

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APA (6th Edition):

Sekar, D. C. (2008). Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26562

Chicago Manual of Style (16th Edition):

Sekar, Deepak Chandra. “Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits.” 2008. Doctoral Dissertation, Georgia Tech. Accessed March 26, 2019. http://hdl.handle.net/1853/26562.

MLA Handbook (7th Edition):

Sekar, Deepak Chandra. “Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits.” 2008. Web. 26 Mar 2019.

Vancouver:

Sekar DC. Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1853/26562.

Council of Science Editors:

Sekar DC. Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26562


Oregon State University

28. Patwary, Md. Ataur R. Low-power dynamic CMOS circuits in high-performance memory arrays.

Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University

 Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic… (more)

Subjects/Keywords: Dynamic circuits; Low voltage integrated circuits

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APA (6th Edition):

Patwary, M. A. R. (2009). Low-power dynamic CMOS circuits in high-performance memory arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10906

Chicago Manual of Style (16th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Doctoral Dissertation, Oregon State University. Accessed March 26, 2019. http://hdl.handle.net/1957/10906.

MLA Handbook (7th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Web. 26 Mar 2019.

Vancouver:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1957/10906.

Council of Science Editors:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/10906


University of Hong Kong

29. Meng, Lingling. Computational electromagnetics methods for IC modeling.

Degree: M. Phil., 2013, University of Hong Kong

Two kinds of computational electromagnetics (CEM) methodology are discussed for the challenges in integrated circuit (IC) and printed circuit board (PCB) design. One is an… (more)

Subjects/Keywords: Electromagnetism - Data processing; Integrated circuits; Printed circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Meng, L. (2013). Computational electromagnetics methods for IC modeling. (Masters Thesis). University of Hong Kong. Retrieved from Meng, L. [孟玲玲]. (2013). Computational electromagnetics methods for IC modeling. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5153736 ; http://dx.doi.org/10.5353/th_b5153736 ; http://hdl.handle.net/10722/195993

Chicago Manual of Style (16th Edition):

Meng, Lingling. “Computational electromagnetics methods for IC modeling.” 2013. Masters Thesis, University of Hong Kong. Accessed March 26, 2019. Meng, L. [孟玲玲]. (2013). Computational electromagnetics methods for IC modeling. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5153736 ; http://dx.doi.org/10.5353/th_b5153736 ; http://hdl.handle.net/10722/195993.

MLA Handbook (7th Edition):

Meng, Lingling. “Computational electromagnetics methods for IC modeling.” 2013. Web. 26 Mar 2019.

Vancouver:

Meng L. Computational electromagnetics methods for IC modeling. [Internet] [Masters thesis]. University of Hong Kong; 2013. [cited 2019 Mar 26]. Available from: Meng, L. [孟玲玲]. (2013). Computational electromagnetics methods for IC modeling. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5153736 ; http://dx.doi.org/10.5353/th_b5153736 ; http://hdl.handle.net/10722/195993.

Council of Science Editors:

Meng L. Computational electromagnetics methods for IC modeling. [Masters Thesis]. University of Hong Kong; 2013. Available from: Meng, L. [孟玲玲]. (2013). Computational electromagnetics methods for IC modeling. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5153736 ; http://dx.doi.org/10.5353/th_b5153736 ; http://hdl.handle.net/10722/195993


Drexel University

30. Lu, Jianchao. High performance IC clock networks with grid and tree topologies.

Degree: 2011, Drexel University

In this dissertation, an essential step in the integrated circuit (IC) physical design flow—the clock network design—is investigated. Clock network design entailsa series of computationally… (more)

Subjects/Keywords: Electric engineering; Integrated circuits; Timing circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, J. (2011). High performance IC clock networks with grid and tree topologies. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/3526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Jianchao. “High performance IC clock networks with grid and tree topologies.” 2011. Thesis, Drexel University. Accessed March 26, 2019. http://hdl.handle.net/1860/3526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Jianchao. “High performance IC clock networks with grid and tree topologies.” 2011. Web. 26 Mar 2019.

Vancouver:

Lu J. High performance IC clock networks with grid and tree topologies. [Internet] [Thesis]. Drexel University; 2011. [cited 2019 Mar 26]. Available from: http://hdl.handle.net/1860/3526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu J. High performance IC clock networks with grid and tree topologies. [Thesis]. Drexel University; 2011. Available from: http://hdl.handle.net/1860/3526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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