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You searched for subject:(3D IC). Showing records 1 – 30 of 59 total matches.

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Georgia Tech

1. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D(more)

Subjects/Keywords: 3D IC; Design Methodologies

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APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 25, 2020. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 25 Sep 2020.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188


University of Minnesota

2. Jain, Pulkit. Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes.

Degree: PhD, Electrical Engineering, 2012, University of Minnesota

 Rising electric fields and imperfections due to atomic level scaling create non-ideal and stochastic electrodynamics inside a transistor.These appear as reliability mechanisms such as Bias… (more)

Subjects/Keywords: 3D IC; BTI; Reliability; RTN; TDDB; TSV

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APA (6th Edition):

Jain, P. (2012). Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/165683

Chicago Manual of Style (16th Edition):

Jain, Pulkit. “Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes.” 2012. Doctoral Dissertation, University of Minnesota. Accessed September 25, 2020. http://hdl.handle.net/11299/165683.

MLA Handbook (7th Edition):

Jain, Pulkit. “Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes.” 2012. Web. 25 Sep 2020.

Vancouver:

Jain P. Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes. [Internet] [Doctoral dissertation]. University of Minnesota; 2012. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/11299/165683.

Council of Science Editors:

Jain P. Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes. [Doctoral Dissertation]. University of Minnesota; 2012. Available from: http://hdl.handle.net/11299/165683


Duke University

3. Deutsch, Sergej. Test and Debug Solutions for 3D-Stacked Integrated Circuits .

Degree: 2015, Duke University

  Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper… (more)

Subjects/Keywords: Electrical engineering; 3D-IC; Test; TSV

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APA (6th Edition):

Deutsch, S. (2015). Test and Debug Solutions for 3D-Stacked Integrated Circuits . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/10450

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Deutsch, Sergej. “Test and Debug Solutions for 3D-Stacked Integrated Circuits .” 2015. Thesis, Duke University. Accessed September 25, 2020. http://hdl.handle.net/10161/10450.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Deutsch, Sergej. “Test and Debug Solutions for 3D-Stacked Integrated Circuits .” 2015. Web. 25 Sep 2020.

Vancouver:

Deutsch S. Test and Debug Solutions for 3D-Stacked Integrated Circuits . [Internet] [Thesis]. Duke University; 2015. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10161/10450.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Deutsch S. Test and Debug Solutions for 3D-Stacked Integrated Circuits . [Thesis]. Duke University; 2015. Available from: http://hdl.handle.net/10161/10450

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

4. Yueh, Wen. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The multi-chip integration in an advanced packaging has made the multi-physics interactions increasingly important. The objective of this research is to address the thermal coupling… (more)

Subjects/Keywords: Cooling; VLSI; SRAM; EDRAM; 3D IC; Packaging

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APA (6th Edition):

Yueh, W. (2015). Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56171

Chicago Manual of Style (16th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 25, 2020. http://hdl.handle.net/1853/56171.

MLA Handbook (7th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Web. 25 Sep 2020.

Vancouver:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1853/56171.

Council of Science Editors:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56171


NSYSU

5. Ho, Cheng-you. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This paper presents a set of novel scheme and corresponding methods for Test Interposer Interconnects. Testing interposer is difficult due to the large number of… (more)

Subjects/Keywords: 3D Stack; 3D Package; 2.5D; 3D IC; Interposer; Through-Silicon Via

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APA (6th Edition):

Ho, C. (2014). An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Cheng-you. “An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.” 2014. Thesis, NSYSU. Accessed September 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Cheng-you. “An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.” 2014. Web. 25 Sep 2020.

Vancouver:

Ho C. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho C. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Sarhan, Hossam. Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Université Grenoble Alpes (ComUE)

L'impact des interconnections d'un circuit intégré sur les performances et la consommation est de plus en plus important à partir du nœud CMOS 28 nm… (more)

Subjects/Keywords: 3D IC; Monolithique 3D; Méthodologie de conception; 3D haute densité; Architecture; Évaluation des technologies; 3D IC; Monolithic 3D; Design methodology; High density 3D; Architecture; Technololgy assessment; 620

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APA (6th Edition):

Sarhan, H. (2015). Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2015GREAT134

Chicago Manual of Style (16th Edition):

Sarhan, Hossam. “Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité.” 2015. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed September 25, 2020. http://www.theses.fr/2015GREAT134.

MLA Handbook (7th Edition):

Sarhan, Hossam. “Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité.” 2015. Web. 25 Sep 2020.

Vancouver:

Sarhan H. Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2015. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2015GREAT134.

Council of Science Editors:

Sarhan H. Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2015. Available from: http://www.theses.fr/2015GREAT134


Université de Grenoble

7. Jabbar, Mohamad. Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D : ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip.

Degree: Docteur es, Sciences et technologie industrielles, 2013, Université de Grenoble

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre… (more)

Subjects/Keywords: 3D IC; Exploration; MPSoC; NoC; Mise en oeuvre de conception physique; 3D IC; Exploration; MPSoC; NoC; Physical Design

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APA (6th Edition):

Jabbar, M. (2013). Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D : ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2013GRENT006

Chicago Manual of Style (16th Edition):

Jabbar, Mohamad. “Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D : ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip.” 2013. Doctoral Dissertation, Université de Grenoble. Accessed September 25, 2020. http://www.theses.fr/2013GRENT006.

MLA Handbook (7th Edition):

Jabbar, Mohamad. “Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D : ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip.” 2013. Web. 25 Sep 2020.

Vancouver:

Jabbar M. Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D : ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip. [Internet] [Doctoral dissertation]. Université de Grenoble; 2013. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2013GRENT006.

Council of Science Editors:

Jabbar M. Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D : ASIC Design Methodologies for 3D NOC Based 3D Heterogeneous Multiprocessor on Chip. [Doctoral Dissertation]. Université de Grenoble; 2013. Available from: http://www.theses.fr/2013GRENT006


Penn State University

8. DeBole, Michael Vincent. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS .

Degree: 2011, Penn State University

 Video analytics is the science of analyzing image sequences and video with the aim to gain a cognitive understanding of a scene. The applications which… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; Image Processing; 3D IC; FPGA Framework

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APA (6th Edition):

DeBole, M. V. (2011). CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/11829

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DeBole, Michael Vincent. “CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS .” 2011. Thesis, Penn State University. Accessed September 25, 2020. https://submit-etda.libraries.psu.edu/catalog/11829.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DeBole, Michael Vincent. “CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS .” 2011. Web. 25 Sep 2020.

Vancouver:

DeBole MV. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Sep 25]. Available from: https://submit-etda.libraries.psu.edu/catalog/11829.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DeBole MV. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/11829

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Fan, Li. 3D-IC Technology Characterization and Test Chip Design.

Degree: 2013, University of Saskatchewan

 With sub-micron silicon processing technology reaching under 30nm, it becomes more difficult for integrated circuits to achieve higher integration through the scaling down of the… (more)

Subjects/Keywords: 3D-IC; TSV

…71 vii List of Figures 1.1 Typical 3D-IC Structure… …2 1.2 Timing improvement: 3D-IC compares to 2D-IC . . . . . . . . . . . . . . . . 3… …32 3.6 Schematic of a ring oscillator used in 3D-IC… …growing demand for integration improvement, 3D-IC packaging was invented with 1 the… …involvement of many manufacturers. This is the future trend for chip packaging. 1.1 3D-IC… 

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APA (6th Edition):

Fan, L. (2013). 3D-IC Technology Characterization and Test Chip Design. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/ETD-2013-02-912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fan, Li. “3D-IC Technology Characterization and Test Chip Design.” 2013. Thesis, University of Saskatchewan. Accessed September 25, 2020. http://hdl.handle.net/10388/ETD-2013-02-912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fan, Li. “3D-IC Technology Characterization and Test Chip Design.” 2013. Web. 25 Sep 2020.

Vancouver:

Fan L. 3D-IC Technology Characterization and Test Chip Design. [Internet] [Thesis]. University of Saskatchewan; 2013. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10388/ETD-2013-02-912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fan L. 3D-IC Technology Characterization and Test Chip Design. [Thesis]. University of Saskatchewan; 2013. Available from: http://hdl.handle.net/10388/ETD-2013-02-912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Yang , Shi. Design and Implementation of A Scalable Test Module to Support 3D IC Testing.

Degree: Master, Electrical Engineering, 2014, NSYSU

 This thesis presents a new test architecture based on 3D IC stacking stage, called scalable test module (STM). STM will be fabricated a separate die… (more)

Subjects/Keywords: test efficiency; scalability; 3D IC testing; IEEE 1149.1 Std.

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APA (6th Edition):

Yang , S. (2014). Design and Implementation of A Scalable Test Module to Support 3D IC Testing. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727114-222124

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang , Shi. “Design and Implementation of A Scalable Test Module to Support 3D IC Testing.” 2014. Thesis, NSYSU. Accessed September 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727114-222124.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang , Shi. “Design and Implementation of A Scalable Test Module to Support 3D IC Testing.” 2014. Web. 25 Sep 2020.

Vancouver:

Yang S. Design and Implementation of A Scalable Test Module to Support 3D IC Testing. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727114-222124.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang S. Design and Implementation of A Scalable Test Module to Support 3D IC Testing. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727114-222124

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Hsu, Chin-An. Performance Analysis and Optimization of Scalable Test Module.

Degree: Master, Electrical Engineering, 2015, NSYSU

3D IC is one of the hot research topics recently due to its advantages of smaller chip area and lower power consumption. However, many challenges… (more)

Subjects/Keywords: 3D IC testing; IEEE 1149.1 Std; testing performance analysis

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APA (6th Edition):

Hsu, C. (2015). Performance Analysis and Optimization of Scalable Test Module. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-141402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chin-An. “Performance Analysis and Optimization of Scalable Test Module.” 2015. Thesis, NSYSU. Accessed September 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-141402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chin-An. “Performance Analysis and Optimization of Scalable Test Module.” 2015. Web. 25 Sep 2020.

Vancouver:

Hsu C. Performance Analysis and Optimization of Scalable Test Module. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Sep 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-141402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Performance Analysis and Optimization of Scalable Test Module. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-141402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Princeton University

12. Chen, Xianmin. FinFET-based System Modeling and Low-Power System Design .

Degree: PhD, 2016, Princeton University

 FinFET has begun to replace MOSFET at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has higher on-current and lower leakage due… (more)

Subjects/Keywords: 3D IC; FinFET; Low-power; NoC; PVT variation; System modeling

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APA (6th Edition):

Chen, X. (2016). FinFET-based System Modeling and Low-Power System Design . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp016t053j389

Chicago Manual of Style (16th Edition):

Chen, Xianmin. “FinFET-based System Modeling and Low-Power System Design .” 2016. Doctoral Dissertation, Princeton University. Accessed September 25, 2020. http://arks.princeton.edu/ark:/88435/dsp016t053j389.

MLA Handbook (7th Edition):

Chen, Xianmin. “FinFET-based System Modeling and Low-Power System Design .” 2016. Web. 25 Sep 2020.

Vancouver:

Chen X. FinFET-based System Modeling and Low-Power System Design . [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2020 Sep 25]. Available from: http://arks.princeton.edu/ark:/88435/dsp016t053j389.

Council of Science Editors:

Chen X. FinFET-based System Modeling and Low-Power System Design . [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp016t053j389


Delft University of Technology

13. Winters, J. (author). Conceptual Design of a Pick and Place Machine for 3D-IC.

Degree: 2010, Delft University of Technology

Precision and Microsystems Engineering

Mechanical, Maritime and Materials Engineering

Advisors/Committee Members: Munnig Schmidt, R.H. (mentor).

Subjects/Keywords: Pick and Place; 3D-IC

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APA (6th Edition):

Winters, J. (. (2010). Conceptual Design of a Pick and Place Machine for 3D-IC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a8de4ca9-2f44-4842-a62d-06aad3f782e6

Chicago Manual of Style (16th Edition):

Winters, J (author). “Conceptual Design of a Pick and Place Machine for 3D-IC.” 2010. Masters Thesis, Delft University of Technology. Accessed September 25, 2020. http://resolver.tudelft.nl/uuid:a8de4ca9-2f44-4842-a62d-06aad3f782e6.

MLA Handbook (7th Edition):

Winters, J (author). “Conceptual Design of a Pick and Place Machine for 3D-IC.” 2010. Web. 25 Sep 2020.

Vancouver:

Winters J(. Conceptual Design of a Pick and Place Machine for 3D-IC. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Sep 25]. Available from: http://resolver.tudelft.nl/uuid:a8de4ca9-2f44-4842-a62d-06aad3f782e6.

Council of Science Editors:

Winters J(. Conceptual Design of a Pick and Place Machine for 3D-IC. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:a8de4ca9-2f44-4842-a62d-06aad3f782e6


Rochester Institute of Technology

14. Coddington, James David. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures.

Degree: MS, Computer Engineering, 2015, Rochester Institute of Technology

  With the increased complexity and continual scaling of integrated circuit performance, multi-core chips with dozens, hundreds, even thousands of parallel computing units require high… (more)

Subjects/Keywords: 3D IC; Architecture; Energy; Interconnect; Network-on-chip; Performance

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APA (6th Edition):

Coddington, J. D. (2015). Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8588

Chicago Manual of Style (16th Edition):

Coddington, James David. “Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed September 25, 2020. https://scholarworks.rit.edu/theses/8588.

MLA Handbook (7th Edition):

Coddington, James David. “Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures.” 2015. Web. 25 Sep 2020.

Vancouver:

Coddington JD. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2020 Sep 25]. Available from: https://scholarworks.rit.edu/theses/8588.

Council of Science Editors:

Coddington JD. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8588


University of Windsor

15. Basith, Iftekhar Ibne. Contactless Test Access Mechanism for 3D IC.

Degree: PhD, Electrical and Computer Engineering, 2016, University of Windsor

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size… (more)

Subjects/Keywords: 3D IC; Contactless; Coupling; Fabrication; Test; Through-Silicon Via

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basith, I. I. (2016). Contactless Test Access Mechanism for 3D IC. (Doctoral Dissertation). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5799

Chicago Manual of Style (16th Edition):

Basith, Iftekhar Ibne. “Contactless Test Access Mechanism for 3D IC.” 2016. Doctoral Dissertation, University of Windsor. Accessed September 25, 2020. https://scholar.uwindsor.ca/etd/5799.

MLA Handbook (7th Edition):

Basith, Iftekhar Ibne. “Contactless Test Access Mechanism for 3D IC.” 2016. Web. 25 Sep 2020.

Vancouver:

Basith II. Contactless Test Access Mechanism for 3D IC. [Internet] [Doctoral dissertation]. University of Windsor; 2016. [cited 2020 Sep 25]. Available from: https://scholar.uwindsor.ca/etd/5799.

Council of Science Editors:

Basith II. Contactless Test Access Mechanism for 3D IC. [Doctoral Dissertation]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5799


Georgia Tech

16. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC(more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

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APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 25, 2020. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 25 Sep 2020.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330

17. DASH, ASSMITRA. Minimizing Test Time through Test FlowOptimization in 3D-SICs.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

3D stacked ICs (3D-SICs) with multiple dies interconnected by through-silicon-vias(TSVs) are considered as a technology driver and proven to have overwhelming advantagesover traditional ICs… (more)

Subjects/Keywords: 3D IC; 3D SIC; Testflow

…41 v List of Figures 1.1 1.2 1.3 Comparison of 2D IC with 3D-SIC… …for 2D IC, (b) Test flow for 3D-SIC . . . . . . . . . . . 2 3 5 3.1 3.2… …latest evolution of 3D stacked IC (3D-SIC), where “a single package containing a… …traditional IC is illustrated in figure 1.1. These TSV based 3D-SICs are termed as “super chips” as… …performance and reduced cost Figure 1.1: Comparison of 2D IC with 3D-SIC The manufacturing process… 

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APA (6th Edition):

DASH, A. (2013). Minimizing Test Time through Test FlowOptimization in 3D-SICs. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102171

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DASH, ASSMITRA. “Minimizing Test Time through Test FlowOptimization in 3D-SICs.” 2013. Thesis, Linköping UniversityLinköping University. Accessed September 25, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102171.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DASH, ASSMITRA. “Minimizing Test Time through Test FlowOptimization in 3D-SICs.” 2013. Web. 25 Sep 2020.

Vancouver:

DASH A. Minimizing Test Time through Test FlowOptimization in 3D-SICs. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Sep 25]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102171.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DASH A. Minimizing Test Time through Test FlowOptimization in 3D-SICs. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102171

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

18. Jagtap, R.S. (author). A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs.

Degree: 2011, Delft University of Technology

Planar scaling of semiconductor ICs for achieving higher integration seems to be on the brink of saturation. As an alternative solution, three-dimensional (3D) integration follows… (more)

Subjects/Keywords: 3D IC; TSV; SystemC; simulation methodology; interconnect topology; 3D chip stacking; TSV modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jagtap, R. S. (. (2011). A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ec523897-4480-438f-8558-a72636b33dbc

Chicago Manual of Style (16th Edition):

Jagtap, R S (author). “A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs.” 2011. Masters Thesis, Delft University of Technology. Accessed September 25, 2020. http://resolver.tudelft.nl/uuid:ec523897-4480-438f-8558-a72636b33dbc.

MLA Handbook (7th Edition):

Jagtap, R S (author). “A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs.” 2011. Web. 25 Sep 2020.

Vancouver:

Jagtap RS(. A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2020 Sep 25]. Available from: http://resolver.tudelft.nl/uuid:ec523897-4480-438f-8558-a72636b33dbc.

Council of Science Editors:

Jagtap RS(. A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:ec523897-4480-438f-8558-a72636b33dbc


NSYSU

19. Wang, Ming-Han. Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2014, NSYSU

 Polymer material tends to absorb moisture of environment to cause volume swelling among various materials of electronic package, such as underfill and substrate. The residual… (more)

Subjects/Keywords: Finite element; Glass transition temperature; Vapor pressure; Organic passivation; Moisture; 2.5D IC Package; 3D IC Package

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APA (6th Edition):

Wang, M. (2014). Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ming-Han. “Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects.” 2014. Thesis, NSYSU. Accessed September 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ming-Han. “Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects.” 2014. Web. 25 Sep 2020.

Vancouver:

Wang M. Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang M. Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Windsor

20. Mashkovtsev, Vladimir Spartakovich. A DLL Based Test Solution for 3D ICs.

Degree: MA, Electrical and Computer Engineering, 2015, University of Windsor

  Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations… (more)

Subjects/Keywords: 2.5D IC Integration; 3D IC Integration; Delay locked loop (DLL); Design-for-test; Parametric faults; Test for interposers

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mashkovtsev, V. S. (2015). A DLL Based Test Solution for 3D ICs. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5295

Chicago Manual of Style (16th Edition):

Mashkovtsev, Vladimir Spartakovich. “A DLL Based Test Solution for 3D ICs.” 2015. Masters Thesis, University of Windsor. Accessed September 25, 2020. https://scholar.uwindsor.ca/etd/5295.

MLA Handbook (7th Edition):

Mashkovtsev, Vladimir Spartakovich. “A DLL Based Test Solution for 3D ICs.” 2015. Web. 25 Sep 2020.

Vancouver:

Mashkovtsev VS. A DLL Based Test Solution for 3D ICs. [Internet] [Masters thesis]. University of Windsor; 2015. [cited 2020 Sep 25]. Available from: https://scholar.uwindsor.ca/etd/5295.

Council of Science Editors:

Mashkovtsev VS. A DLL Based Test Solution for 3D ICs. [Masters Thesis]. University of Windsor; 2015. Available from: https://scholar.uwindsor.ca/etd/5295

21. Souare, Papa Momar. Effets thermiques dans les empilements 3d de puces électroniques : études numériques et expérimentales : Thermal effects in 3d stacks of electronic chip : numerical and experimental studies.

Degree: Docteur es, Sciences et génie des Matériaux, 2014, Saint-Etienne, EMSE

On assiste aujourd’hui à une évolution des systèmes électroniques nomades vers des fonctionnalités plus avancées. Cette complexification des systèmes électroniques nomades nécessite une augmentation de… (more)

Subjects/Keywords: Thermique; 3D; TSV; 3D IC; Auto échauffement; Capteur de température; Simulation FEM; Mesure thermoélectrique; Thermal; TSV; 3D IC; Self-heating; Sensor; FEM simulation; Thermoelectric measurement

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APA (6th Edition):

Souare, P. M. (2014). Effets thermiques dans les empilements 3d de puces électroniques : études numériques et expérimentales : Thermal effects in 3d stacks of electronic chip : numerical and experimental studies. (Doctoral Dissertation). Saint-Etienne, EMSE. Retrieved from http://www.theses.fr/2014EMSE0766

Chicago Manual of Style (16th Edition):

Souare, Papa Momar. “Effets thermiques dans les empilements 3d de puces électroniques : études numériques et expérimentales : Thermal effects in 3d stacks of electronic chip : numerical and experimental studies.” 2014. Doctoral Dissertation, Saint-Etienne, EMSE. Accessed September 25, 2020. http://www.theses.fr/2014EMSE0766.

MLA Handbook (7th Edition):

Souare, Papa Momar. “Effets thermiques dans les empilements 3d de puces électroniques : études numériques et expérimentales : Thermal effects in 3d stacks of electronic chip : numerical and experimental studies.” 2014. Web. 25 Sep 2020.

Vancouver:

Souare PM. Effets thermiques dans les empilements 3d de puces électroniques : études numériques et expérimentales : Thermal effects in 3d stacks of electronic chip : numerical and experimental studies. [Internet] [Doctoral dissertation]. Saint-Etienne, EMSE; 2014. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2014EMSE0766.

Council of Science Editors:

Souare PM. Effets thermiques dans les empilements 3d de puces électroniques : études numériques et expérimentales : Thermal effects in 3d stacks of electronic chip : numerical and experimental studies. [Doctoral Dissertation]. Saint-Etienne, EMSE; 2014. Available from: http://www.theses.fr/2014EMSE0766


Université de Grenoble

22. Fourneaud, Ludovic. Caractérisation et modélisation des performances hautes fréquences des réseaux d'interconnexions de circuits avancés 3D : application à la réalisation d'imageurs de nouvelle génération : Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

Le travail de doctorat réalisé s'attache à étudier les nouveaux types d'interconnexions comme les TSV (Through Silicon Via), les lignes de redistribution (RDL) et les… (more)

Subjects/Keywords: 3D-IC; De-embedding; TSV; Copper pillar; Modèle RLCG; Courants de Foucault; Intégration 3D; Caractérisation RF; 3D-IC; De-embedding; TSV; Copper pillar; RLCG model; Eddy current; RF characterisation

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APA (6th Edition):

Fourneaud, L. (2012). Caractérisation et modélisation des performances hautes fréquences des réseaux d'interconnexions de circuits avancés 3D : application à la réalisation d'imageurs de nouvelle génération : Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT071

Chicago Manual of Style (16th Edition):

Fourneaud, Ludovic. “Caractérisation et modélisation des performances hautes fréquences des réseaux d'interconnexions de circuits avancés 3D : application à la réalisation d'imageurs de nouvelle génération : Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed September 25, 2020. http://www.theses.fr/2012GRENT071.

MLA Handbook (7th Edition):

Fourneaud, Ludovic. “Caractérisation et modélisation des performances hautes fréquences des réseaux d'interconnexions de circuits avancés 3D : application à la réalisation d'imageurs de nouvelle génération : Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers.” 2012. Web. 25 Sep 2020.

Vancouver:

Fourneaud L. Caractérisation et modélisation des performances hautes fréquences des réseaux d'interconnexions de circuits avancés 3D : application à la réalisation d'imageurs de nouvelle génération : Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2012GRENT071.

Council of Science Editors:

Fourneaud L. Caractérisation et modélisation des performances hautes fréquences des réseaux d'interconnexions de circuits avancés 3D : application à la réalisation d'imageurs de nouvelle génération : Characterization and modelling of 3D inteconnects HF performance for new generation of 3D imagers. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT071

23. Djomeni Weleguela, Monica Larissa. Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques : Study of through silicon via (TSV) integration realised by MOCVD for 3D stacking of microelectronics components.

Degree: Docteur es, Electronique, microélectronique, photonique, 2014, Université de Strasbourg

Ces dernières années, l’évolution de la taille des circuits intégrés a été dirigée par la loi de Moore conduisant à des noeuds technologiques de 22… (more)

Subjects/Keywords: 3D-IC; TSV; TiN; Cu; IPVD; MOCVD; Barrière; Couche d’accroche; Caractérisation; 3D-IC; TSV; TiN; Cu; IPVD; MOCVD; Barrier layer; Seed layer; Characterization; 621.38

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APA (6th Edition):

Djomeni Weleguela, M. L. (2014). Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques : Study of through silicon via (TSV) integration realised by MOCVD for 3D stacking of microelectronics components. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2014STRAD013

Chicago Manual of Style (16th Edition):

Djomeni Weleguela, Monica Larissa. “Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques : Study of through silicon via (TSV) integration realised by MOCVD for 3D stacking of microelectronics components.” 2014. Doctoral Dissertation, Université de Strasbourg. Accessed September 25, 2020. http://www.theses.fr/2014STRAD013.

MLA Handbook (7th Edition):

Djomeni Weleguela, Monica Larissa. “Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques : Study of through silicon via (TSV) integration realised by MOCVD for 3D stacking of microelectronics components.” 2014. Web. 25 Sep 2020.

Vancouver:

Djomeni Weleguela ML. Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques : Study of through silicon via (TSV) integration realised by MOCVD for 3D stacking of microelectronics components. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2014. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2014STRAD013.

Council of Science Editors:

Djomeni Weleguela ML. Etude de l'intégration de vias traversants réalisés par MOCVD en vue de l'empilement en 3D des composants microélectroniques : Study of through silicon via (TSV) integration realised by MOCVD for 3D stacking of microelectronics components. [Doctoral Dissertation]. Université de Strasbourg; 2014. Available from: http://www.theses.fr/2014STRAD013


UCLA

24. WANG, YAODONG. Mechanical Reliability Challenges in Cu-Sn Microbump for 3D IC Packaging Technology.

Degree: Materials Science and Engineering, 2016, UCLA

 In this thesis, I systematically investigated and discussed the mechanical reliability challenges of Cu-Sn IMC-based microbump from the as-reflowed condition, after multiple reflows, to solid… (more)

Subjects/Keywords: Materials Science; 3D IC; Brittleness; Cu-Sn IMC; Mechanical reliability; Microbump; Packaging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

WANG, Y. (2016). Mechanical Reliability Challenges in Cu-Sn Microbump for 3D IC Packaging Technology. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0xf8f017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

WANG, YAODONG. “Mechanical Reliability Challenges in Cu-Sn Microbump for 3D IC Packaging Technology.” 2016. Thesis, UCLA. Accessed September 25, 2020. http://www.escholarship.org/uc/item/0xf8f017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

WANG, YAODONG. “Mechanical Reliability Challenges in Cu-Sn Microbump for 3D IC Packaging Technology.” 2016. Web. 25 Sep 2020.

Vancouver:

WANG Y. Mechanical Reliability Challenges in Cu-Sn Microbump for 3D IC Packaging Technology. [Internet] [Thesis]. UCLA; 2016. [cited 2020 Sep 25]. Available from: http://www.escholarship.org/uc/item/0xf8f017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

WANG Y. Mechanical Reliability Challenges in Cu-Sn Microbump for 3D IC Packaging Technology. [Thesis]. UCLA; 2016. Available from: http://www.escholarship.org/uc/item/0xf8f017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

25. Yao, Wei. Modeling and Optimization for High-speed Links and 3D IC.

Degree: Electrical Engineering, 2012, UCLA

 The advance of modern integrated circuit (IC) processes has supported increasing date rates on chip-to-chip communications in many consumer and professional applications, such as multimedia… (more)

Subjects/Keywords: Electrical engineering; 3D IC; circuit optimization; Interconnect modeling; signal integrity; through-silicon via

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APA (6th Edition):

Yao, W. (2012). Modeling and Optimization for High-speed Links and 3D IC. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/5f2003tx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yao, Wei. “Modeling and Optimization for High-speed Links and 3D IC.” 2012. Thesis, UCLA. Accessed September 25, 2020. http://www.escholarship.org/uc/item/5f2003tx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yao, Wei. “Modeling and Optimization for High-speed Links and 3D IC.” 2012. Web. 25 Sep 2020.

Vancouver:

Yao W. Modeling and Optimization for High-speed Links and 3D IC. [Internet] [Thesis]. UCLA; 2012. [cited 2020 Sep 25]. Available from: http://www.escholarship.org/uc/item/5f2003tx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yao W. Modeling and Optimization for High-speed Links and 3D IC. [Thesis]. UCLA; 2012. Available from: http://www.escholarship.org/uc/item/5f2003tx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Viswanathan, Vijayaragavan. Modeling and design of 3D Imager IC : Modélisation et conception de circuits intégrés tridimensionnels.

Degree: Docteur es, Electronique, 2012, Ecully, Ecole centrale de Lyon

Pas de résumé

CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade.… (more)

Subjects/Keywords: CMOS; Intégration tridimensionnelle; Fronts de Pareto; CMOS image sensor; 3D imager IC; Pareto front methodology

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APA (6th Edition):

Viswanathan, V. (2012). Modeling and design of 3D Imager IC : Modélisation et conception de circuits intégrés tridimensionnels. (Doctoral Dissertation). Ecully, Ecole centrale de Lyon. Retrieved from http://www.theses.fr/2012ECDL0022

Chicago Manual of Style (16th Edition):

Viswanathan, Vijayaragavan. “Modeling and design of 3D Imager IC : Modélisation et conception de circuits intégrés tridimensionnels.” 2012. Doctoral Dissertation, Ecully, Ecole centrale de Lyon. Accessed September 25, 2020. http://www.theses.fr/2012ECDL0022.

MLA Handbook (7th Edition):

Viswanathan, Vijayaragavan. “Modeling and design of 3D Imager IC : Modélisation et conception de circuits intégrés tridimensionnels.” 2012. Web. 25 Sep 2020.

Vancouver:

Viswanathan V. Modeling and design of 3D Imager IC : Modélisation et conception de circuits intégrés tridimensionnels. [Internet] [Doctoral dissertation]. Ecully, Ecole centrale de Lyon; 2012. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2012ECDL0022.

Council of Science Editors:

Viswanathan V. Modeling and design of 3D Imager IC : Modélisation et conception de circuits intégrés tridimensionnels. [Doctoral Dissertation]. Ecully, Ecole centrale de Lyon; 2012. Available from: http://www.theses.fr/2012ECDL0022


Princeton University

27. Tao, Sen. Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques .

Degree: PhD, 2018, Princeton University

 Since Moore's law was initially presented in 1965, shrinking transistors have driven advances in integrated circuits (ICs), resulting in tremendous innovations and increased capacity of… (more)

Subjects/Keywords: 3D IC; analog-to-digital converter; error correction code; integrated circuit; statistical distribution

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tao, S. (2018). Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01d504rp09c

Chicago Manual of Style (16th Edition):

Tao, Sen. “Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques .” 2018. Doctoral Dissertation, Princeton University. Accessed September 25, 2020. http://arks.princeton.edu/ark:/88435/dsp01d504rp09c.

MLA Handbook (7th Edition):

Tao, Sen. “Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques .” 2018. Web. 25 Sep 2020.

Vancouver:

Tao S. Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2020 Sep 25]. Available from: http://arks.princeton.edu/ark:/88435/dsp01d504rp09c.

Council of Science Editors:

Tao S. Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01d504rp09c


Georgia Tech

28. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 25, 2020. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 25 Sep 2020.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810

29. Yang, Ping-Lin. Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security.

Degree: 2017, University of California – eScholarship, University of California

 With the continuous demands on integrating more functions and devices on a single chip, the technology has been evolving along the scaling path for decades.… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Engineering; 3D IC; Dynamic Reconfigurable Computing; Hardware Security; Monolithic 3D; Physical Design; VeSFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, P. (2017). Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/5s9833kz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Ping-Lin. “Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security.” 2017. Thesis, University of California – eScholarship, University of California. Accessed September 25, 2020. http://www.escholarship.org/uc/item/5s9833kz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Ping-Lin. “Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security.” 2017. Web. 25 Sep 2020.

Vancouver:

Yang P. Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security. [Internet] [Thesis]. University of California – eScholarship, University of California; 2017. [cited 2020 Sep 25]. Available from: http://www.escholarship.org/uc/item/5s9833kz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang P. Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security. [Thesis]. University of California – eScholarship, University of California; 2017. Available from: http://www.escholarship.org/uc/item/5s9833kz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

30. Chang, Kyungwook. Design and tool solutions for energy-efficient reliable monolithic 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of this dissertation is to analyze and identify the benefits and challenges of energy-efficient and reliable monolithic 3D (M3D) ICs, and to develop… (more)

Subjects/Keywords: Monolithic 3D IC; CAD; Physical design; Low power design; High performance design; Power supply integrity; Deep neural network

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, K. (2019). Design and tool solutions for energy-efficient reliable monolithic 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62672

Chicago Manual of Style (16th Edition):

Chang, Kyungwook. “Design and tool solutions for energy-efficient reliable monolithic 3D ICs.” 2019. Doctoral Dissertation, Georgia Tech. Accessed September 25, 2020. http://hdl.handle.net/1853/62672.

MLA Handbook (7th Edition):

Chang, Kyungwook. “Design and tool solutions for energy-efficient reliable monolithic 3D ICs.” 2019. Web. 25 Sep 2020.

Vancouver:

Chang K. Design and tool solutions for energy-efficient reliable monolithic 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1853/62672.

Council of Science Editors:

Chang K. Design and tool solutions for energy-efficient reliable monolithic 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62672

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