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You searched for subject:(3D IC Package). Showing records 1 – 2 of 2 total matches.

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NSYSU

1. Ho, Cheng-you. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

This paper presents a set of novel scheme and corresponding methods for Test Interposer Interconnects. Testing interposer is difficult due to the large number of interconnets to be tested and only small number of test access ports available. Previous methods for PRE-BOND interposer testing can only achieve limited fault coverage for open faults. We propose to include a test interposer that is aligned with the target interposer under test in the testing process. Combining these two interposers as a pair will provide access to interposer nets that are not normally accessible; thus, all interposer interconnects become testable under our proposed test scheme. The experimental results show our scheme and methods are effective with all 100% fault testability under both open and short faults. We propose one base test interposer construction (BTIC) algorithm for both open and short faults in [16]. This paper provides two improved BTIC methods. First, Optimized Test Interposer Construction (OTIC) for open fault; Second, Integrated Optimized Test Interposer Construction (ITIC). OTIC outperforms BTIC in wirelength averagely 14.80X for open fault; ITIC integrates two test interposers in BTIC into ONLY ONE test interposer so we can test open fault and short fault simultaneously with only one test interposer. Also, ITIC outperform BTIC in wirelength averagely 4.50X for open fault and 7.08X for short fault. In test time (#TestSession), OTIC, ITIC, and BTIC are in constant level for open fault, OTIC and BTIC only need 1 TestSession; ITIC needs four. For short fault, ITIC outperform BTIC 147.75X. Advisors/Committee Members: Shiann-Rong Kuang (chair), Chua-Chin Wang (chair), Wei-Kuang Lai (chair), Jwu-E Chen (chair), Shu-Min Li (committee member).

Subjects/Keywords: 3D Stack; 3D Package; 2.5D; 3D IC; Interposer; Through-Silicon Via

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, C. (2014). An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Cheng-you. “An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.” 2014. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Cheng-you. “An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.” 2014. Web. 04 Mar 2021.

Vancouver:

Ho C. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho C. An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1027114-003118

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Wang, Ming-Han. Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2014, NSYSU

Polymer material tends to absorb moisture of environment to cause volume swelling among various materials of electronic package, such as underfill and substrate. The residual moisture of the package would also be vaporized into vapor phase in the reflow process. These phenomena render expansion mismatch and stress concentration at the interface between each components. If stress induced by moisture, vapor pressure and temperature up to mechanical strength, the product have the risk to damage and affect the operation. This paper adopt the finite element software, ANSYS v14.5, to investigate moisture diffusion and structure effects of hygro-thermal-vapor pressure coupling. This study is divided into two parts: First part is about 3D IC package. Second part is about 2.5D IC package. In 3D IC research, whether the mold compound covered and through silicon vias, micro-bumps are discussed under moisture, vapor pressure and temperature effects. In 2.5D IC research, the traditional inorganic passivation layer, Si3N4, is analyzed, in addition, the low-cost organic material is also investigated. Besides, the material properies of organic material will have a sharply change after reflow temperature up to the glass transition temperature (Tg). This paper also focus on this issue and compare the results of these two advanced package under hygro-thermal-vapor pressure coupling. Advisors/Committee Members: Chung-Ting Wang (chair), Ben-Je Lwo (chair), Sheng-Chih Shen (chair), Yeong-Shu Chen (chair), Mei-Ling Wu (committee member).

Subjects/Keywords: Finite element; Glass transition temperature; Vapor pressure; Organic passivation; Moisture; 2.5D IC Package; 3D IC Package

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, M. (2014). Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ming-Han. “Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects.” 2014. Thesis, NSYSU. Accessed March 04, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ming-Han. “Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects.” 2014. Web. 04 Mar 2021.

Vancouver:

Wang M. Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang M. Stress and Warpage Analyses on the 3D and 2.5D ICs with TSV Structure under Thermal and Moisture Effects. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102114-144116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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