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NSYSU

1.
Chen, Guan-Ting.
A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, *2b*/*Cycle* Combine with Alternate 1b/* Cycle*.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed, the 2b/cycle conversion is adapted in the conversion of the upper bits. Since three comparators are required to perform the 2b/cycle conversion, it may cause the increase of the error probability. Therefore, the proposed architecture adapts the non-binary correction technique in the upper bits to tolerate fault error and hence correct the error. In the lower bit conversion, a 1b/cycle conversion is implmented to increase the accuracy. Moreover, the architecture also adopted the alternate technique in lower bit conversion to improve the conversion efficiency. This technique not only uses the comparators more efficiently, but also relaxing the issue of the longer comparison time in the lower bit conversions. At last, a redundant bit is added in the lower bits to increase the fault tolerance capability of the lower bits.
This thesis implements a 10-bit analog-to-digital converter with 100MHz sampling frequency by using the TSMC 90nm process technology. For the static analysis, the DNL and INL are +1.248 / -0.750 LSB and +1.679 / -1.677 LSB, respectively. For the dynamic analysis, the SFDR and SNDR at the Nyquist rate are 62.76 dB and 56.099 dB. The ENOB is 9.026 bit, the power consumption is 2.397 mW and FoM is 45.98 fJ / conv.-step.
*Advisors/Committee Members: Ko-Chi Kuo (committee member), Xin-Yu Shih (chair), Shiann-Rong Kuang (chair).*

Subjects/Keywords: 2b/Cycle; Non-binary Error Correction; Alternate Technique; Successive Approximation Register; Analog to Digital Converter

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Chen, G. (2018). A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Thesis, NSYSU. Accessed November 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Web. 13 Nov 2019.

Vancouver:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Nov 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

2.
Bai, Je-Wei.
A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per *cycle* and non-binary digital error correction.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This circuit can be used in the applications for the wireless communications.
In the circuit design, in order to achieve a higher operation speed and better conversion precision, a 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction architecture is proposed by adapting the dynamic comparator techniques to reduce static power consumption. In order to achieve the high-speed operation requirement, the non-binary capacitor array switching and digital correction methods are adapted and it can increase the fault tolerant capability by comparing capacitance before they are stabled. On the other hand, the symmetrical bootstrapping switch is implemented to control the front end sampling switch to improve the conversion speed of the proposed analog-to-digital converter, and thus achieve lowering the non-linearity effects on the sample and hold circuit due to the lowered voltage operation.
This paper presents 80 MS/s and 10 bit analog-to-digital converter, which DNL is + 0.997-1 LSB, INL is + 1.351 / -1.464 LSB, SFDR and SNDR at the Nyquist rate are 65.453 dB and 56.327 dB, ENOB is 9.064 bit, power consumption is 2.19 mW, finally FOM of 51 fJ / conv.-step.
Keywords: Analog to Digital ConverterãSuccessive Approximation Registerã2b/Cycleãdigital error correctionãnon-binary digital error correction
*Advisors/Committee Members: Xin-Yu Shih (chair), ko-chi kuo (committee member), Shiarn-Rong Kuang (chair).*

Subjects/Keywords: non-binary digital error correction; digital error correction; 2b/Cycle; Successive Approximation Register; Analog to Digital Converter

Record Details Similar Records

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Bai, J. (2016). A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Thesis, NSYSU. Accessed November 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Web. 13 Nov 2019.

Vancouver:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Nov 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Not specified: Masters Thesis or Doctoral Dissertation