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You searched for subject:(2D Torus VLSI layout sequence pair Module placement). Showing records 1 – 30 of 10963 total matches.

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1. 柴田, 貴之. 2次元トーラス空間における矩形配置のコード表現と最適化.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:金子峰雄

情報科学研究科

修士

Subjects/Keywords: 2次元トーラス,VLSIレイアウト,シーケンスペア,矩形配置; 2D Torus,VLSI layout,sequence-pair,Module placement

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

柴田, . (n.d.). 2次元トーラス空間における矩形配置のコード表現と最適化. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/4353

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

柴田, 貴之. “2次元トーラス空間における矩形配置のコード表現と最適化.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed January 20, 2021. http://hdl.handle.net/10119/4353.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

柴田, 貴之. “2次元トーラス空間における矩形配置のコード表現と最適化.” Web. 20 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

柴田 . 2次元トーラス空間における矩形配置のコード表現と最適化. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10119/4353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

柴田 . 2次元トーラス空間における矩形配置のコード表現と最適化. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/4353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


University of Cincinnati

2. BADAOUI, RAOUL. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure,… (more)

Subjects/Keywords: vlsi; analog vlsi; routing; placement; extraction; pre-layout extraction

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APA (6th Edition):

BADAOUI, R. (2005). APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275

Chicago Manual of Style (16th Edition):

BADAOUI, RAOUL. “APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

MLA Handbook (7th Edition):

BADAOUI, RAOUL. “APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.” 2005. Web. 20 Jan 2021.

Vancouver:

BADAOUI R. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

Council of Science Editors:

BADAOUI R. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275


University of Waterloo

3. Etawil, Hussein. Convex Optimization and Utility Theory: New Trends in VLSI Circuit Layout.

Degree: 1999, University of Waterloo

 The design of modern integrated circuits is overwhelmingly complicated due to the enormous number of cells in a typical modern circuit. To deal with this… (more)

Subjects/Keywords: Electrical & Computer Engineering; VLSI; Circuit Layout; Placement; Routing

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APA (6th Edition):

Etawil, H. (1999). Convex Optimization and Utility Theory: New Trends in VLSI Circuit Layout. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/813

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Etawil, Hussein. “Convex Optimization and Utility Theory: New Trends in VLSI Circuit Layout.” 1999. Thesis, University of Waterloo. Accessed January 20, 2021. http://hdl.handle.net/10012/813.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Etawil, Hussein. “Convex Optimization and Utility Theory: New Trends in VLSI Circuit Layout.” 1999. Web. 20 Jan 2021.

Vancouver:

Etawil H. Convex Optimization and Utility Theory: New Trends in VLSI Circuit Layout. [Internet] [Thesis]. University of Waterloo; 1999. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10012/813.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Etawil H. Convex Optimization and Utility Theory: New Trends in VLSI Circuit Layout. [Thesis]. University of Waterloo; 1999. Available from: http://hdl.handle.net/10012/813

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

4. Liu, Qi. A Sequence-Pair and Mixed Integer Programming Based Methodology for the Facility Layout Problem.

Degree: PhD, Industrial and Systems Engineering, 2004, Virginia Tech

 The facility layout problem (FLP) is one of the most important and challenging problems in both the operations research and industrial engineering research domains. In… (more)

Subjects/Keywords: Mixed Integer Programming; Sequence-Pair Representation; Facility Layout Problem

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APA (6th Edition):

Liu, Q. (2004). A Sequence-Pair and Mixed Integer Programming Based Methodology for the Facility Layout Problem. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29780

Chicago Manual of Style (16th Edition):

Liu, Qi. “A Sequence-Pair and Mixed Integer Programming Based Methodology for the Facility Layout Problem.” 2004. Doctoral Dissertation, Virginia Tech. Accessed January 20, 2021. http://hdl.handle.net/10919/29780.

MLA Handbook (7th Edition):

Liu, Qi. “A Sequence-Pair and Mixed Integer Programming Based Methodology for the Facility Layout Problem.” 2004. Web. 20 Jan 2021.

Vancouver:

Liu Q. A Sequence-Pair and Mixed Integer Programming Based Methodology for the Facility Layout Problem. [Internet] [Doctoral dissertation]. Virginia Tech; 2004. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10919/29780.

Council of Science Editors:

Liu Q. A Sequence-Pair and Mixed Integer Programming Based Methodology for the Facility Layout Problem. [Doctoral Dissertation]. Virginia Tech; 2004. Available from: http://hdl.handle.net/10919/29780

5. 三輪, 剛史. ソフトモジュールを含む配置問題の一解法.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:平石 邦彦

情報科学研究科

修士

Subjects/Keywords: VLSI, レイアウトデザイン, フロアプラン, 配置, ソフトモジュール; VLSI, layout design, floorplan, placement, soft-mo

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APA (6th Edition):

三輪, . (n.d.). ソフトモジュールを含む配置問題の一解法. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/1061

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

三輪, 剛史. “ソフトモジュールを含む配置問題の一解法.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed January 20, 2021. http://hdl.handle.net/10119/1061.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

三輪, 剛史. “ソフトモジュールを含む配置問題の一解法.” Web. 20 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

三輪 . ソフトモジュールを含む配置問題の一解法. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10119/1061.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

三輪 . ソフトモジュールを含む配置問題の一解法. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/1061

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Texas A&M University

6. Shah, Pratik Jitendra. Case studies on lithography-friendly vlsi circuit layout.

Degree: MS, Computer Engineering, 2009, Texas A&M University

 Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered… (more)

Subjects/Keywords: Lithography; VLSI; layout

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shah, P. J. (2009). Case studies on lithography-friendly vlsi circuit layout. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3120

Chicago Manual of Style (16th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Masters Thesis, Texas A&M University. Accessed January 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-3120.

MLA Handbook (7th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Web. 20 Jan 2021.

Vancouver:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Internet] [Masters thesis]. Texas A&M University; 2009. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Council of Science Editors:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Masters Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120


University of Texas – Austin

7. Pak, Jiwoo. Electromigration modeling and layout optimization for advanced VLSI.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Electromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional… (more)

Subjects/Keywords: Electromigration; VLSI; Layout; Physical Design; EDA

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APA (6th Edition):

Pak, J. (2014). Electromigration modeling and layout optimization for advanced VLSI. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/30944

Chicago Manual of Style (16th Edition):

Pak, Jiwoo. “Electromigration modeling and layout optimization for advanced VLSI.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed January 20, 2021. http://hdl.handle.net/2152/30944.

MLA Handbook (7th Edition):

Pak, Jiwoo. “Electromigration modeling and layout optimization for advanced VLSI.” 2014. Web. 20 Jan 2021.

Vancouver:

Pak J. Electromigration modeling and layout optimization for advanced VLSI. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2152/30944.

Council of Science Editors:

Pak J. Electromigration modeling and layout optimization for advanced VLSI. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/30944

8. Kumar, Anurag, 1983-. Placement for structured ASICs.

Degree: MSin Engineering, Electrical and Computer Engineering, 2009, University of Texas – Austin

 Structured ASICs provide an exciting middle-ground between ASIC and FPGA design styles because they provide trade-off between the high per- formance of ASIC design and… (more)

Subjects/Keywords: Placement; Vlsi

Placement for Structured ASICs Anurag Kumar, M.S.E. The University of Texas at Austin… …placement stage must be aware of the modularity of the structured ASIC architecture. This work… …describes a novel solution to placement of structured ASICs. Integer linear programming… …stages to speed-up the detailed placement stage. Our methods show overall wirelength reduction… …Our Placement Flow 4.1 Global Placement . . . . . . . 4.2 Global Refinement… 

Page 1 Page 2 Page 3 Page 4 Page 5 Sample image

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, Anurag, 1. (2009). Placement for structured ASICs. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2009-12-430

Chicago Manual of Style (16th Edition):

Kumar, Anurag, 1983-. “Placement for structured ASICs.” 2009. Masters Thesis, University of Texas – Austin. Accessed January 20, 2021. http://hdl.handle.net/2152/ETD-UT-2009-12-430.

MLA Handbook (7th Edition):

Kumar, Anurag, 1983-. “Placement for structured ASICs.” 2009. Web. 20 Jan 2021.

Vancouver:

Kumar, Anurag 1. Placement for structured ASICs. [Internet] [Masters thesis]. University of Texas – Austin; 2009. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-430.

Council of Science Editors:

Kumar, Anurag 1. Placement for structured ASICs. [Masters Thesis]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-430


University of Cincinnati

9. Mukherjee, Tuhin. Cluster Shaping: A novel optimization technique for large scale VLSI placement.

Degree: MS, Engineering and Applied Science: Electrical Engineering, 2014, University of Cincinnati

 The process of VLSI placement has been under constant evolution since its early days when the number of cells was ~100 to modern designs containing… (more)

Subjects/Keywords: Engineering; VLSI placement; clustering; shaping; Timing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukherjee, T. (2014). Cluster Shaping: A novel optimization technique for large scale VLSI placement. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006

Chicago Manual of Style (16th Edition):

Mukherjee, Tuhin. “Cluster Shaping: A novel optimization technique for large scale VLSI placement.” 2014. Masters Thesis, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006.

MLA Handbook (7th Edition):

Mukherjee, Tuhin. “Cluster Shaping: A novel optimization technique for large scale VLSI placement.” 2014. Web. 20 Jan 2021.

Vancouver:

Mukherjee T. Cluster Shaping: A novel optimization technique for large scale VLSI placement. [Internet] [Masters thesis]. University of Cincinnati; 2014. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006.

Council of Science Editors:

Mukherjee T. Cluster Shaping: A novel optimization technique for large scale VLSI placement. [Masters Thesis]. University of Cincinnati; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006


University of Minnesota

10. Agashiwala, Nimish. Timing Driven Analytical Placement for FPGA.

Degree: MS, Electrical Engineering, 2015, University of Minnesota

 Conventional Simulated Annealing (SA) based placement methods for FPGAs give best results in terms of wirelength and critical path delay. The runtime for these SA… (more)

Subjects/Keywords: Analytical; FPGA; Placement; Quadratic placement; Timing Driven; VLSI CAD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agashiwala, N. (2015). Timing Driven Analytical Placement for FPGA. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/175486

Chicago Manual of Style (16th Edition):

Agashiwala, Nimish. “Timing Driven Analytical Placement for FPGA.” 2015. Masters Thesis, University of Minnesota. Accessed January 20, 2021. http://hdl.handle.net/11299/175486.

MLA Handbook (7th Edition):

Agashiwala, Nimish. “Timing Driven Analytical Placement for FPGA.” 2015. Web. 20 Jan 2021.

Vancouver:

Agashiwala N. Timing Driven Analytical Placement for FPGA. [Internet] [Masters thesis]. University of Minnesota; 2015. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/11299/175486.

Council of Science Editors:

Agashiwala N. Timing Driven Analytical Placement for FPGA. [Masters Thesis]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/175486

11. 小川, 智之. 周期的繰り返し矩形配置の解表現と配置最適化.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:金子 峰雄

情報科学研究科

修士

Subjects/Keywords: フロアプラン,シーケンスペア,コード表現,非スライス配置; floor plan, sequence pair, non-slicing placement

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

小川, . (n.d.). 周期的繰り返し矩形配置の解表現と配置最適化. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/1929

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

小川, 智之. “周期的繰り返し矩形配置の解表現と配置最適化.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed January 20, 2021. http://hdl.handle.net/10119/1929.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

小川, 智之. “周期的繰り返し矩形配置の解表現と配置最適化.” Web. 20 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

小川 . 周期的繰り返し矩形配置の解表現と配置最適化. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10119/1929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

小川 . 周期的繰り返し矩形配置の解表現と配置最適化. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/1929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


University of South Florida

12. Fernando, Pradeep R. Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs.

Degree: 2006, University of South Florida

 Dramatic improvements in circuit integration technologies have resulted in a huge increase in the complexity of circuits that can be fabricated on a single integrated… (more)

Subjects/Keywords: Physical Design; 3D Integrated Circuits; Evolutionary Search; Placement; Sequence Pair; American Studies; Arts and Humanities

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APA (6th Edition):

Fernando, P. R. (2006). Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/3936

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fernando, Pradeep R. “Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs.” 2006. Thesis, University of South Florida. Accessed January 20, 2021. https://scholarcommons.usf.edu/etd/3936.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fernando, Pradeep R. “Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs.” 2006. Web. 20 Jan 2021.

Vancouver:

Fernando PR. Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs. [Internet] [Thesis]. University of South Florida; 2006. [cited 2021 Jan 20]. Available from: https://scholarcommons.usf.edu/etd/3936.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fernando PR. Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs. [Thesis]. University of South Florida; 2006. Available from: https://scholarcommons.usf.edu/etd/3936

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

13. Guex, Jerson Paulo. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.

Degree: 2013, Universidade do Rio Grande do Sul

Este trabalho visa explorar técnicas de projeto de células que possibilitem a minimização dos efeitos da variabilidade de processo sobre o comportamento elétrico dos circuitos… (more)

Subjects/Keywords: Microeletrônica; Cell layout; Process variability; Vlsi; Transistores; DFM; Transistor folding; Microelectronics

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APA (6th Edition):

Guex, J. P. (2013). Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/78529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guex, Jerson Paulo. “Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed January 20, 2021. http://hdl.handle.net/10183/78529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guex, Jerson Paulo. “Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.” 2013. Web. 20 Jan 2021.

Vancouver:

Guex JP. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10183/78529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guex JP. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/78529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

14. Adya, Saurabh N. Unification of VLSI placement and floorplanning.

Degree: PhD, Electrical engineering, 2004, University of Michigan

 As VLSI circuits become larger and more complex, the need to improve design automation tools becomes more urgent. Interconnect effects dominate performance and power in… (more)

Subjects/Keywords: Cad; Floorplanning; Placement; Unification; Vlsi

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APA (6th Edition):

Adya, S. N. (2004). Unification of VLSI placement and floorplanning. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124607

Chicago Manual of Style (16th Edition):

Adya, Saurabh N. “Unification of VLSI placement and floorplanning.” 2004. Doctoral Dissertation, University of Michigan. Accessed January 20, 2021. http://hdl.handle.net/2027.42/124607.

MLA Handbook (7th Edition):

Adya, Saurabh N. “Unification of VLSI placement and floorplanning.” 2004. Web. 20 Jan 2021.

Vancouver:

Adya SN. Unification of VLSI placement and floorplanning. [Internet] [Doctoral dissertation]. University of Michigan; 2004. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2027.42/124607.

Council of Science Editors:

Adya SN. Unification of VLSI placement and floorplanning. [Doctoral Dissertation]. University of Michigan; 2004. Available from: http://hdl.handle.net/2027.42/124607


Virginia Commonwealth University

15. Berlier, Jacob A. A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms.

Degree: MS, Engineering, 2011, Virginia Commonwealth University

 The design and implementation of today's most advanced VLSI circuits and multi-layer printed circuit boards would not be possible without automated design tools that assist… (more)

Subjects/Keywords: cloud computing; parallel genetic algorithm; placement; routing; vlsi; pcb; Engineering

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APA (6th Edition):

Berlier, J. A. (2011). A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms. (Thesis). Virginia Commonwealth University. Retrieved from https://doi.org/10.25772/5190-YT63 ; https://scholarscompass.vcu.edu/etd/2406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Berlier, Jacob A. “A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms.” 2011. Thesis, Virginia Commonwealth University. Accessed January 20, 2021. https://doi.org/10.25772/5190-YT63 ; https://scholarscompass.vcu.edu/etd/2406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Berlier, Jacob A. “A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms.” 2011. Web. 20 Jan 2021.

Vancouver:

Berlier JA. A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms. [Internet] [Thesis]. Virginia Commonwealth University; 2011. [cited 2021 Jan 20]. Available from: https://doi.org/10.25772/5190-YT63 ; https://scholarscompass.vcu.edu/etd/2406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Berlier JA. A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms. [Thesis]. Virginia Commonwealth University; 2011. Available from: https://doi.org/10.25772/5190-YT63 ; https://scholarscompass.vcu.edu/etd/2406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Pattison, Ryan. A Completely Parallelizable Analytic Algorithm for Fast and Scalable FPGA Placement.

Degree: MS, School of Computer Science, 2015, University of Guelph

 Modern Field Programmable Gate Arrays (FPGAs) have millions of reconfigurable components capable of implementing complex system on a chip designs. Leveraging the capabilities of FPGAs… (more)

Subjects/Keywords: FPGA; Placement; VLSI; CAD

…Analytic Placement Stages . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 Finding the… …36 3.1 StarPlace Placement Flow . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1… …Jacobi-StarPlace Placement Flow . . . . . . . . . . . . . . . . . . . . 49 4.2 Assigning… …67 viii List of Algorithms 1 StarPlace SOR Placement… …Partition Legalization Method . . . . . . . . . . . . . . 47 6 StarPlace Jacobi Placement… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pattison, R. (2015). A Completely Parallelizable Analytic Algorithm for Fast and Scalable FPGA Placement. (Masters Thesis). University of Guelph. Retrieved from https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9082

Chicago Manual of Style (16th Edition):

Pattison, Ryan. “A Completely Parallelizable Analytic Algorithm for Fast and Scalable FPGA Placement.” 2015. Masters Thesis, University of Guelph. Accessed January 20, 2021. https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9082.

MLA Handbook (7th Edition):

Pattison, Ryan. “A Completely Parallelizable Analytic Algorithm for Fast and Scalable FPGA Placement.” 2015. Web. 20 Jan 2021.

Vancouver:

Pattison R. A Completely Parallelizable Analytic Algorithm for Fast and Scalable FPGA Placement. [Internet] [Masters thesis]. University of Guelph; 2015. [cited 2021 Jan 20]. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9082.

Council of Science Editors:

Pattison R. A Completely Parallelizable Analytic Algorithm for Fast and Scalable FPGA Placement. [Masters Thesis]. University of Guelph; 2015. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9082

17. Yilmaz, Eftun. Benchmarking of Optimization Modules for Two Wind Farm Design Software Tools.

Degree: Energy and Environment, 2012, Gotland University

  Optimization of wind farm layout is an expensive and complex task involving several engineering challenges. The layout of any wind farm directly impacts profitability… (more)

Subjects/Keywords: wind energy; optimization; wind farm layout; wind turbine placement; efficiency

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yilmaz, E. (2012). Benchmarking of Optimization Modules for Two Wind Farm Design Software Tools. (Thesis). Gotland University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hgo:diva-1946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yilmaz, Eftun. “Benchmarking of Optimization Modules for Two Wind Farm Design Software Tools.” 2012. Thesis, Gotland University. Accessed January 20, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hgo:diva-1946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yilmaz, Eftun. “Benchmarking of Optimization Modules for Two Wind Farm Design Software Tools.” 2012. Web. 20 Jan 2021.

Vancouver:

Yilmaz E. Benchmarking of Optimization Modules for Two Wind Farm Design Software Tools. [Internet] [Thesis]. Gotland University; 2012. [cited 2021 Jan 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hgo:diva-1946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yilmaz E. Benchmarking of Optimization Modules for Two Wind Farm Design Software Tools. [Thesis]. Gotland University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hgo:diva-1946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Manchester

18. Mehdi, Akeel Ramadan. Purity relative to classes of finitely presented modules.

Degree: PhD, 2013, University of Manchester

 Any set of finitely presented left modules defines a relative purity for left modules and also apurity for right modules. Purities defined by various classes… (more)

Subjects/Keywords: 512; purity, pure-injective, pure projective, dual module, (m,n)-purity, finite-dimensional algebra, Auslander-Reiten translate, Ziegler closure, full support closure, tame hereditary algebra, adic module, generic module, Prüfer module, definable classes, almost dual pair, cotorsion pair, S-cotorsion pair

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APA (6th Edition):

Mehdi, A. R. (2013). Purity relative to classes of finitely presented modules. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/purity-relative-to-classes-of-finitely-presented-modules(6ebd54f0-7b74-4f13-abb9-3f3594f93f6a).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.576899

Chicago Manual of Style (16th Edition):

Mehdi, Akeel Ramadan. “Purity relative to classes of finitely presented modules.” 2013. Doctoral Dissertation, University of Manchester. Accessed January 20, 2021. https://www.research.manchester.ac.uk/portal/en/theses/purity-relative-to-classes-of-finitely-presented-modules(6ebd54f0-7b74-4f13-abb9-3f3594f93f6a).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.576899.

MLA Handbook (7th Edition):

Mehdi, Akeel Ramadan. “Purity relative to classes of finitely presented modules.” 2013. Web. 20 Jan 2021.

Vancouver:

Mehdi AR. Purity relative to classes of finitely presented modules. [Internet] [Doctoral dissertation]. University of Manchester; 2013. [cited 2021 Jan 20]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/purity-relative-to-classes-of-finitely-presented-modules(6ebd54f0-7b74-4f13-abb9-3f3594f93f6a).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.576899.

Council of Science Editors:

Mehdi AR. Purity relative to classes of finitely presented modules. [Doctoral Dissertation]. University of Manchester; 2013. Available from: https://www.research.manchester.ac.uk/portal/en/theses/purity-relative-to-classes-of-finitely-presented-modules(6ebd54f0-7b74-4f13-abb9-3f3594f93f6a).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.576899

19. Hilgers, Brandon. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.

Degree: MS, Electrical Engineering, 2015, Cal Poly

  This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates… (more)

Subjects/Keywords: SRAM; Compiler; Memory; Automated; Layout; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hilgers, B. (2015). SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125

Chicago Manual of Style (16th Edition):

Hilgers, Brandon. “SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.” 2015. Masters Thesis, Cal Poly. Accessed January 20, 2021. https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125.

MLA Handbook (7th Edition):

Hilgers, Brandon. “SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies.” 2015. Web. 20 Jan 2021.

Vancouver:

Hilgers B. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. [Internet] [Masters thesis]. Cal Poly; 2015. [cited 2021 Jan 20]. Available from: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125.

Council of Science Editors:

Hilgers B. SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies. [Masters Thesis]. Cal Poly; 2015. Available from: https://digitalcommons.calpoly.edu/theses/1423 ; 10.15368/theses.2015.125


Virginia Tech

20. He, Yingchun. VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip.

Degree: MS, Electrical and Computer Engineering, 1998, Virginia Tech

 Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct… (more)

Subjects/Keywords: run-time configurable computing; layout; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

He, Y. (1998). VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36845

Chicago Manual of Style (16th Edition):

He, Yingchun. “VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip.” 1998. Masters Thesis, Virginia Tech. Accessed January 20, 2021. http://hdl.handle.net/10919/36845.

MLA Handbook (7th Edition):

He, Yingchun. “VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip.” 1998. Web. 20 Jan 2021.

Vancouver:

He Y. VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip. [Internet] [Masters thesis]. Virginia Tech; 1998. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10919/36845.

Council of Science Editors:

He Y. VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip. [Masters Thesis]. Virginia Tech; 1998. Available from: http://hdl.handle.net/10919/36845

21. -0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Very-large-scale integrated (VLSI) circuits have entered the era of 1x nm technology node and beyond. Emerging manufacturing processes such as multiple patterning lithography, E-beam lithography… (more)

Subjects/Keywords: VLSI design automation; Design for manufacturability; Machine learning; Physical design; Post-layout optimization; Mask synthesis

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APA (6th Edition):

-0977-2774. (2018). Bridging design and manufacturing gap through machine learning and machine-generated layout. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65900

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-0977-2774. “Bridging design and manufacturing gap through machine learning and machine-generated layout.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed January 20, 2021. http://hdl.handle.net/2152/65900.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-0977-2774. “Bridging design and manufacturing gap through machine learning and machine-generated layout.” 2018. Web. 20 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2152/65900.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/65900

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Universidade do Rio Grande do Sul

22. Sawicki, Sandro. Particionamento de células e pads de I/O em circuitos VLSI 3D.

Degree: 2009, Universidade do Rio Grande do Sul

A etapa de particionamento em circuitos VLSI 3D é fundamental na distribuição de células e blocos para as camadas do circuito, além de auxiliar na… (more)

Subjects/Keywords: 3D VLSI integrated circuits; Microeletrônica; 3D; Partitioning; Vlsi; Placement; I/O pads; Projeto : Circuitos integrados; Circuitos integrados; CAD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sawicki, S. (2009). Particionamento de células e pads de I/O em circuitos VLSI 3D. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/26502

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sawicki, Sandro. “Particionamento de células e pads de I/O em circuitos VLSI 3D.” 2009. Thesis, Universidade do Rio Grande do Sul. Accessed January 20, 2021. http://hdl.handle.net/10183/26502.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sawicki, Sandro. “Particionamento de células e pads de I/O em circuitos VLSI 3D.” 2009. Web. 20 Jan 2021.

Vancouver:

Sawicki S. Particionamento de células e pads de I/O em circuitos VLSI 3D. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2009. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10183/26502.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sawicki S. Particionamento de células e pads de I/O em circuitos VLSI 3D. [Thesis]. Universidade do Rio Grande do Sul; 2009. Available from: http://hdl.handle.net/10183/26502

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Ledoux, Christophe. Conception par optimisation de convertisseurs statiques pour applications mono-convertisseur multi-machines séquentielles ; contribution à l'optimisation du placement-routage. : Conception by optimization of static converters for applications mono-converter sequential multi-machines; contribution to the optimization of the placement-layout.

Degree: Docteur es, Energie (SPI), 2012, Supélec

Les systèmes électriques sont de plus en plus présents dans les applications embarquées. Ils remplacent les systèmes mécaniques ou hydrauliques. Dans le cas du remplacement… (more)

Subjects/Keywords: Pré-dimensionnement; Optimisation; Placement-routage; Mono-convertisseur multi-machines; Pre-sizing; Optimization; Placement-layout; Mono-converter multi-machines; 378.242

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APA (6th Edition):

Ledoux, C. (2012). Conception par optimisation de convertisseurs statiques pour applications mono-convertisseur multi-machines séquentielles ; contribution à l'optimisation du placement-routage. : Conception by optimization of static converters for applications mono-converter sequential multi-machines; contribution to the optimization of the placement-layout. (Doctoral Dissertation). Supélec. Retrieved from http://www.theses.fr/2012SUPL0024

Chicago Manual of Style (16th Edition):

Ledoux, Christophe. “Conception par optimisation de convertisseurs statiques pour applications mono-convertisseur multi-machines séquentielles ; contribution à l'optimisation du placement-routage. : Conception by optimization of static converters for applications mono-converter sequential multi-machines; contribution to the optimization of the placement-layout.” 2012. Doctoral Dissertation, Supélec. Accessed January 20, 2021. http://www.theses.fr/2012SUPL0024.

MLA Handbook (7th Edition):

Ledoux, Christophe. “Conception par optimisation de convertisseurs statiques pour applications mono-convertisseur multi-machines séquentielles ; contribution à l'optimisation du placement-routage. : Conception by optimization of static converters for applications mono-converter sequential multi-machines; contribution to the optimization of the placement-layout.” 2012. Web. 20 Jan 2021.

Vancouver:

Ledoux C. Conception par optimisation de convertisseurs statiques pour applications mono-convertisseur multi-machines séquentielles ; contribution à l'optimisation du placement-routage. : Conception by optimization of static converters for applications mono-converter sequential multi-machines; contribution to the optimization of the placement-layout. [Internet] [Doctoral dissertation]. Supélec; 2012. [cited 2021 Jan 20]. Available from: http://www.theses.fr/2012SUPL0024.

Council of Science Editors:

Ledoux C. Conception par optimisation de convertisseurs statiques pour applications mono-convertisseur multi-machines séquentielles ; contribution à l'optimisation du placement-routage. : Conception by optimization of static converters for applications mono-converter sequential multi-machines; contribution to the optimization of the placement-layout. [Doctoral Dissertation]. Supélec; 2012. Available from: http://www.theses.fr/2012SUPL0024


Virginia Tech

24. Watt, Grace R. Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module.

Degree: MS, Electrical Engineering, 2020, Virginia Tech

 This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to… (more)

Subjects/Keywords: SiC MOSFET; power module packaging; flexible PCB; current sharing; symmetrical direct bonded copper (DBC) layout; diode-less module; multi-chip module; device parametric tolerances; package parasitics; vertical GaN

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Watt, G. R. (2020). Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96559

Chicago Manual of Style (16th Edition):

Watt, Grace R. “Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module.” 2020. Masters Thesis, Virginia Tech. Accessed January 20, 2021. http://hdl.handle.net/10919/96559.

MLA Handbook (7th Edition):

Watt, Grace R. “Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module.” 2020. Web. 20 Jan 2021.

Vancouver:

Watt GR. Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10919/96559.

Council of Science Editors:

Watt GR. Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/96559


Jönköping University

25. Eriksson, Madeleine. Text Placement in SNS forEffective Communication : A qualitative study investigating the most favourable text placement onmedia sharing SNS advertisements to best communicate informationthrough text.

Degree: Computer Science and Informatics, 2020, Jönköping University

  The aim of this thesis is to conduct a qualitative study investigating the mostfavourable text placement on social networking sites (SNS) to best communicateinformation… (more)

Subjects/Keywords: SNS; Text Placement; Media Sharing SNS; Layout; Advertising; Information System; Communication; Design; Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Eriksson, M. (2020). Text Placement in SNS forEffective Communication : A qualitative study investigating the most favourable text placement onmedia sharing SNS advertisements to best communicate informationthrough text. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-49541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Eriksson, Madeleine. “Text Placement in SNS forEffective Communication : A qualitative study investigating the most favourable text placement onmedia sharing SNS advertisements to best communicate informationthrough text.” 2020. Thesis, Jönköping University. Accessed January 20, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-49541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Eriksson, Madeleine. “Text Placement in SNS forEffective Communication : A qualitative study investigating the most favourable text placement onmedia sharing SNS advertisements to best communicate informationthrough text.” 2020. Web. 20 Jan 2021.

Vancouver:

Eriksson M. Text Placement in SNS forEffective Communication : A qualitative study investigating the most favourable text placement onmedia sharing SNS advertisements to best communicate informationthrough text. [Internet] [Thesis]. Jönköping University; 2020. [cited 2021 Jan 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-49541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Eriksson M. Text Placement in SNS forEffective Communication : A qualitative study investigating the most favourable text placement onmedia sharing SNS advertisements to best communicate informationthrough text. [Thesis]. Jönköping University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-49541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

26. -2180-8629. Layout automation for analog and mixed-signal integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Recently, the demand for analog and mixed-signal (AMS) integrated circuits (ICs) has increased significantly due to various emerging applications. However, most of the AMS IC… (more)

Subjects/Keywords: Analog and mixed-signal integrated circuits; Layout; Physical design automation; Placement; Electronic design automation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

-2180-8629. (2019). Layout automation for analog and mixed-signal integrated circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3213

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-2180-8629. “Layout automation for analog and mixed-signal integrated circuits.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed January 20, 2021. http://dx.doi.org/10.26153/tsw/3213.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-2180-8629. “Layout automation for analog and mixed-signal integrated circuits.” 2019. Web. 20 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-2180-8629. Layout automation for analog and mixed-signal integrated circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Jan 20]. Available from: http://dx.doi.org/10.26153/tsw/3213.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-2180-8629. Layout automation for analog and mixed-signal integrated circuits. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3213

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Leiden University

27. Bruin, Lennart de. Sequence dependent mechanics of forced nucleosome unwrapping.

Degree: 2015, Leiden University

 Accessibility to nucleosomal dna is an important factor in transcription and gene expression. During transcription, rna polymerase exerts a force on the nucleosome under which… (more)

Subjects/Keywords: dna; unwrapping; sequence-dependence; force; 601; nucleosome; rigid base pair; simulation; Monte Carlo

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APA (6th Edition):

Bruin, L. d. (2015). Sequence dependent mechanics of forced nucleosome unwrapping. (Masters Thesis). Leiden University. Retrieved from http://hdl.handle.net/1887/37071

Chicago Manual of Style (16th Edition):

Bruin, Lennart de. “Sequence dependent mechanics of forced nucleosome unwrapping.” 2015. Masters Thesis, Leiden University. Accessed January 20, 2021. http://hdl.handle.net/1887/37071.

MLA Handbook (7th Edition):

Bruin, Lennart de. “Sequence dependent mechanics of forced nucleosome unwrapping.” 2015. Web. 20 Jan 2021.

Vancouver:

Bruin Ld. Sequence dependent mechanics of forced nucleosome unwrapping. [Internet] [Masters thesis]. Leiden University; 2015. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1887/37071.

Council of Science Editors:

Bruin Ld. Sequence dependent mechanics of forced nucleosome unwrapping. [Masters Thesis]. Leiden University; 2015. Available from: http://hdl.handle.net/1887/37071


Iowa State University

28. Yadav, Akshay. Methods for correcting and analyzing gene families.

Degree: 2020, Iowa State University

 Gene families are groups of genes that have descended from a common ancestral gene present in the species under study. Current, widely used gene family… (more)

Subjects/Keywords: Gene family building; Genome evolution; Machine learning; Protein domains; Sequence pair classification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yadav, A. (2020). Methods for correcting and analyzing gene families. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/18059

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yadav, Akshay. “Methods for correcting and analyzing gene families.” 2020. Thesis, Iowa State University. Accessed January 20, 2021. https://lib.dr.iastate.edu/etd/18059.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yadav, Akshay. “Methods for correcting and analyzing gene families.” 2020. Web. 20 Jan 2021.

Vancouver:

Yadav A. Methods for correcting and analyzing gene families. [Internet] [Thesis]. Iowa State University; 2020. [cited 2021 Jan 20]. Available from: https://lib.dr.iastate.edu/etd/18059.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yadav A. Methods for correcting and analyzing gene families. [Thesis]. Iowa State University; 2020. Available from: https://lib.dr.iastate.edu/etd/18059

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Lorraine

29. Bouzoubaa, Yahya. Méthodes exactes et heuristiques pour l’optimisation de l’agencement d’un logement : application aux situations de handicap : Exact and heuristic methods for optimizing the layout of an apartment : application to situations of disability.

Degree: Docteur es, Informatique, 2017, Université de Lorraine

 Le volet applicatif de cette thèse porte sur l'agencement d'un logement destiné à une personne en situation de handicap. L'agencement désigne le choix de la… (more)

Subjects/Keywords: Optimisation combinatoire; Modélisation mathématique; Métaheuristique; Placement 2D; Bin packing; Handicap; Combinatorial optimization; Mathematic modelling; Metaheuristic; Placement 2D; Bin packing; Handicap; 006.3; 643

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bouzoubaa, Y. (2017). Méthodes exactes et heuristiques pour l’optimisation de l’agencement d’un logement : application aux situations de handicap : Exact and heuristic methods for optimizing the layout of an apartment : application to situations of disability. (Doctoral Dissertation). Université de Lorraine. Retrieved from http://www.theses.fr/2017LORR0369

Chicago Manual of Style (16th Edition):

Bouzoubaa, Yahya. “Méthodes exactes et heuristiques pour l’optimisation de l’agencement d’un logement : application aux situations de handicap : Exact and heuristic methods for optimizing the layout of an apartment : application to situations of disability.” 2017. Doctoral Dissertation, Université de Lorraine. Accessed January 20, 2021. http://www.theses.fr/2017LORR0369.

MLA Handbook (7th Edition):

Bouzoubaa, Yahya. “Méthodes exactes et heuristiques pour l’optimisation de l’agencement d’un logement : application aux situations de handicap : Exact and heuristic methods for optimizing the layout of an apartment : application to situations of disability.” 2017. Web. 20 Jan 2021.

Vancouver:

Bouzoubaa Y. Méthodes exactes et heuristiques pour l’optimisation de l’agencement d’un logement : application aux situations de handicap : Exact and heuristic methods for optimizing the layout of an apartment : application to situations of disability. [Internet] [Doctoral dissertation]. Université de Lorraine; 2017. [cited 2021 Jan 20]. Available from: http://www.theses.fr/2017LORR0369.

Council of Science Editors:

Bouzoubaa Y. Méthodes exactes et heuristiques pour l’optimisation de l’agencement d’un logement : application aux situations de handicap : Exact and heuristic methods for optimizing the layout of an apartment : application to situations of disability. [Doctoral Dissertation]. Université de Lorraine; 2017. Available from: http://www.theses.fr/2017LORR0369


University of North Texas

30. Aluru, Gunasekhar. Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System.

Degree: 2016, University of North Texas

 The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level.… (more)

Subjects/Keywords: Layout Design; EDA or CAD system; Electric VLSI Design System; Physical Verification; Open-source EDA tool; Digital Designs; Analog Designs: User-manual for Electric VLSI Design System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aluru, G. (2016). Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc849770/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aluru, Gunasekhar. “Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System.” 2016. Thesis, University of North Texas. Accessed January 20, 2021. https://digital.library.unt.edu/ark:/67531/metadc849770/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aluru, Gunasekhar. “Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System.” 2016. Web. 20 Jan 2021.

Vancouver:

Aluru G. Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System. [Internet] [Thesis]. University of North Texas; 2016. [cited 2021 Jan 20]. Available from: https://digital.library.unt.edu/ark:/67531/metadc849770/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aluru G. Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System. [Thesis]. University of North Texas; 2016. Available from: https://digital.library.unt.edu/ark:/67531/metadc849770/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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