Advanced search options
You searched for subject:(2 VLSI )
.
Showing records 1 – 4 of
4 total matches.
▼ Search Limiters
University of Akron
1. Weesinghe Weerasinha , Sewwandi Wijayaratna. FPGA Architectures for Fast Steerable Beam-Enhanced Digital Aperture Arrays.
Degree: MSin Engineering, Electrical Engineering, 2014, University of Akron
URL: http://rave.ohiolink.edu/etdc/view?acc_num=akron1407762895
Subjects/Keywords: Electrical Engineering; Beamforming; beamfilter; FPGA; VLSI; WDF; beam-enhanced; multi-dimensional; beam-steering; 2-D IIR
Record Details
Similar Records
❌
APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Weesinghe Weerasinha , S. W. (2014). FPGA Architectures for Fast Steerable Beam-Enhanced Digital Aperture Arrays. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1407762895
Chicago Manual of Style (16th Edition):
Weesinghe Weerasinha , Sewwandi Wijayaratna. “FPGA Architectures for Fast Steerable Beam-Enhanced Digital Aperture Arrays.” 2014. Masters Thesis, University of Akron. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=akron1407762895.
MLA Handbook (7th Edition):
Weesinghe Weerasinha , Sewwandi Wijayaratna. “FPGA Architectures for Fast Steerable Beam-Enhanced Digital Aperture Arrays.” 2014. Web. 27 Jan 2021.
Vancouver:
Weesinghe Weerasinha SW. FPGA Architectures for Fast Steerable Beam-Enhanced Digital Aperture Arrays. [Internet] [Masters thesis]. University of Akron; 2014. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1407762895.
Council of Science Editors:
Weesinghe Weerasinha SW. FPGA Architectures for Fast Steerable Beam-Enhanced Digital Aperture Arrays. [Masters Thesis]. University of Akron; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1407762895
2. 柴田, 貴之. 2次元トーラス空間における矩形配置のコード表現と最適化.
Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学
URL: http://hdl.handle.net/10119/4353
Supervisor:金子峰雄
情報科学研究科
修士
Subjects/Keywords: 2次元トーラス,VLSIレイアウト,シーケンスペア,矩形配置; 2D Torus,VLSI layout,sequence-pair,Module placement
Record Details
Similar Records
❌
APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
柴田, . (n.d.). 2次元トーラス空間における矩形配置のコード表現と最適化. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/4353
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
柴田, 貴之. “2次元トーラス空間における矩形配置のコード表現と最適化.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed January 27, 2021. http://hdl.handle.net/10119/4353.
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
柴田, 貴之. “2次元トーラス空間における矩形配置のコード表現と最適化.” Web. 27 Jan 2021.
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Vancouver:
柴田 . 2次元トーラス空間における矩形配置のコード表現と最適化. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Jan 27]. Available from: http://hdl.handle.net/10119/4353.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.
Council of Science Editors:
柴田 . 2次元トーラス空間における矩形配置のコード表現と最適化. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/4353
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.
University of Sydney
3. Shiraishi, Hisako. Design of an Analog VLSI Cochlea .
Degree: 2003, University of Sydney
URL: http://hdl.handle.net/2123/556
Subjects/Keywords: analog VLSI; 2-D; cochlea; CMOS weak inversion; log-domain filter; outer hair cells
Record Details
Similar Records
❌
APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Shiraishi, H. (2003). Design of an Analog VLSI Cochlea . (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/556
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Shiraishi, Hisako. “Design of an Analog VLSI Cochlea .” 2003. Thesis, University of Sydney. Accessed January 27, 2021. http://hdl.handle.net/2123/556.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Shiraishi, Hisako. “Design of an Analog VLSI Cochlea .” 2003. Web. 27 Jan 2021.
Vancouver:
Shiraishi H. Design of an Analog VLSI Cochlea . [Internet] [Thesis]. University of Sydney; 2003. [cited 2021 Jan 27]. Available from: http://hdl.handle.net/2123/556.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Shiraishi H. Design of an Analog VLSI Cochlea . [Thesis]. University of Sydney; 2003. Available from: http://hdl.handle.net/2123/556
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
4. Seneviratne, Vishwa. Design and Rapid-prototyping of Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform.
Degree: MS, Electrical Engineering, 2017, University of Akron
URL: http://rave.ohiolink.edu/etdc/view?acc_num=akron1488149940846702
Subjects/Keywords: Communication; Electrical Engineering; Engineering; ROACH-2; multidimensional; FPGA; polyphase structures; beamformers; systolic arrays; planar array; phased-array; wideband beamformers; plane wave signal; beam filter; passive LRC networks; multirate; VLSI; ADC; antenna arrays; look-ahead optimization
…LIST OF TABLES Table 3.1 3.2 4.1 5.1 6.1 6.2 Page Comparison of VLSI FPGA resource… …consumption for 32 element differential form 2-D IIR beam filter at 18-bit and 12-bit inputs… …46 ASIC synthesis results for AMS, 180nm CMOS for 32 element differential form 2-D IIR… …consumption for 32 element differential form polyphased 2-D IIR beam filter at 16-bit and 32-bit… …x29;, (d) Phased array based radar systems used in Military applications. [2…
Record Details
Similar Records
❌
APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Seneviratne, V. (2017). Design and Rapid-prototyping of Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1488149940846702
Chicago Manual of Style (16th Edition):
Seneviratne, Vishwa. “Design and Rapid-prototyping of Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform.” 2017. Masters Thesis, University of Akron. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=akron1488149940846702.
MLA Handbook (7th Edition):
Seneviratne, Vishwa. “Design and Rapid-prototyping of Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform.” 2017. Web. 27 Jan 2021.
Vancouver:
Seneviratne V. Design and Rapid-prototyping of Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform. [Internet] [Masters thesis]. University of Akron; 2017. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1488149940846702.
Council of Science Editors:
Seneviratne V. Design and Rapid-prototyping of Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform. [Masters Thesis]. University of Akron; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1488149940846702