Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:( integrated circuit). Showing records 1 – 30 of 538 total matches.

[1] [2] [3] [4] [5] … [18]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Languages

Country

▼ Search Limiters

1. Park, Chang Joon. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.

Degree: 2013, Texas Digital Library

 Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal… (more)

Subjects/Keywords: Integrated Circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, C. J. (2013). Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. (Thesis). Texas Digital Library. Retrieved from http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Chang Joon. “Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.” 2013. Thesis, Texas Digital Library. Accessed August 15, 2020. http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Chang Joon. “Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications.” 2013. Web. 15 Aug 2020.

Vancouver:

Park CJ. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. [Internet] [Thesis]. Texas Digital Library; 2013. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park CJ. Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications. [Thesis]. Texas Digital Library; 2013. Available from: http://hdl.handle.net/1969; http://hdl.handle.net/2249.1/66538

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

2. Kim, Brian. Microfabricated Devices For Direct Measurements Of Quantal Transmitter Release From Living Cells .

Degree: 2013, Cornell University

 Neurotransmitters are released in packets or quanta from vesicles that fuse with the cell membrane. The machinery proteins called Soluble N-ethylmaleimide-sensitive factor Attachment Protein Receptor… (more)

Subjects/Keywords: Biosensor; Exocytosis; CMOS Integrated Circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, B. (2013). Microfabricated Devices For Direct Measurements Of Quantal Transmitter Release From Living Cells . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/33818

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Brian. “Microfabricated Devices For Direct Measurements Of Quantal Transmitter Release From Living Cells .” 2013. Thesis, Cornell University. Accessed August 15, 2020. http://hdl.handle.net/1813/33818.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Brian. “Microfabricated Devices For Direct Measurements Of Quantal Transmitter Release From Living Cells .” 2013. Web. 15 Aug 2020.

Vancouver:

Kim B. Microfabricated Devices For Direct Measurements Of Quantal Transmitter Release From Living Cells . [Internet] [Thesis]. Cornell University; 2013. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1813/33818.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim B. Microfabricated Devices For Direct Measurements Of Quantal Transmitter Release From Living Cells . [Thesis]. Cornell University; 2013. Available from: http://hdl.handle.net/1813/33818

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

3. Bagheri, Arezu. High-Integration-Density Neural Interfaces for High-Spatial-Rrsolution Intracranial EEG Monitoring.

Degree: 2013, University of Toronto

This thesis presents two experimental microelectronic prototypes for neurophysiological applications. Both systems target diagnostics and treatment of neurological disorders, and they are experimentally validated in… (more)

Subjects/Keywords: Neural Intarfaces; Integrated Circuit; 0544

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bagheri, A. (2013). High-Integration-Density Neural Interfaces for High-Spatial-Rrsolution Intracranial EEG Monitoring. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42678

Chicago Manual of Style (16th Edition):

Bagheri, Arezu. “High-Integration-Density Neural Interfaces for High-Spatial-Rrsolution Intracranial EEG Monitoring.” 2013. Masters Thesis, University of Toronto. Accessed August 15, 2020. http://hdl.handle.net/1807/42678.

MLA Handbook (7th Edition):

Bagheri, Arezu. “High-Integration-Density Neural Interfaces for High-Spatial-Rrsolution Intracranial EEG Monitoring.” 2013. Web. 15 Aug 2020.

Vancouver:

Bagheri A. High-Integration-Density Neural Interfaces for High-Spatial-Rrsolution Intracranial EEG Monitoring. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1807/42678.

Council of Science Editors:

Bagheri A. High-Integration-Density Neural Interfaces for High-Spatial-Rrsolution Intracranial EEG Monitoring. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/42678


Ryerson University

4. Abdullah, Alaa R. On-chip interconnects modeling and timing driven buffer insertion.

Degree: 2010, Ryerson University

 With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well… (more)

Subjects/Keywords: Interconnects (Integrated circuit technology); Interconnects (Integrated circuit technology)  – Computer simulation; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abdullah, A. R. (2010). On-chip interconnects modeling and timing driven buffer insertion. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abdullah, Alaa R. “On-chip interconnects modeling and timing driven buffer insertion.” 2010. Thesis, Ryerson University. Accessed August 15, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A1356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abdullah, Alaa R. “On-chip interconnects modeling and timing driven buffer insertion.” 2010. Web. 15 Aug 2020.

Vancouver:

Abdullah AR. On-chip interconnects modeling and timing driven buffer insertion. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Aug 15]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abdullah AR. On-chip interconnects modeling and timing driven buffer insertion. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Jang, Sun Hwan. Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 This dissertation presents various “efficient” design techniques for mm-wave front-end integrated circuits in regards to dc power, bandwidth, and chip size. The ideas, while suitable… (more)

Subjects/Keywords: Millimeter-wave; RFIC; Integrated Circuit; CMOS; BiCMOS

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jang, S. H. (2016). Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158120

Chicago Manual of Style (16th Edition):

Jang, Sun Hwan. “Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS.” 2016. Doctoral Dissertation, Texas A&M University. Accessed August 15, 2020. http://hdl.handle.net/1969.1/158120.

MLA Handbook (7th Edition):

Jang, Sun Hwan. “Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS.” 2016. Web. 15 Aug 2020.

Vancouver:

Jang SH. Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1969.1/158120.

Council of Science Editors:

Jang SH. Efficient High-Performance Millimeter-Wave Front-End Integrated Circuit Designs and Techniques in SiGe BiCMOS. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158120


UCLA

6. Yang, Jiyue. Design of A 0-3Ghz Spectrum Scanner Using Sampled Linear and Periodically Time Varying Circuit.

Degree: Electrical and Computer Engineering, 2018, UCLA

 As the number of wireless network users increases in the modern communication systems, cognitive radio becomes an attractive solution to the crowded communication spectrum. A… (more)

Subjects/Keywords: Engineering; RF Integrated Circuit; Spectrum Scanner

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2018). Design of A 0-3Ghz Spectrum Scanner Using Sampled Linear and Periodically Time Varying Circuit. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/47d0m3mc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Jiyue. “Design of A 0-3Ghz Spectrum Scanner Using Sampled Linear and Periodically Time Varying Circuit.” 2018. Thesis, UCLA. Accessed August 15, 2020. http://www.escholarship.org/uc/item/47d0m3mc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Jiyue. “Design of A 0-3Ghz Spectrum Scanner Using Sampled Linear and Periodically Time Varying Circuit.” 2018. Web. 15 Aug 2020.

Vancouver:

Yang J. Design of A 0-3Ghz Spectrum Scanner Using Sampled Linear and Periodically Time Varying Circuit. [Internet] [Thesis]. UCLA; 2018. [cited 2020 Aug 15]. Available from: http://www.escholarship.org/uc/item/47d0m3mc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang J. Design of A 0-3Ghz Spectrum Scanner Using Sampled Linear and Periodically Time Varying Circuit. [Thesis]. UCLA; 2018. Available from: http://www.escholarship.org/uc/item/47d0m3mc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Ottawa

7. Hasan, Mehedi. Photonic Integrated Circuit Architecture for Radio-over-Fibre Applications .

Degree: 2015, University of Ottawa

 The aim of the research presented in this thesis is to develop photonic integrated circuit (PIC) for Radio-over-Fiber (RoF) application. As such, at the beginning… (more)

Subjects/Keywords: Radio-over-Fibre; Photonic Integrated Circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hasan, M. (2015). Photonic Integrated Circuit Architecture for Radio-over-Fibre Applications . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/32826

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hasan, Mehedi. “Photonic Integrated Circuit Architecture for Radio-over-Fibre Applications .” 2015. Thesis, University of Ottawa. Accessed August 15, 2020. http://hdl.handle.net/10393/32826.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hasan, Mehedi. “Photonic Integrated Circuit Architecture for Radio-over-Fibre Applications .” 2015. Web. 15 Aug 2020.

Vancouver:

Hasan M. Photonic Integrated Circuit Architecture for Radio-over-Fibre Applications . [Internet] [Thesis]. University of Ottawa; 2015. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/10393/32826.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hasan M. Photonic Integrated Circuit Architecture for Radio-over-Fibre Applications . [Thesis]. University of Ottawa; 2015. Available from: http://hdl.handle.net/10393/32826

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

8. Ercius, Peter. Three-Dimensional Electron Tomography Of Integrated Circuit Devices .

Degree: 2009, Cornell University

 The three-dimensional structure of integrated circuit (IC) devices can be analyzed at the nanometer scale by electron tomography using projection images generated from a scanning… (more)

Subjects/Keywords: Integrated Circuit Devices

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ercius, P. (2009). Three-Dimensional Electron Tomography Of Integrated Circuit Devices . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/13913

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ercius, Peter. “Three-Dimensional Electron Tomography Of Integrated Circuit Devices .” 2009. Thesis, Cornell University. Accessed August 15, 2020. http://hdl.handle.net/1813/13913.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ercius, Peter. “Three-Dimensional Electron Tomography Of Integrated Circuit Devices .” 2009. Web. 15 Aug 2020.

Vancouver:

Ercius P. Three-Dimensional Electron Tomography Of Integrated Circuit Devices . [Internet] [Thesis]. Cornell University; 2009. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1813/13913.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ercius P. Three-Dimensional Electron Tomography Of Integrated Circuit Devices . [Thesis]. Cornell University; 2009. Available from: http://hdl.handle.net/1813/13913

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

9. Akbar, Fatemeh. New Architectures for Low Complexity Scalable Phased Arrays.

Degree: PhD, Electrical Engineering, 2018, University of Michigan

 Inspired by the unique advantages of phased arrays in communication and radar systems, i.e. their capability to increase the channel capacity, signal-to-noise ratio, directivity, and… (more)

Subjects/Keywords: Phased array; integrated circuit; Electrical Engineering; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Akbar, F. (2018). New Architectures for Low Complexity Scalable Phased Arrays. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/147494

Chicago Manual of Style (16th Edition):

Akbar, Fatemeh. “New Architectures for Low Complexity Scalable Phased Arrays.” 2018. Doctoral Dissertation, University of Michigan. Accessed August 15, 2020. http://hdl.handle.net/2027.42/147494.

MLA Handbook (7th Edition):

Akbar, Fatemeh. “New Architectures for Low Complexity Scalable Phased Arrays.” 2018. Web. 15 Aug 2020.

Vancouver:

Akbar F. New Architectures for Low Complexity Scalable Phased Arrays. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/2027.42/147494.

Council of Science Editors:

Akbar F. New Architectures for Low Complexity Scalable Phased Arrays. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/147494


University of Toronto

10. Sun, Xiao. Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration.

Degree: 2013, University of Toronto

This thesis prompt a theoretical analysis of the hybrid plasmonic waveguide (HPWG) and a TE-pass polarizer based on HPWG has been designed, fabricated and characterized.… (more)

Subjects/Keywords: plasmonic waveguide; polarizer; integrated optical circuit; 0544

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sun, X. (2013). Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/35684

Chicago Manual of Style (16th Edition):

Sun, Xiao. “Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration.” 2013. Masters Thesis, University of Toronto. Accessed August 15, 2020. http://hdl.handle.net/1807/35684.

MLA Handbook (7th Edition):

Sun, Xiao. “Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration.” 2013. Web. 15 Aug 2020.

Vancouver:

Sun X. Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1807/35684.

Council of Science Editors:

Sun X. Hybrid Plasmonic Waveguides and Devices: Theory, Modeling and Experimental Demonstration. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/35684


Hong Kong University of Science and Technology

11. Wang, Zhehui ECE. Modelling, analysis, and application of optical inter/intra-chip interconnects and interfaces.

Degree: 2017, Hong Kong University of Science and Technology

 With the fast development of processor chips, power-efficient, high-bandwidth, and low-latency inter-chip interconnects become more and more important. Studies show that the bandwidth of traditional… (more)

Subjects/Keywords: Interconnects (Integrated circuit technology) ; Optical interconnects

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, Z. E. (2017). Modelling, analysis, and application of optical inter/intra-chip interconnects and interfaces. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-95310 ; https://doi.org/10.14711/thesis-b1779932 ; http://repository.ust.hk/ir/bitstream/1783.1-95310/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Zhehui ECE. “Modelling, analysis, and application of optical inter/intra-chip interconnects and interfaces.” 2017. Thesis, Hong Kong University of Science and Technology. Accessed August 15, 2020. http://repository.ust.hk/ir/Record/1783.1-95310 ; https://doi.org/10.14711/thesis-b1779932 ; http://repository.ust.hk/ir/bitstream/1783.1-95310/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Zhehui ECE. “Modelling, analysis, and application of optical inter/intra-chip interconnects and interfaces.” 2017. Web. 15 Aug 2020.

Vancouver:

Wang ZE. Modelling, analysis, and application of optical inter/intra-chip interconnects and interfaces. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2017. [cited 2020 Aug 15]. Available from: http://repository.ust.hk/ir/Record/1783.1-95310 ; https://doi.org/10.14711/thesis-b1779932 ; http://repository.ust.hk/ir/bitstream/1783.1-95310/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang ZE. Modelling, analysis, and application of optical inter/intra-chip interconnects and interfaces. [Thesis]. Hong Kong University of Science and Technology; 2017. Available from: http://repository.ust.hk/ir/Record/1783.1-95310 ; https://doi.org/10.14711/thesis-b1779932 ; http://repository.ust.hk/ir/bitstream/1783.1-95310/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Louisiana State University

12. Liu, Yang. Phase Noise in CMOS Phase-Locked Loop Circuits.

Degree: PhD, Electrical and Computer Engineering, 2011, Louisiana State University

 Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs… (more)

Subjects/Keywords: hot carrier effect; phase noise; integrated circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Y. (2011). Phase Noise in CMOS Phase-Locked Loop Circuits. (Doctoral Dissertation). Louisiana State University. Retrieved from etd-11052011-182642 ; https://digitalcommons.lsu.edu/gradschool_dissertations/720

Chicago Manual of Style (16th Edition):

Liu, Yang. “Phase Noise in CMOS Phase-Locked Loop Circuits.” 2011. Doctoral Dissertation, Louisiana State University. Accessed August 15, 2020. etd-11052011-182642 ; https://digitalcommons.lsu.edu/gradschool_dissertations/720.

MLA Handbook (7th Edition):

Liu, Yang. “Phase Noise in CMOS Phase-Locked Loop Circuits.” 2011. Web. 15 Aug 2020.

Vancouver:

Liu Y. Phase Noise in CMOS Phase-Locked Loop Circuits. [Internet] [Doctoral dissertation]. Louisiana State University; 2011. [cited 2020 Aug 15]. Available from: etd-11052011-182642 ; https://digitalcommons.lsu.edu/gradschool_dissertations/720.

Council of Science Editors:

Liu Y. Phase Noise in CMOS Phase-Locked Loop Circuits. [Doctoral Dissertation]. Louisiana State University; 2011. Available from: etd-11052011-182642 ; https://digitalcommons.lsu.edu/gradschool_dissertations/720


Université de Bordeaux I

13. Deyine, Amjad. Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI : Electrical characterization, highlight of physicochemical phenomena and fractional modeling of supercapacitors made of activated carbon electrodes.

Degree: Docteur es, Electronique, 2011, Université de Bordeaux I

 L’objectif principal du projet est d’étudier les techniques d’analyses de défaillances des circuits intégrés VLSI basées sur l’emploi de laser. Les études ont été effectuées… (more)

Subjects/Keywords: Stimulation laser; Circuit intégré; Laser stimulation; Integrated circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Deyine, A. (2011). Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI : Electrical characterization, highlight of physicochemical phenomena and fractional modeling of supercapacitors made of activated carbon electrodes. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2011BOR14252

Chicago Manual of Style (16th Edition):

Deyine, Amjad. “Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI : Electrical characterization, highlight of physicochemical phenomena and fractional modeling of supercapacitors made of activated carbon electrodes.” 2011. Doctoral Dissertation, Université de Bordeaux I. Accessed August 15, 2020. http://www.theses.fr/2011BOR14252.

MLA Handbook (7th Edition):

Deyine, Amjad. “Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI : Electrical characterization, highlight of physicochemical phenomena and fractional modeling of supercapacitors made of activated carbon electrodes.” 2011. Web. 15 Aug 2020.

Vancouver:

Deyine A. Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI : Electrical characterization, highlight of physicochemical phenomena and fractional modeling of supercapacitors made of activated carbon electrodes. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2011. [cited 2020 Aug 15]. Available from: http://www.theses.fr/2011BOR14252.

Council of Science Editors:

Deyine A. Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI : Electrical characterization, highlight of physicochemical phenomena and fractional modeling of supercapacitors made of activated carbon electrodes. [Doctoral Dissertation]. Université de Bordeaux I; 2011. Available from: http://www.theses.fr/2011BOR14252


University of Toronto

14. Moiannou, Tom. Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and a Practical Single-Mode Controller with Near Minimum Deviation Transient Response.

Degree: 2018, University of Toronto

The work presented in this thesis focuses on the practical implementation of techniques to reduce the volume of the output filter capacitor and inductor. The… (more)

Subjects/Keywords: Circuit; Control; Integrated Circuit; Minimum Deviation; Power Management; SMPS; 0544

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moiannou, T. (2018). Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and a Practical Single-Mode Controller with Near Minimum Deviation Transient Response. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/95629

Chicago Manual of Style (16th Edition):

Moiannou, Tom. “Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and a Practical Single-Mode Controller with Near Minimum Deviation Transient Response.” 2018. Masters Thesis, University of Toronto. Accessed August 15, 2020. http://hdl.handle.net/1807/95629.

MLA Handbook (7th Edition):

Moiannou, Tom. “Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and a Practical Single-Mode Controller with Near Minimum Deviation Transient Response.” 2018. Web. 15 Aug 2020.

Vancouver:

Moiannou T. Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and a Practical Single-Mode Controller with Near Minimum Deviation Transient Response. [Internet] [Masters thesis]. University of Toronto; 2018. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1807/95629.

Council of Science Editors:

Moiannou T. Practical Implementation of Flying Capacitor Based Multilevel Converters On-Chip and a Practical Single-Mode Controller with Near Minimum Deviation Transient Response. [Masters Thesis]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/95629


Portland State University

15. Jamadagni, Navaneeth Prasannakumar. 3-D modelling of IC interconnect using OpenAccess and Art of Illusion.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2010, Portland State University

  In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In… (more)

Subjects/Keywords: Interconnects (Integrated circuit technology)  – Computer simulation; Integrated circuits  – Computer simulation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jamadagni, N. P. (2010). 3-D modelling of IC interconnect using OpenAccess and Art of Illusion. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/28

Chicago Manual of Style (16th Edition):

Jamadagni, Navaneeth Prasannakumar. “3-D modelling of IC interconnect using OpenAccess and Art of Illusion.” 2010. Masters Thesis, Portland State University. Accessed August 15, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/28.

MLA Handbook (7th Edition):

Jamadagni, Navaneeth Prasannakumar. “3-D modelling of IC interconnect using OpenAccess and Art of Illusion.” 2010. Web. 15 Aug 2020.

Vancouver:

Jamadagni NP. 3-D modelling of IC interconnect using OpenAccess and Art of Illusion. [Internet] [Masters thesis]. Portland State University; 2010. [cited 2020 Aug 15]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/28.

Council of Science Editors:

Jamadagni NP. 3-D modelling of IC interconnect using OpenAccess and Art of Illusion. [Masters Thesis]. Portland State University; 2010. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/28


Hong Kong University of Science and Technology

16. Jiang, Haoyuan ECE. Time-dependent interconnect electromigration simulation.

Degree: 2017, Hong Kong University of Science and Technology

 Due to the geometry scaling in advantaged technology node, the current density increases significant in interconnects. The ITRS roadmap predicts that all interconnects with minimum… (more)

Subjects/Keywords: Electrodiffusion ; Interconnects (Integrated circuit technology) ; Integrated circuits ; Deterioration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jiang, H. E. (2017). Time-dependent interconnect electromigration simulation. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-91069 ; https://doi.org/10.14711/thesis-991012554563803412 ; http://repository.ust.hk/ir/bitstream/1783.1-91069/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiang, Haoyuan ECE. “Time-dependent interconnect electromigration simulation.” 2017. Thesis, Hong Kong University of Science and Technology. Accessed August 15, 2020. http://repository.ust.hk/ir/Record/1783.1-91069 ; https://doi.org/10.14711/thesis-991012554563803412 ; http://repository.ust.hk/ir/bitstream/1783.1-91069/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiang, Haoyuan ECE. “Time-dependent interconnect electromigration simulation.” 2017. Web. 15 Aug 2020.

Vancouver:

Jiang HE. Time-dependent interconnect electromigration simulation. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2017. [cited 2020 Aug 15]. Available from: http://repository.ust.hk/ir/Record/1783.1-91069 ; https://doi.org/10.14711/thesis-991012554563803412 ; http://repository.ust.hk/ir/bitstream/1783.1-91069/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang HE. Time-dependent interconnect electromigration simulation. [Thesis]. Hong Kong University of Science and Technology; 2017. Available from: http://repository.ust.hk/ir/Record/1783.1-91069 ; https://doi.org/10.14711/thesis-991012554563803412 ; http://repository.ust.hk/ir/bitstream/1783.1-91069/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

17. Mavuram, Sushmitha. Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology.

Degree: MS, Computer Engineering, 2019, Rochester Institute of Technology

  The complexity of the circuit design has been significantly increased from 1980’s till date, and until 80’s, due to less complexity and technology node… (more)

Subjects/Keywords: Integrated circuits; Integrated circuit testing; Testability features; MBIST; LBIST; JTAG

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mavuram, S. (2019). Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10326

Chicago Manual of Style (16th Edition):

Mavuram, Sushmitha. “Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed August 15, 2020. https://scholarworks.rit.edu/theses/10326.

MLA Handbook (7th Edition):

Mavuram, Sushmitha. “Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology.” 2019. Web. 15 Aug 2020.

Vancouver:

Mavuram S. Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Aug 15]. Available from: https://scholarworks.rit.edu/theses/10326.

Council of Science Editors:

Mavuram S. Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10326


University of Arkansas

18. Lamichhane, Ranjan Raj. A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications.

Degree: MSEE, 2013, University of Arkansas

  The potential of silicon carbide (SiC) for modern power electronics applications is revolutionary because of its superior material properties including substantially better breakdown voltage,… (more)

Subjects/Keywords: Applied sciences; Gate driver; High temperature integrated circuit; High voltage integrated circuit; Integrated circuits integrated circuit; Power electronics; silicon carbide; Electrical and Electronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lamichhane, R. R. (2013). A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/948

Chicago Manual of Style (16th Edition):

Lamichhane, Ranjan Raj. “A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications.” 2013. Masters Thesis, University of Arkansas. Accessed August 15, 2020. https://scholarworks.uark.edu/etd/948.

MLA Handbook (7th Edition):

Lamichhane, Ranjan Raj. “A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications.” 2013. Web. 15 Aug 2020.

Vancouver:

Lamichhane RR. A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications. [Internet] [Masters thesis]. University of Arkansas; 2013. [cited 2020 Aug 15]. Available from: https://scholarworks.uark.edu/etd/948.

Council of Science Editors:

Lamichhane RR. A Wide Bandgap Silicon Carbide (SiC) Gate Driver for High Temperature, High Voltage, and High Frequency Applications. [Masters Thesis]. University of Arkansas; 2013. Available from: https://scholarworks.uark.edu/etd/948


Texas A&M University

19. Mukherjee, Parijat. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.

Degree: PhD, Computer Engineering, 2014, Texas A&M University

 Verifying whether a circuit meets its intended specifications, as well as diagnosing the circuits that do not, is indispensable at every stage of integrated circuit(more)

Subjects/Keywords: Model checking; Integrated circuit testing; Integrated circuit yield; Yield estimation; Circuit optimization; Statistical analysis; Sampling methods; Monte carlo methods; Machine learning; Analog circuits; Mixed analog digital integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukherjee, P. (2014). Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/154004

Chicago Manual of Style (16th Edition):

Mukherjee, Parijat. “Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.” 2014. Doctoral Dissertation, Texas A&M University. Accessed August 15, 2020. http://hdl.handle.net/1969.1/154004.

MLA Handbook (7th Edition):

Mukherjee, Parijat. “Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.” 2014. Web. 15 Aug 2020.

Vancouver:

Mukherjee P. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. [Internet] [Doctoral dissertation]. Texas A&M University; 2014. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1969.1/154004.

Council of Science Editors:

Mukherjee P. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. [Doctoral Dissertation]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/154004


NSYSU

20. Lin, Ding-Zhi. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.

Degree: Master, Electrical Engineering, 2018, NSYSU

 With the advance of mobile healthcare and the Internet-of-things increasing numbers of applications incorporate low-power miniature sensing devices for various types of input signal. In… (more)

Subjects/Keywords: biomedical chip; adjustable gain; switched capacitor amplifier; integrated circuit; temperature monitoring circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, D. (2018). Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Ding-Zhi. “Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.” 2018. Thesis, NSYSU. Accessed August 15, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Ding-Zhi. “Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.” 2018. Web. 15 Aug 2020.

Vancouver:

Lin D. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Aug 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin D. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

21. Xie, Jing. Three Dimensional Integrated Circuit Design and Test.

Degree: 2015, Penn State University

 The emerging three-dimensional integrated circuits (3D ICs) is one of the most promising solutions for future IC designs. 3D stacking enables much higher memory bandwidth… (more)

Subjects/Keywords: VLSI; Three Dimensional Integrated Circuit; Testing; Circuit Design; Low Power; High Performance

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xie, J. (2015). Three Dimensional Integrated Circuit Design and Test. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/26281

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Jing. “Three Dimensional Integrated Circuit Design and Test.” 2015. Thesis, Penn State University. Accessed August 15, 2020. https://submit-etda.libraries.psu.edu/catalog/26281.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Jing. “Three Dimensional Integrated Circuit Design and Test.” 2015. Web. 15 Aug 2020.

Vancouver:

Xie J. Three Dimensional Integrated Circuit Design and Test. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Aug 15]. Available from: https://submit-etda.libraries.psu.edu/catalog/26281.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie J. Three Dimensional Integrated Circuit Design and Test. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/26281

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Autònoma de Barcelona

22. Díaz Fortuny, Javier. A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs.

Degree: Departament d'Enginyeria Electrònica, 2019, Universitat Autònoma de Barcelona

 Since the invention in 1960 of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the CMOS semiconductor industry has invariably invented new feats to progressively… (more)

Subjects/Keywords: Circuit integrat; Circuito integrado; Integrated circuit; MOSFET; Variabilitat; Variabilidad; Variability; Tecnologies; 621.3

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Díaz Fortuny, J. (2019). A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs. (Thesis). Universitat Autònoma de Barcelona. Retrieved from http://hdl.handle.net/10803/667954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Díaz Fortuny, Javier. “A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs.” 2019. Thesis, Universitat Autònoma de Barcelona. Accessed August 15, 2020. http://hdl.handle.net/10803/667954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Díaz Fortuny, Javier. “A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs.” 2019. Web. 15 Aug 2020.

Vancouver:

Díaz Fortuny J. A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs. [Internet] [Thesis]. Universitat Autònoma de Barcelona; 2019. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/10803/667954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Díaz Fortuny J. A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs. [Thesis]. Universitat Autònoma de Barcelona; 2019. Available from: http://hdl.handle.net/10803/667954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Grenoble

23. Lacord, Joris. Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm : Models developpment for power performance assessment of advanced CMOS technologies sub-20nm.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

Depuis la commercialisation du premier circuit intégré en 1971, l'industrie de la microélectronique s'est fixée comme leitmotiv de réduire les dimensions des transistors MOSFETs, en… (more)

Subjects/Keywords: CMOS; MASTAR; Modèle; Performance; Circuit intégré; CMOS; MASTAR; Model; Integrated circuit; Speed

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lacord, J. (2012). Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm : Models developpment for power performance assessment of advanced CMOS technologies sub-20nm. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT073

Chicago Manual of Style (16th Edition):

Lacord, Joris. “Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm : Models developpment for power performance assessment of advanced CMOS technologies sub-20nm.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed August 15, 2020. http://www.theses.fr/2012GRENT073.

MLA Handbook (7th Edition):

Lacord, Joris. “Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm : Models developpment for power performance assessment of advanced CMOS technologies sub-20nm.” 2012. Web. 15 Aug 2020.

Vancouver:

Lacord J. Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm : Models developpment for power performance assessment of advanced CMOS technologies sub-20nm. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2020 Aug 15]. Available from: http://www.theses.fr/2012GRENT073.

Council of Science Editors:

Lacord J. Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm : Models developpment for power performance assessment of advanced CMOS technologies sub-20nm. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT073


University of Illinois – Urbana-Champaign

24. Assem, Pourya. In-sensor information processing for resource-limited platforms on flexible epidermal substrates.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Moving towards the age of big data, the demand for embedded processing has been drastically increasing to make inference and intelligent decisions at lower architectural… (more)

Subjects/Keywords: Application-specific integrated circuit (ASIC); Integrated circuit (IC); Near-field communication (NFC); Pan-Tompkins Algorithm (PTA); Photoplethysmogram (PPG); Epidermal electronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Assem, P. (2016). In-sensor information processing for resource-limited platforms on flexible epidermal substrates. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Assem, Pourya. “In-sensor information processing for resource-limited platforms on flexible epidermal substrates.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed August 15, 2020. http://hdl.handle.net/2142/95628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Assem, Pourya. “In-sensor information processing for resource-limited platforms on flexible epidermal substrates.” 2016. Web. 15 Aug 2020.

Vancouver:

Assem P. In-sensor information processing for resource-limited platforms on flexible epidermal substrates. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/2142/95628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Assem P. In-sensor information processing for resource-limited platforms on flexible epidermal substrates. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

25. Podzemný, Jakub. Univerzální emulační platforma pro ověřování návrhu integrovaných obvodů: Universal Emulation Platform for Checking the Designs of the Integrated Circuits.

Degree: 2019, Brno University of Technology

 This work deals with verification possibilities of integrated circuits, especially with hardware emulation. The first part of the text briefly describes designing process of an… (more)

Subjects/Keywords: integrovaný obvod; návrh integrovaných obvodů; emulace; emulační platforma; integrated circuit; integrated circuit design; emulation; emulation platform

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Podzemný, J. (2019). Univerzální emulační platforma pro ověřování návrhu integrovaných obvodů: Universal Emulation Platform for Checking the Designs of the Integrated Circuits. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/80767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Podzemný, Jakub. “Univerzální emulační platforma pro ověřování návrhu integrovaných obvodů: Universal Emulation Platform for Checking the Designs of the Integrated Circuits.” 2019. Thesis, Brno University of Technology. Accessed August 15, 2020. http://hdl.handle.net/11012/80767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Podzemný, Jakub. “Univerzální emulační platforma pro ověřování návrhu integrovaných obvodů: Universal Emulation Platform for Checking the Designs of the Integrated Circuits.” 2019. Web. 15 Aug 2020.

Vancouver:

Podzemný J. Univerzální emulační platforma pro ověřování návrhu integrovaných obvodů: Universal Emulation Platform for Checking the Designs of the Integrated Circuits. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/11012/80767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Podzemný J. Univerzální emulační platforma pro ověřování návrhu integrovaných obvodů: Universal Emulation Platform for Checking the Designs of the Integrated Circuits. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/80767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Chuang, Sheng-Chih. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.

Degree: Master, Electrical Engineering, 2015, NSYSU

 This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a… (more)

Subjects/Keywords: Nerve cuff recording; Electroneurogram; Sample-and-hold circuit; Application-specific integrated circuit (ASIC); Low power circuit; Velocity selective recording

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chuang, S. (2015). Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Thesis, NSYSU. Accessed August 15, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Web. 15 Aug 2020.

Vancouver:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Aug 15]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

27. Kavimandan, Mandar Dilip. Integrated Inductors.

Degree: MSEgr, Electrical Engineering, 2008, Wright State University

Integrated inductors, also called spiral inductors, on-chip inductors, or planarinductors, are inseparable part in radio frequency integrated circuits (RFICs). Increasing growth in RFICs from… (more)

Subjects/Keywords: Electrical Engineering; Integrated Inductors; Planar Inductors; Spiral Inductors; Spiral Calculator; PCB Inductors; Integrated Circuit Transformers

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kavimandan, M. D. (2008). Integrated Inductors. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1229637343

Chicago Manual of Style (16th Edition):

Kavimandan, Mandar Dilip. “Integrated Inductors.” 2008. Masters Thesis, Wright State University. Accessed August 15, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1229637343.

MLA Handbook (7th Edition):

Kavimandan, Mandar Dilip. “Integrated Inductors.” 2008. Web. 15 Aug 2020.

Vancouver:

Kavimandan MD. Integrated Inductors. [Internet] [Masters thesis]. Wright State University; 2008. [cited 2020 Aug 15]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1229637343.

Council of Science Editors:

Kavimandan MD. Integrated Inductors. [Masters Thesis]. Wright State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1229637343


University of Washington

28. Streshinsky, Matthew Akio. A Terabit Optical Link in Silicon.

Degree: PhD, 2015, University of Washington

 As data centers grow, there is a need to be able to densely pack low power, high bandwidth, kilometer-reach interconnects into the same available rack… (more)

Subjects/Keywords: CMOS Photonics; Integrated Optics; Photonic Integrated Circuit; Silicon Photonics; Electrical engineering; Optics; electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Streshinsky, M. A. (2015). A Terabit Optical Link in Silicon. (Doctoral Dissertation). University of Washington. Retrieved from http://hdl.handle.net/1773/33153

Chicago Manual of Style (16th Edition):

Streshinsky, Matthew Akio. “A Terabit Optical Link in Silicon.” 2015. Doctoral Dissertation, University of Washington. Accessed August 15, 2020. http://hdl.handle.net/1773/33153.

MLA Handbook (7th Edition):

Streshinsky, Matthew Akio. “A Terabit Optical Link in Silicon.” 2015. Web. 15 Aug 2020.

Vancouver:

Streshinsky MA. A Terabit Optical Link in Silicon. [Internet] [Doctoral dissertation]. University of Washington; 2015. [cited 2020 Aug 15]. Available from: http://hdl.handle.net/1773/33153.

Council of Science Editors:

Streshinsky MA. A Terabit Optical Link in Silicon. [Doctoral Dissertation]. University of Washington; 2015. Available from: http://hdl.handle.net/1773/33153


University of California – Santa Cruz

29. McDonald, Mark. Metamaterials and THz Integrated Circuits.

Degree: Electrical Engineering, 2017, University of California – Santa Cruz

 THz integrated circuits are now possible with improved processes that have increased fτ and fmax. The increased fτ and fmax enable the use of metamaterials… (more)

Subjects/Keywords: Electrical engineering; integrated circuit; metamaterial; modes; resonator; terahertz; THz

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

McDonald, M. (2017). Metamaterials and THz Integrated Circuits. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/3bq8594c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

McDonald, Mark. “Metamaterials and THz Integrated Circuits.” 2017. Thesis, University of California – Santa Cruz. Accessed August 15, 2020. http://www.escholarship.org/uc/item/3bq8594c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

McDonald, Mark. “Metamaterials and THz Integrated Circuits.” 2017. Web. 15 Aug 2020.

Vancouver:

McDonald M. Metamaterials and THz Integrated Circuits. [Internet] [Thesis]. University of California – Santa Cruz; 2017. [cited 2020 Aug 15]. Available from: http://www.escholarship.org/uc/item/3bq8594c.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

McDonald M. Metamaterials and THz Integrated Circuits. [Thesis]. University of California – Santa Cruz; 2017. Available from: http://www.escholarship.org/uc/item/3bq8594c

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – San Diego

30. Kijsanayotin, Tissana. Electronically Reconfigurable Circuits for Millimeter-Wave and Beyond.

Degree: Electrical Engineering (Electronic Circuits and Systems), 2015, University of California – San Diego

 Millimeter-wave (mm-Wave) wireless communication systems often employ phased array architecture to overcome the high path loss and to provide spatial selectivity. As the number of… (more)

Subjects/Keywords: Electrical engineering; CMOS; Integrated Circuit; Millimeter-Wave; Reconfigurable; SiGe; Silicon

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kijsanayotin, T. (2015). Electronically Reconfigurable Circuits for Millimeter-Wave and Beyond. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/9k00v4mz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kijsanayotin, Tissana. “Electronically Reconfigurable Circuits for Millimeter-Wave and Beyond.” 2015. Thesis, University of California – San Diego. Accessed August 15, 2020. http://www.escholarship.org/uc/item/9k00v4mz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kijsanayotin, Tissana. “Electronically Reconfigurable Circuits for Millimeter-Wave and Beyond.” 2015. Web. 15 Aug 2020.

Vancouver:

Kijsanayotin T. Electronically Reconfigurable Circuits for Millimeter-Wave and Beyond. [Internet] [Thesis]. University of California – San Diego; 2015. [cited 2020 Aug 15]. Available from: http://www.escholarship.org/uc/item/9k00v4mz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kijsanayotin T. Electronically Reconfigurable Circuits for Millimeter-Wave and Beyond. [Thesis]. University of California – San Diego; 2015. Available from: http://www.escholarship.org/uc/item/9k00v4mz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [18]

.