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You searched for subject:( hardware accelerator). Showing records 1 – 30 of 50 total matches.

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University of Toronto

1. Siu, Kevin. Reducing Off-chip Memory Accesses in Deep Neural Network Accelerators.

Degree: 2019, University of Toronto

The popularity of deep neural networks (DNNs) has led to widespread development of specialized hardware for accelerating their computations. Many designs employ a memory system… (more)

Subjects/Keywords: Hardware Accelerator; Neural Network; 0464

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APA (6th Edition):

Siu, K. (2019). Reducing Off-chip Memory Accesses in Deep Neural Network Accelerators. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/98351

Chicago Manual of Style (16th Edition):

Siu, Kevin. “Reducing Off-chip Memory Accesses in Deep Neural Network Accelerators.” 2019. Masters Thesis, University of Toronto. Accessed December 03, 2020. http://hdl.handle.net/1807/98351.

MLA Handbook (7th Edition):

Siu, Kevin. “Reducing Off-chip Memory Accesses in Deep Neural Network Accelerators.” 2019. Web. 03 Dec 2020.

Vancouver:

Siu K. Reducing Off-chip Memory Accesses in Deep Neural Network Accelerators. [Internet] [Masters thesis]. University of Toronto; 2019. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/1807/98351.

Council of Science Editors:

Siu K. Reducing Off-chip Memory Accesses in Deep Neural Network Accelerators. [Masters Thesis]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/98351


Delft University of Technology

2. De Wit, R. (author). PPU: A Protocol Parsing Unit in Hardware.

Degree: 2015, Delft University of Technology

The design of a protocol parser in hardware based on language theory to improve time-to-market, reduce development cost and increase performance compared to protocol parsing… (more)

Subjects/Keywords: protocol language parser hardware accelerator

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APA (6th Edition):

De Wit, R. (. (2015). PPU: A Protocol Parsing Unit in Hardware. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8fd22239-6559-48bd-8f55-54c33d64dd32

Chicago Manual of Style (16th Edition):

De Wit, R (author). “PPU: A Protocol Parsing Unit in Hardware.” 2015. Masters Thesis, Delft University of Technology. Accessed December 03, 2020. http://resolver.tudelft.nl/uuid:8fd22239-6559-48bd-8f55-54c33d64dd32.

MLA Handbook (7th Edition):

De Wit, R (author). “PPU: A Protocol Parsing Unit in Hardware.” 2015. Web. 03 Dec 2020.

Vancouver:

De Wit R(. PPU: A Protocol Parsing Unit in Hardware. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Dec 03]. Available from: http://resolver.tudelft.nl/uuid:8fd22239-6559-48bd-8f55-54c33d64dd32.

Council of Science Editors:

De Wit R(. PPU: A Protocol Parsing Unit in Hardware. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:8fd22239-6559-48bd-8f55-54c33d64dd32


University of Manchester

3. Clarkson, James. Compiler and Runtime Support for Heterogeneous Programming.

Degree: 2019, University of Manchester

 Over the last decade computer architectures have changed dramatically leaving us in a position where nearly every desktop computer, laptop, server or mobile phone, has… (more)

Subjects/Keywords: Programming languages; Java; Hardware Accelerator; GPGPU

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APA (6th Edition):

Clarkson, J. (2019). Compiler and Runtime Support for Heterogeneous Programming. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:318477

Chicago Manual of Style (16th Edition):

Clarkson, James. “Compiler and Runtime Support for Heterogeneous Programming.” 2019. Doctoral Dissertation, University of Manchester. Accessed December 03, 2020. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:318477.

MLA Handbook (7th Edition):

Clarkson, James. “Compiler and Runtime Support for Heterogeneous Programming.” 2019. Web. 03 Dec 2020.

Vancouver:

Clarkson J. Compiler and Runtime Support for Heterogeneous Programming. [Internet] [Doctoral dissertation]. University of Manchester; 2019. [cited 2020 Dec 03]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:318477.

Council of Science Editors:

Clarkson J. Compiler and Runtime Support for Heterogeneous Programming. [Doctoral Dissertation]. University of Manchester; 2019. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:318477


University of Manchester

4. Clarkson, James. Compiler and runtime support for heterogeneous programming.

Degree: PhD, 2019, University of Manchester

 Over the last decade computer architectures have changed dramatically leaving us in a position where nearly every desktop computer, laptop, server or mobile phone, has… (more)

Subjects/Keywords: Hardware Accelerator; GPGPU; Programming languages; Java

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APA (6th Edition):

Clarkson, J. (2019). Compiler and runtime support for heterogeneous programming. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/compiler-and-runtime-support-for-heterogeneous-programming(3a83a155-390c-41d8-ab44-20cf963b4f94).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799440

Chicago Manual of Style (16th Edition):

Clarkson, James. “Compiler and runtime support for heterogeneous programming.” 2019. Doctoral Dissertation, University of Manchester. Accessed December 03, 2020. https://www.research.manchester.ac.uk/portal/en/theses/compiler-and-runtime-support-for-heterogeneous-programming(3a83a155-390c-41d8-ab44-20cf963b4f94).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799440.

MLA Handbook (7th Edition):

Clarkson, James. “Compiler and runtime support for heterogeneous programming.” 2019. Web. 03 Dec 2020.

Vancouver:

Clarkson J. Compiler and runtime support for heterogeneous programming. [Internet] [Doctoral dissertation]. University of Manchester; 2019. [cited 2020 Dec 03]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/compiler-and-runtime-support-for-heterogeneous-programming(3a83a155-390c-41d8-ab44-20cf963b4f94).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799440.

Council of Science Editors:

Clarkson J. Compiler and runtime support for heterogeneous programming. [Doctoral Dissertation]. University of Manchester; 2019. Available from: https://www.research.manchester.ac.uk/portal/en/theses/compiler-and-runtime-support-for-heterogeneous-programming(3a83a155-390c-41d8-ab44-20cf963b4f94).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.799440


Virginia Tech

5. Pahlavan Yali, Moein. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance… (more)

Subjects/Keywords: Embedded Systems; FPGA; Hardware Accelerator; Performance Model

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APA (6th Edition):

Pahlavan Yali, M. (2015). FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51193

Chicago Manual of Style (16th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Masters Thesis, Virginia Tech. Accessed December 03, 2020. http://hdl.handle.net/10919/51193.

MLA Handbook (7th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Web. 03 Dec 2020.

Vancouver:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10919/51193.

Council of Science Editors:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51193


University of California – San Diego

6. Lotfi, Atieh. Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators.

Degree: Computer Science and Engineering, 2018, University of California – San Diego

 Faced with the exponential growth in computing requirements, programmable hardware accelerators, such as GPUs and FPGAs, are becoming increasingly popular in high performance computing systems.… (more)

Subjects/Keywords: Computer science; Computer engineering; Error mitigation; FPGA; GPU; Hardware resource optimization; Programmable hardware accelerator

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APA (6th Edition):

Lotfi, A. (2018). Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/1ww3k3b8

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lotfi, Atieh. “Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators.” 2018. Thesis, University of California – San Diego. Accessed December 03, 2020. http://www.escholarship.org/uc/item/1ww3k3b8.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lotfi, Atieh. “Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators.” 2018. Web. 03 Dec 2020.

Vancouver:

Lotfi A. Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. [Internet] [Thesis]. University of California – San Diego; 2018. [cited 2020 Dec 03]. Available from: http://www.escholarship.org/uc/item/1ww3k3b8.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lotfi A. Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. [Thesis]. University of California – San Diego; 2018. Available from: http://www.escholarship.org/uc/item/1ww3k3b8

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

7. Sabarad, Jagdish Shivaji. A Reconfigurable Accelerator For Neuromorphic Object Recognition.

Degree: 2016, Penn State University

 A significant challenge in creating machines with artificial vision is designing systems which can process visual information as efficiently as the human brain. Recent advances… (more)

Subjects/Keywords: Hardware Accelerator; HMAX; FPGA; Machine Vision; Computer Vision; Hardware Architecture; High Performance Computing; Bio-Vision

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APA (6th Edition):

Sabarad, J. S. (2016). A Reconfigurable Accelerator For Neuromorphic Object Recognition. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/29520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sabarad, Jagdish Shivaji. “A Reconfigurable Accelerator For Neuromorphic Object Recognition.” 2016. Thesis, Penn State University. Accessed December 03, 2020. https://submit-etda.libraries.psu.edu/catalog/29520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sabarad, Jagdish Shivaji. “A Reconfigurable Accelerator For Neuromorphic Object Recognition.” 2016. Web. 03 Dec 2020.

Vancouver:

Sabarad JS. A Reconfigurable Accelerator For Neuromorphic Object Recognition. [Internet] [Thesis]. Penn State University; 2016. [cited 2020 Dec 03]. Available from: https://submit-etda.libraries.psu.edu/catalog/29520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sabarad JS. A Reconfigurable Accelerator For Neuromorphic Object Recognition. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/29520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

8. Stokke, Keaten. An FPGA-Based Hardware Accelerator For The Digital Image Correlation Engine.

Degree: MSCmpE, 2020, University of Arkansas

  The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare… (more)

Subjects/Keywords: Accelerator; DIC; DICe; FPGA; Hardware; Image; Hardware Systems; Numerical Analysis and Scientific Computing; Signal Processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stokke, K. (2020). An FPGA-Based Hardware Accelerator For The Digital Image Correlation Engine. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3664

Chicago Manual of Style (16th Edition):

Stokke, Keaten. “An FPGA-Based Hardware Accelerator For The Digital Image Correlation Engine.” 2020. Masters Thesis, University of Arkansas. Accessed December 03, 2020. https://scholarworks.uark.edu/etd/3664.

MLA Handbook (7th Edition):

Stokke, Keaten. “An FPGA-Based Hardware Accelerator For The Digital Image Correlation Engine.” 2020. Web. 03 Dec 2020.

Vancouver:

Stokke K. An FPGA-Based Hardware Accelerator For The Digital Image Correlation Engine. [Internet] [Masters thesis]. University of Arkansas; 2020. [cited 2020 Dec 03]. Available from: https://scholarworks.uark.edu/etd/3664.

Council of Science Editors:

Stokke K. An FPGA-Based Hardware Accelerator For The Digital Image Correlation Engine. [Masters Thesis]. University of Arkansas; 2020. Available from: https://scholarworks.uark.edu/etd/3664


Universidade do Rio Grande do Sul

9. Diniz, Claudio Machado. Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard.

Degree: 2015, Universidade do Rio Grande do Sul

 The demand for ultra-high resolution video (beyond 1920x1080 pixels) led to the need of developing new and more efficient video coding standards to provide high… (more)

Subjects/Keywords: Microeletrônica; HEVC; Vídeo digital; Hardware accelerator; Video coding architecture; Reconfigurable architectures

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APA (6th Edition):

Diniz, C. M. (2015). Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/118394

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Diniz, Claudio Machado. “Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed December 03, 2020. http://hdl.handle.net/10183/118394.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Diniz, Claudio Machado. “Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard.” 2015. Web. 03 Dec 2020.

Vancouver:

Diniz CM. Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10183/118394.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Diniz CM. Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/118394

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Ottawa

10. Wang, Wei. Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment .

Degree: 2013, University of Ottawa

 In this thesis we present pvFPGA, the first system design solution for virtualizing an FPGA - based hardware accelerator on the x86 platform. The accelerator(more)

Subjects/Keywords: FPGA; hardware accelerator; paravirtualization; pvFPGA; coprovisor; data pool; DMA context switch

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APA (6th Edition):

Wang, W. (2013). Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/24283

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Wei. “Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment .” 2013. Thesis, University of Ottawa. Accessed December 03, 2020. http://hdl.handle.net/10393/24283.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Wei. “Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment .” 2013. Web. 03 Dec 2020.

Vancouver:

Wang W. Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment . [Internet] [Thesis]. University of Ottawa; 2013. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10393/24283.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment . [Thesis]. University of Ottawa; 2013. Available from: http://hdl.handle.net/10393/24283

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas State University – San Marcos

11. Ranganathapura Chandrai G, Karuna. Hardware Accelerator for Elias Gamma Code.

Degree: MS, Engineering, 2017, Texas State University – San Marcos

 Elias Gamma code, developed by Peter Elias, is a universal lossless compression method applied to unbounded positive integers. Extensive research on this coding technique has… (more)

Subjects/Keywords: Hardware accelerator; Elias Gamma; Compression; Decompression; Packing; Unpacking; FPGA; ASIC

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APA (6th Edition):

Ranganathapura Chandrai G, K. (2017). Hardware Accelerator for Elias Gamma Code. (Masters Thesis). Texas State University – San Marcos. Retrieved from https://digital.library.txstate.edu/handle/10877/8508

Chicago Manual of Style (16th Edition):

Ranganathapura Chandrai G, Karuna. “Hardware Accelerator for Elias Gamma Code.” 2017. Masters Thesis, Texas State University – San Marcos. Accessed December 03, 2020. https://digital.library.txstate.edu/handle/10877/8508.

MLA Handbook (7th Edition):

Ranganathapura Chandrai G, Karuna. “Hardware Accelerator for Elias Gamma Code.” 2017. Web. 03 Dec 2020.

Vancouver:

Ranganathapura Chandrai G K. Hardware Accelerator for Elias Gamma Code. [Internet] [Masters thesis]. Texas State University – San Marcos; 2017. [cited 2020 Dec 03]. Available from: https://digital.library.txstate.edu/handle/10877/8508.

Council of Science Editors:

Ranganathapura Chandrai G K. Hardware Accelerator for Elias Gamma Code. [Masters Thesis]. Texas State University – San Marcos; 2017. Available from: https://digital.library.txstate.edu/handle/10877/8508


University of Cincinnati

12. Anderson, Thomas. Built-In Self Training of Hardware-Based Neural Networks.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2017, University of Cincinnati

 Articial neural networks and deep learning are a topic of increasing interest in computing. This has spurred investigation into dedicated hardware like accelerators to speed… (more)

Subjects/Keywords: Computer Engineering; neural networks; backpropagation algorithm; training; accelerator; hardware; function approximation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Anderson, T. (2017). Built-In Self Training of Hardware-Based Neural Networks. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1512039036199393

Chicago Manual of Style (16th Edition):

Anderson, Thomas. “Built-In Self Training of Hardware-Based Neural Networks.” 2017. Masters Thesis, University of Cincinnati. Accessed December 03, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1512039036199393.

MLA Handbook (7th Edition):

Anderson, Thomas. “Built-In Self Training of Hardware-Based Neural Networks.” 2017. Web. 03 Dec 2020.

Vancouver:

Anderson T. Built-In Self Training of Hardware-Based Neural Networks. [Internet] [Masters thesis]. University of Cincinnati; 2017. [cited 2020 Dec 03]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1512039036199393.

Council of Science Editors:

Anderson T. Built-In Self Training of Hardware-Based Neural Networks. [Masters Thesis]. University of Cincinnati; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1512039036199393


NSYSU

13. Wu, Pei-Hsuan. Architecture Design and Implementation of Deep Neural Network Hardware Accelerators.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 Deep Neural Networks (DNN) widely used in computer vision applications have superior performance in image classification and object detection. However, the huge amount of data… (more)

Subjects/Keywords: CNN hardware accelerator; deep neural network (DNN); convolutional neural network (CNN); machine learning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, P. (2018). Architecture Design and Implementation of Deep Neural Network Hardware Accelerators. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Pei-Hsuan. “Architecture Design and Implementation of Deep Neural Network Hardware Accelerators.” 2018. Thesis, NSYSU. Accessed December 03, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Pei-Hsuan. “Architecture Design and Implementation of Deep Neural Network Hardware Accelerators.” 2018. Web. 03 Dec 2020.

Vancouver:

Wu P. Architecture Design and Implementation of Deep Neural Network Hardware Accelerators. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Dec 03]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Architecture Design and Implementation of Deep Neural Network Hardware Accelerators. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

14. Liu, Boyan. A Data Sorting Hardware Accelerator on FPGA.

Degree: Electrical Engineering and Computer Science (EECS), 2020, KTH

In recent years, with the rise of the application of big data, efficiency has become more important for data processing, and simple sorting methods… (more)

Subjects/Keywords: Data Sorting; Hardware Accelerator Algorithm; Block Circuit; FPGA; Computer and Information Sciences; Data- och informationsvetenskap

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APA (6th Edition):

Liu, B. (2020). A Data Sorting Hardware Accelerator on FPGA. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Boyan. “A Data Sorting Hardware Accelerator on FPGA.” 2020. Thesis, KTH. Accessed December 03, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Boyan. “A Data Sorting Hardware Accelerator on FPGA.” 2020. Web. 03 Dec 2020.

Vancouver:

Liu B. A Data Sorting Hardware Accelerator on FPGA. [Internet] [Thesis]. KTH; 2020. [cited 2020 Dec 03]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu B. A Data Sorting Hardware Accelerator on FPGA. [Thesis]. KTH; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

15. [No author]. On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications .

Degree: 2013, Washington State University

 Large-scale integration of multiple cores on a single chip is the current answer to the challenge of attaining higher computation throughput while restricting power consumption… (more)

Subjects/Keywords: Computer engineering; computational biology; hardware accelerator; high-performance computing; multicore; network-on-chip

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APA (6th Edition):

author], [. (2013). On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/4716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications .” 2013. Thesis, Washington State University. Accessed December 03, 2020. http://hdl.handle.net/2376/4716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications .” 2013. Web. 03 Dec 2020.

Vancouver:

author] [. On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications . [Internet] [Thesis]. Washington State University; 2013. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/2376/4716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications . [Thesis]. Washington State University; 2013. Available from: http://hdl.handle.net/2376/4716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Alhamwi, Ali. Co-design hardware/software of real time vision system on FPGA for obstacle detection : Conception conjointe matériel-logiciel d'un système de vision temps réel sur FPGA pour la détection d'obstacles.

Degree: Docteur es, Systèmes embarqués, 2016, Université Toulouse III – Paul Sabatier

La détection, localisation d'obstacles et la reconstruction de carte d'occupation 2D sont des fonctions de base pour un robot navigant dans un environnement intérieure lorsque… (more)

Subjects/Keywords: FPGA; Détection d'obstacles; Vision; Robotique; Accélérateur matérielle; FPGA; OBSTACLE DETECTION; VISION; ROBOTIC; HARDWARE ACCELERATOR

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APA (6th Edition):

Alhamwi, A. (2016). Co-design hardware/software of real time vision system on FPGA for obstacle detection : Conception conjointe matériel-logiciel d'un système de vision temps réel sur FPGA pour la détection d'obstacles. (Doctoral Dissertation). Université Toulouse III – Paul Sabatier. Retrieved from http://www.theses.fr/2016TOU30342

Chicago Manual of Style (16th Edition):

Alhamwi, Ali. “Co-design hardware/software of real time vision system on FPGA for obstacle detection : Conception conjointe matériel-logiciel d'un système de vision temps réel sur FPGA pour la détection d'obstacles.” 2016. Doctoral Dissertation, Université Toulouse III – Paul Sabatier. Accessed December 03, 2020. http://www.theses.fr/2016TOU30342.

MLA Handbook (7th Edition):

Alhamwi, Ali. “Co-design hardware/software of real time vision system on FPGA for obstacle detection : Conception conjointe matériel-logiciel d'un système de vision temps réel sur FPGA pour la détection d'obstacles.” 2016. Web. 03 Dec 2020.

Vancouver:

Alhamwi A. Co-design hardware/software of real time vision system on FPGA for obstacle detection : Conception conjointe matériel-logiciel d'un système de vision temps réel sur FPGA pour la détection d'obstacles. [Internet] [Doctoral dissertation]. Université Toulouse III – Paul Sabatier; 2016. [cited 2020 Dec 03]. Available from: http://www.theses.fr/2016TOU30342.

Council of Science Editors:

Alhamwi A. Co-design hardware/software of real time vision system on FPGA for obstacle detection : Conception conjointe matériel-logiciel d'un système de vision temps réel sur FPGA pour la détection d'obstacles. [Doctoral Dissertation]. Université Toulouse III – Paul Sabatier; 2016. Available from: http://www.theses.fr/2016TOU30342

17. Facchetti, Jeremy. HAALO : A cloud native hardware accelerator abstraction with low overhead.

Degree: Computer Science, 2019, Luleå University of Technology

  With the upcoming 5G deployment and the exponentially increasing data transmitted over cellular networks, off the shelf hardware won't provide enough performance to cope… (more)

Subjects/Keywords: cloud; 5g; hardware accelerator; kubernetes; docker; vnf; nfv; cloud native; virtualization; Computer Systems; Datorsystem

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APA (6th Edition):

Facchetti, J. (2019). HAALO : A cloud native hardware accelerator abstraction with low overhead. (Thesis). Luleå University of Technology. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Facchetti, Jeremy. “HAALO : A cloud native hardware accelerator abstraction with low overhead.” 2019. Thesis, Luleå University of Technology. Accessed December 03, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Facchetti, Jeremy. “HAALO : A cloud native hardware accelerator abstraction with low overhead.” 2019. Web. 03 Dec 2020.

Vancouver:

Facchetti J. HAALO : A cloud native hardware accelerator abstraction with low overhead. [Internet] [Thesis]. Luleå University of Technology; 2019. [cited 2020 Dec 03]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Facchetti J. HAALO : A cloud native hardware accelerator abstraction with low overhead. [Thesis]. Luleå University of Technology; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

18. Zheng, Feng, M.S. in Engineering. Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA.

Degree: MSin Engineering, Electrical and Computer Engineering, 2010, University of Texas – Austin

 The report detailing the Hardware Accelerator for the JPEG encoder is organized into three sections. First, it will review the processes of the Joint Photographic… (more)

Subjects/Keywords: JPEG; Hardware accelerator; Discrete cosine transform

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APA (6th Edition):

Zheng, Feng, M. S. i. E. (2010). Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-12-2381

Chicago Manual of Style (16th Edition):

Zheng, Feng, M S in Engineering. “Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA.” 2010. Masters Thesis, University of Texas – Austin. Accessed December 03, 2020. http://hdl.handle.net/2152/ETD-UT-2010-12-2381.

MLA Handbook (7th Edition):

Zheng, Feng, M S in Engineering. “Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA.” 2010. Web. 03 Dec 2020.

Vancouver:

Zheng, Feng MSiE. Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA. [Internet] [Masters thesis]. University of Texas – Austin; 2010. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-12-2381.

Council of Science Editors:

Zheng, Feng MSiE. Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA. [Masters Thesis]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-12-2381


York University

19. Wu, Zhongpan. Hardware Accelerated DNA Sequencing.

Degree: MASc - Master of Applied Science, Electrical and Computer Engineering, 2019, York University

 DNA sequencing technology is quickly evolving. The latest developments ex- ploit nanopore sensing and microelectronics to realize real-time, hand-held devices. A critical limitation in these… (more)

Subjects/Keywords: Bioinformatics; DNA Sequencing; Nanopore; Real-time; Hand-held; Sequencing device; FPGA; Hardware Accelerator; PCIe; CPU; Basecalling speed; Power Con- sumption

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APA (6th Edition):

Wu, Z. (2019). Hardware Accelerated DNA Sequencing. (Masters Thesis). York University. Retrieved from http://hdl.handle.net/10315/36356

Chicago Manual of Style (16th Edition):

Wu, Zhongpan. “Hardware Accelerated DNA Sequencing.” 2019. Masters Thesis, York University. Accessed December 03, 2020. http://hdl.handle.net/10315/36356.

MLA Handbook (7th Edition):

Wu, Zhongpan. “Hardware Accelerated DNA Sequencing.” 2019. Web. 03 Dec 2020.

Vancouver:

Wu Z. Hardware Accelerated DNA Sequencing. [Internet] [Masters thesis]. York University; 2019. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10315/36356.

Council of Science Editors:

Wu Z. Hardware Accelerated DNA Sequencing. [Masters Thesis]. York University; 2019. Available from: http://hdl.handle.net/10315/36356

20. Kitrungrotsakul, Yuranan. Hardware Acceleration of Real-time Image Processing for Vehicle Control.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:田中 清史

情報科学研究科

修士

Subjects/Keywords: Hardware Accelerator; GPU; Programmable logic; Embedded system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kitrungrotsakul, Y. (n.d.). Hardware Acceleration of Real-time Image Processing for Vehicle Control. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/14794

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kitrungrotsakul, Yuranan. “Hardware Acceleration of Real-time Image Processing for Vehicle Control.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed December 03, 2020. http://hdl.handle.net/10119/14794.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kitrungrotsakul, Yuranan. “Hardware Acceleration of Real-time Image Processing for Vehicle Control.” Web. 03 Dec 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Kitrungrotsakul Y. Hardware Acceleration of Real-time Image Processing for Vehicle Control. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10119/14794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Kitrungrotsakul Y. Hardware Acceleration of Real-time Image Processing for Vehicle Control. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/14794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Delft University of Technology

21. Van Wijnen, P.A. (author). Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms.

Degree: 2009, Delft University of Technology

This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University… (more)

Subjects/Keywords: Hardware Accelerator; Pattern Recognition Algorithm; FPGA; Parallel Computing

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APA (6th Edition):

Van Wijnen, P. A. (. (2009). Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:e8756f82-ebde-4e0f-aa09-ab2445b962ad

Chicago Manual of Style (16th Edition):

Van Wijnen, P A (author). “Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms.” 2009. Masters Thesis, Delft University of Technology. Accessed December 03, 2020. http://resolver.tudelft.nl/uuid:e8756f82-ebde-4e0f-aa09-ab2445b962ad.

MLA Handbook (7th Edition):

Van Wijnen, P A (author). “Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms.” 2009. Web. 03 Dec 2020.

Vancouver:

Van Wijnen PA(. Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 Dec 03]. Available from: http://resolver.tudelft.nl/uuid:e8756f82-ebde-4e0f-aa09-ab2445b962ad.

Council of Science Editors:

Van Wijnen PA(. Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:e8756f82-ebde-4e0f-aa09-ab2445b962ad


Brno University of Technology

22. Bareš, Jan. Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry: A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores.

Degree: 2019, Brno University of Technology

 This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the… (more)

Subjects/Keywords: Hardwarová akcelerace; urychlovač; akcelerační systém; FPGA; návrh protokolu; komunikační protokol; Hardware acceleration; accelerator; acceleration system; FPGA; design of protocol; communication protocol

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APA (6th Edition):

Bareš, J. (2019). Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry: A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/80760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bareš, Jan. “Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry: A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores.” 2019. Thesis, Brno University of Technology. Accessed December 03, 2020. http://hdl.handle.net/11012/80760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bareš, Jan. “Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry: A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores.” 2019. Web. 03 Dec 2020.

Vancouver:

Bareš J. Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry: A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/11012/80760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bareš J. Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry: A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/80760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Babecki, Christopher. A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications.

Degree: MSs (Engineering), EECS - Electrical Engineering, 2015, Case Western Reserve University School of Graduate Studies

 Security is becoming an increasing concern in today's computer applications. Unfortunately, most encryption/decryption algorithms are computationally expensive and often do not map efficiently to general… (more)

Subjects/Keywords: Computer Engineering; security applications; domain-specific hardware accelerator; energy-efficiency; reconfigurable computing; side-channel attack resistance

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APA (6th Edition):

Babecki, C. (2015). A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications. (Masters Thesis). Case Western Reserve University School of Graduate Studies. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331

Chicago Manual of Style (16th Edition):

Babecki, Christopher. “A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications.” 2015. Masters Thesis, Case Western Reserve University School of Graduate Studies. Accessed December 03, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331.

MLA Handbook (7th Edition):

Babecki, Christopher. “A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications.” 2015. Web. 03 Dec 2020.

Vancouver:

Babecki C. A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications. [Internet] [Masters thesis]. Case Western Reserve University School of Graduate Studies; 2015. [cited 2020 Dec 03]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331.

Council of Science Editors:

Babecki C. A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications. [Masters Thesis]. Case Western Reserve University School of Graduate Studies; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331

24. Bhagawat, Pankaj. Hardware Accelerator for MIMO Wireless Systems.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

 Ever increasing demand for higher data rates and better Quality of Service (QoS) for a growing number of users requires new transceiver algorithms and architectures… (more)

Subjects/Keywords: MIMO wireless systems; configurable hardware; hardware accelerator; soft detection

…Available Processing Power [7] . . . . . 6 5 Architectural Flexibility Vs. Hardware… …standards. B. Hardware Implementation Perspective Fig. 4 depicts how the complexity of algorithms… …that the baseband hardware must be flexible enough to support runtime configuration. The… …Hardware Efficiency [8] erogeneous MultiProcessor System on Chip (MPSoC)… …which have multiple function hardware accelerators governed by a central processor, is… 

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APA (6th Edition):

Bhagawat, P. (2012). Hardware Accelerator for MIMO Wireless Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10364

Chicago Manual of Style (16th Edition):

Bhagawat, Pankaj. “Hardware Accelerator for MIMO Wireless Systems.” 2012. Doctoral Dissertation, Texas A&M University. Accessed December 03, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10364.

MLA Handbook (7th Edition):

Bhagawat, Pankaj. “Hardware Accelerator for MIMO Wireless Systems.” 2012. Web. 03 Dec 2020.

Vancouver:

Bhagawat P. Hardware Accelerator for MIMO Wireless Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10364.

Council of Science Editors:

Bhagawat P. Hardware Accelerator for MIMO Wireless Systems. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10364


University of Arkansas

25. Sadeghian, Abazar. Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems.

Degree: MSCmpE, 2016, University of Arkansas

  Field Programmable Gate Arrays (FPGAs) were first introduced circa 1980, and they held the promise of delivering performance levels associated with customized circuits, but… (more)

Subjects/Keywords: Applied sciences; Accelerator; Custom hardware; Field Programmable gate arrays; Hardware/software co-design; Partial reconfiguration; System on chip; Digital Circuits; Other Electrical and Computer Engineering

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APA (6th Edition):

Sadeghian, A. (2016). Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1584

Chicago Manual of Style (16th Edition):

Sadeghian, Abazar. “Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems.” 2016. Masters Thesis, University of Arkansas. Accessed December 03, 2020. https://scholarworks.uark.edu/etd/1584.

MLA Handbook (7th Edition):

Sadeghian, Abazar. “Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems.” 2016. Web. 03 Dec 2020.

Vancouver:

Sadeghian A. Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2020 Dec 03]. Available from: https://scholarworks.uark.edu/etd/1584.

Council of Science Editors:

Sadeghian A. Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1584


University of Cincinnati

26. Syed, Akber. A Hardware Interpreter for Sparse Matrix LU Factorization.

Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati

  This thesis investigated a hardware interpreter for sparse matrix LU factorization. LU factorization is one of the most commonly used methods for solving a… (more)

Subjects/Keywords: LU factorization; sparse matrices; hardware interpreter; hardware accelerator; loop unrolling

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APA (6th Edition):

Syed, A. (2002). A Hardware Interpreter for Sparse Matrix LU Factorization. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1024934521

Chicago Manual of Style (16th Edition):

Syed, Akber. “A Hardware Interpreter for Sparse Matrix LU Factorization.” 2002. Masters Thesis, University of Cincinnati. Accessed December 03, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1024934521.

MLA Handbook (7th Edition):

Syed, Akber. “A Hardware Interpreter for Sparse Matrix LU Factorization.” 2002. Web. 03 Dec 2020.

Vancouver:

Syed A. A Hardware Interpreter for Sparse Matrix LU Factorization. [Internet] [Masters thesis]. University of Cincinnati; 2002. [cited 2020 Dec 03]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1024934521.

Council of Science Editors:

Syed A. A Hardware Interpreter for Sparse Matrix LU Factorization. [Masters Thesis]. University of Cincinnati; 2002. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1024934521


Université de Grenoble

27. Prost-Boucle, Adrien. Génération rapide d'accélerateurs matériels par synthèse d'architecture sous contraintes de ressources : High-level synthesis for fast generation of hardware accelerators under resource constraints.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Université de Grenoble

Dans le domaine du calcul générique, les circuits FPGA sont très attrayants pour leur performance et leur faible consommation. Cependant, leur présence reste marginale, notamment… (more)

Subjects/Keywords: Méthodologie de conception; Synthèse d'architecture; Accélérateurs matériels; FPGA; Exploration de l'espace de conception; Design flow; High-level synthesis; Hardware accelerator; FPGA; Design space exploration; 620

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APA (6th Edition):

Prost-Boucle, A. (2014). Génération rapide d'accélerateurs matériels par synthèse d'architecture sous contraintes de ressources : High-level synthesis for fast generation of hardware accelerators under resource constraints. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT039

Chicago Manual of Style (16th Edition):

Prost-Boucle, Adrien. “Génération rapide d'accélerateurs matériels par synthèse d'architecture sous contraintes de ressources : High-level synthesis for fast generation of hardware accelerators under resource constraints.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed December 03, 2020. http://www.theses.fr/2014GRENT039.

MLA Handbook (7th Edition):

Prost-Boucle, Adrien. “Génération rapide d'accélerateurs matériels par synthèse d'architecture sous contraintes de ressources : High-level synthesis for fast generation of hardware accelerators under resource constraints.” 2014. Web. 03 Dec 2020.

Vancouver:

Prost-Boucle A. Génération rapide d'accélerateurs matériels par synthèse d'architecture sous contraintes de ressources : High-level synthesis for fast generation of hardware accelerators under resource constraints. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2020 Dec 03]. Available from: http://www.theses.fr/2014GRENT039.

Council of Science Editors:

Prost-Boucle A. Génération rapide d'accélerateurs matériels par synthèse d'architecture sous contraintes de ressources : High-level synthesis for fast generation of hardware accelerators under resource constraints. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT039


University of Michigan

28. Khan, Osama U. Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.

Degree: PhD, Electrical Engineering, 2014, University of Michigan

 The exponential growth in IC technology has enabled low-cost and increasingly capable wireless sensor nodes which provide a promising way forward to realize the vision… (more)

Subjects/Keywords: Low Power Zigbee Receiver; Compressed Sensing; Hardware Accelerator for Bayesian Network; Sub-Nyquist ADC; Distributed Intelligent Sensing; Wireless Sensor Networks; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khan, O. U. (2014). Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/107130

Chicago Manual of Style (16th Edition):

Khan, Osama U. “Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.” 2014. Doctoral Dissertation, University of Michigan. Accessed December 03, 2020. http://hdl.handle.net/2027.42/107130.

MLA Handbook (7th Edition):

Khan, Osama U. “Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.” 2014. Web. 03 Dec 2020.

Vancouver:

Khan OU. Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems. [Internet] [Doctoral dissertation]. University of Michigan; 2014. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/2027.42/107130.

Council of Science Editors:

Khan OU. Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems. [Doctoral Dissertation]. University of Michigan; 2014. Available from: http://hdl.handle.net/2027.42/107130

29. Vallero, Alessandro. HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs.

Degree: 2014, University of Illinois – Chicago

 In recent years FPGAs (Field Programmable Gate Arrays) market has grown dramatically. Increasing of performances and available resources in FPGA devices, due to technological scaling,… (more)

Subjects/Keywords: FPGA; dynamic partial reconfiguration; reconfigurable computing; hardware accelerator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vallero, A. (2014). HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/19056

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vallero, Alessandro. “HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs.” 2014. Thesis, University of Illinois – Chicago. Accessed December 03, 2020. http://hdl.handle.net/10027/19056.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vallero, Alessandro. “HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs.” 2014. Web. 03 Dec 2020.

Vancouver:

Vallero A. HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs. [Internet] [Thesis]. University of Illinois – Chicago; 2014. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10027/19056.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vallero A. HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs. [Thesis]. University of Illinois – Chicago; 2014. Available from: http://hdl.handle.net/10027/19056

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Chandramohan, Rajbharath. Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations.

Degree: MS(M.S.), Electrical and Computer Engineering, 2017, Colorado State University

Hardware accelerators are highly optimized functional blocks designed to perform specific tasks from the CPU at a higher performance. We developed a hardware accelerator for… (more)

Subjects/Keywords: Jacobi 2D; stencil; hardware accelerator; Wave 2D; optimization

…We design an FPGA-based hardware accelerator that efficiently implements the Jacobi 2D… …computation to the processing elements in the hardware accelerator and implement it on FPGA. 1.1… …in the hardware design of the accelerator. (3) Verilog implementation of a 2D… …threedimensional FDTD using floating point arithmetic. They describe in detail their hardware accelerator… …FPGA-based hardware accelerator for two dimensional FDTD based on overlapped tiling in openCL… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandramohan, R. (2017). Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/181355

Chicago Manual of Style (16th Edition):

Chandramohan, Rajbharath. “Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations.” 2017. Masters Thesis, Colorado State University. Accessed December 03, 2020. http://hdl.handle.net/10217/181355.

MLA Handbook (7th Edition):

Chandramohan, Rajbharath. “Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations.” 2017. Web. 03 Dec 2020.

Vancouver:

Chandramohan R. Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations. [Internet] [Masters thesis]. Colorado State University; 2017. [cited 2020 Dec 03]. Available from: http://hdl.handle.net/10217/181355.

Council of Science Editors:

Chandramohan R. Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations. [Masters Thesis]. Colorado State University; 2017. Available from: http://hdl.handle.net/10217/181355

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