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Dept: Computer Science and Engineering

You searched for subject:( en GPU PROGRAMMING). Showing records 1 – 30 of 100 total matches.

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The Ohio State University

1. Srivastava, Rohit Kumar. Modeling Performance of Tensor Transpose using Regression Techniques.

Degree: MS, Computer Science and Engineering, 2018, The Ohio State University

 Tensor transposition is an important primitive in many tensor algebra libraries. For example, tensor contractions are implemented using TTGT(Transpose-Transpose-GEMM-Transpose) approach. Performing efficient transpose of an… (more)

Subjects/Keywords: Computer Science; High-Performance Computing, Parallel programming, CUDA, GPU programming, Tensor Algebra, Tensor Transpose

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srivastava, R. K. (2018). Modeling Performance of Tensor Transpose using Regression Techniques. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1524080824154753

Chicago Manual of Style (16th Edition):

Srivastava, Rohit Kumar. “Modeling Performance of Tensor Transpose using Regression Techniques.” 2018. Masters Thesis, The Ohio State University. Accessed October 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1524080824154753.

MLA Handbook (7th Edition):

Srivastava, Rohit Kumar. “Modeling Performance of Tensor Transpose using Regression Techniques.” 2018. Web. 22 Oct 2019.

Vancouver:

Srivastava RK. Modeling Performance of Tensor Transpose using Regression Techniques. [Internet] [Masters thesis]. The Ohio State University; 2018. [cited 2019 Oct 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524080824154753.

Council of Science Editors:

Srivastava RK. Modeling Performance of Tensor Transpose using Regression Techniques. [Masters Thesis]. The Ohio State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524080824154753


Penn State University

2. Nistor, Dragos Mihai. CPU- and GPU-Based Triangular Surface Mesh Simplification.

Degree: MS, Computer Science and Engineering, 2012, Penn State University

 Mesh simplification and mesh compression are important processes in the realms of computer graphics and high-performance computing, as they allow the mesh to take up… (more)

Subjects/Keywords: mesh; simplification; gpu

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APA (6th Edition):

Nistor, D. M. (2012). CPU- and GPU-Based Triangular Surface Mesh Simplification. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/13892

Chicago Manual of Style (16th Edition):

Nistor, Dragos Mihai. “CPU- and GPU-Based Triangular Surface Mesh Simplification.” 2012. Masters Thesis, Penn State University. Accessed October 22, 2019. https://etda.libraries.psu.edu/catalog/13892.

MLA Handbook (7th Edition):

Nistor, Dragos Mihai. “CPU- and GPU-Based Triangular Surface Mesh Simplification.” 2012. Web. 22 Oct 2019.

Vancouver:

Nistor DM. CPU- and GPU-Based Triangular Surface Mesh Simplification. [Internet] [Masters thesis]. Penn State University; 2012. [cited 2019 Oct 22]. Available from: https://etda.libraries.psu.edu/catalog/13892.

Council of Science Editors:

Nistor DM. CPU- and GPU-Based Triangular Surface Mesh Simplification. [Masters Thesis]. Penn State University; 2012. Available from: https://etda.libraries.psu.edu/catalog/13892


NSYSU

3. Lin, Chin-li. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Although the rendering speed of modern GPUs is dramatically improved, it is still not fast enough for some applications such as real time rendering and… (more)

Subjects/Keywords: GPU; hardware; billboard; impostor

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APA (6th Edition):

Lin, C. (2014). A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Web. 22 Oct 2019.

Vancouver:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Yang, Yu-Wei. Design and Implementation of C Programming Language Extension for Parallel GPU Computing.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 NVIDIA developed a technique of executing general program on GPU, named CUDA (Compute Unified Device Architecture), in 2006. The CUDA programming model allows a group… (more)

Subjects/Keywords: CUDA; Multi-Thread; Parallelization; GPU

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APA (6th Edition):

Yang, Y. (2010). Design and Implementation of C Programming Language Extension for Parallel GPU Computing. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727110-153900

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Yu-Wei. “Design and Implementation of C Programming Language Extension for Parallel GPU Computing.” 2010. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727110-153900.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Yu-Wei. “Design and Implementation of C Programming Language Extension for Parallel GPU Computing.” 2010. Web. 22 Oct 2019.

Vancouver:

Yang Y. Design and Implementation of C Programming Language Extension for Parallel GPU Computing. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727110-153900.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang Y. Design and Implementation of C Programming Language Extension for Parallel GPU Computing. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727110-153900

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Hung, Tsz-En. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 The graphics processing units (GPUs) commonly used in mobile devices differ from those used in PCs, owing to cost and power constraints. Some embedded GPUs… (more)

Subjects/Keywords: GPU; Tile based rendering; Billboard textures; GPU memory modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hung, T. (2017). A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Web. 22 Oct 2019.

Vancouver:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Chen, Jyun-Nan. GPU Compilation and Simulation for a Specialized Embedded System GPU.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents a compiler for a GLSL programs targeted to a novel Graphics Processor Unit (GPU)developed at NSYSU. The NSYSU GPU project has developed… (more)

Subjects/Keywords: GPU; NSYSUâs GPU project; OpenGLES 2.0; LLVM; shader compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, J. (2015). GPU Compilation and Simulation for a Specialized Embedded System GPU. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Jyun-Nan. “GPU Compilation and Simulation for a Specialized Embedded System GPU.” 2015. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Jyun-Nan. “GPU Compilation and Simulation for a Specialized Embedded System GPU.” 2015. Web. 22 Oct 2019.

Vancouver:

Chen J. GPU Compilation and Simulation for a Specialized Embedded System GPU. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen J. GPU Compilation and Simulation for a Specialized Embedded System GPU. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

7. Sethia, Ankit. Dynamic Hardware Resource Management for Efficient Throughput Processing.

Degree: PhD, Computer Science and Engineering, 2015, University of Michigan

 High performance computing is evolving at a rapid pace, with throughput oriented processors such as graphics processing units (GPUs), substituting for traditional processors as the… (more)

Subjects/Keywords: GPGPU Computing; Runtime Resource Management; Throughput Processing; GPU DVFS; GPU Warp Scheduling; GPU Prefetching; Computer Science; Engineering

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APA (6th Edition):

Sethia, A. (2015). Dynamic Hardware Resource Management for Efficient Throughput Processing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113356

Chicago Manual of Style (16th Edition):

Sethia, Ankit. “Dynamic Hardware Resource Management for Efficient Throughput Processing.” 2015. Doctoral Dissertation, University of Michigan. Accessed October 22, 2019. http://hdl.handle.net/2027.42/113356.

MLA Handbook (7th Edition):

Sethia, Ankit. “Dynamic Hardware Resource Management for Efficient Throughput Processing.” 2015. Web. 22 Oct 2019.

Vancouver:

Sethia A. Dynamic Hardware Resource Management for Efficient Throughput Processing. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/2027.42/113356.

Council of Science Editors:

Sethia A. Dynamic Hardware Resource Management for Efficient Throughput Processing. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113356


NSYSU

8. DOW, HSU-KANG. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This is a simulator created base on Attila, a modern GPU architecture and open source project with the power to run games and benchmarks. This… (more)

Subjects/Keywords: GPU; OpenGL ES; GLSL ES; Simulator; Attila

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APA (6th Edition):

DOW, H. (2014). A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DOW, HSU-KANG. “A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.” 2014. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DOW, HSU-KANG. “A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.” 2014. Web. 22 Oct 2019.

Vancouver:

DOW H. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DOW H. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Tsai, An-Ti. GPU Acceleration of Eigenface of the Face Recognition System.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 To use GPGPU to speed up the computation plays an important role in many real-time applications. In this thesis we apply GPGPU to speed up… (more)

Subjects/Keywords: Face recognition; Eigenface; CUDA; GPU parallel computing; GPGPU

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APA (6th Edition):

Tsai, A. (2017). GPU Acceleration of Eigenface of the Face Recognition System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-002830

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, An-Ti. “GPU Acceleration of Eigenface of the Face Recognition System.” 2017. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-002830.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, An-Ti. “GPU Acceleration of Eigenface of the Face Recognition System.” 2017. Web. 22 Oct 2019.

Vancouver:

Tsai A. GPU Acceleration of Eigenface of the Face Recognition System. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-002830.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai A. GPU Acceleration of Eigenface of the Face Recognition System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615117-002830

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Danielsson, Max. Viability of Feature Detection on Sony Xperia Z3 using OpenCL.

Degree: Computer Science and Engineering, 2015, Department of Creative Technologies

  Context. Embedded platforms GPUs are reaching a level of perfor-mance comparable to desktop hardware. Therefore it becomes inter-esting to apply Computer Vision techniques to… (more)

Subjects/Keywords: GPU; Feature Detection; Feature Description; Embedded Device; Computer Sciences; Datavetenskap (datalogi)

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APA (6th Edition):

Danielsson, M. (2015). Viability of Feature Detection on Sony Xperia Z3 using OpenCL. (Thesis). Department of Creative Technologies. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Danielsson, Max. “Viability of Feature Detection on Sony Xperia Z3 using OpenCL.” 2015. Thesis, Department of Creative Technologies. Accessed October 22, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Danielsson, Max. “Viability of Feature Detection on Sony Xperia Z3 using OpenCL.” 2015. Web. 22 Oct 2019.

Vancouver:

Danielsson M. Viability of Feature Detection on Sony Xperia Z3 using OpenCL. [Internet] [Thesis]. Department of Creative Technologies; 2015. [cited 2019 Oct 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Danielsson M. Viability of Feature Detection on Sony Xperia Z3 using OpenCL. [Thesis]. Department of Creative Technologies; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Arafat, Md Humayun. Runtime Systems for Load Balancing and Fault Tolerance on Distributed Systems.

Degree: PhD, Computer Science and Engineering, 2014, The Ohio State University

 Exascale computing creates many challenges for scientific applications in both hardware and software. There is a continuous need for adaption to new architectures. Load balancing… (more)

Subjects/Keywords: Computer Science; Task Parallel model, CPU-GPU, Fault Tolerance, Load Balancing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arafat, M. H. (2014). Runtime Systems for Load Balancing and Fault Tolerance on Distributed Systems. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1408972218

Chicago Manual of Style (16th Edition):

Arafat, Md Humayun. “Runtime Systems for Load Balancing and Fault Tolerance on Distributed Systems.” 2014. Doctoral Dissertation, The Ohio State University. Accessed October 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1408972218.

MLA Handbook (7th Edition):

Arafat, Md Humayun. “Runtime Systems for Load Balancing and Fault Tolerance on Distributed Systems.” 2014. Web. 22 Oct 2019.

Vancouver:

Arafat MH. Runtime Systems for Load Balancing and Fault Tolerance on Distributed Systems. [Internet] [Doctoral dissertation]. The Ohio State University; 2014. [cited 2019 Oct 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1408972218.

Council of Science Editors:

Arafat MH. Runtime Systems for Load Balancing and Fault Tolerance on Distributed Systems. [Doctoral Dissertation]. The Ohio State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1408972218


The Ohio State University

12. Shi, Bobo. Implementation and Performance Analysis of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor and NVIDIA GPU Accelerator.

Degree: MS, Computer Science and Engineering, 2016, The Ohio State University

 CCSD(T), part of coupled cluster (CC) method, is one of the most accurate methods applicable to reasonably large molecules in computational chemistry field. The ability… (more)

Subjects/Keywords: Computer Science; CCSD-T; Xeon Phi Coprocessor; CUDA; GPU; tensor contraction

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APA (6th Edition):

Shi, B. (2016). Implementation and Performance Analysis of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor and NVIDIA GPU Accelerator. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1462793739

Chicago Manual of Style (16th Edition):

Shi, Bobo. “Implementation and Performance Analysis of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor and NVIDIA GPU Accelerator.” 2016. Masters Thesis, The Ohio State University. Accessed October 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1462793739.

MLA Handbook (7th Edition):

Shi, Bobo. “Implementation and Performance Analysis of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor and NVIDIA GPU Accelerator.” 2016. Web. 22 Oct 2019.

Vancouver:

Shi B. Implementation and Performance Analysis of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor and NVIDIA GPU Accelerator. [Internet] [Masters thesis]. The Ohio State University; 2016. [cited 2019 Oct 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1462793739.

Council of Science Editors:

Shi B. Implementation and Performance Analysis of Many-body Quantum Chemical Methods on the Intel Xeon Phi Coprocessor and NVIDIA GPU Accelerator. [Masters Thesis]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1462793739


NSYSU

13. Chen, Chun-Cheng. GPU Acceleration of 3D MRSI using CUDA.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 Using Graphic Processor Unit (GPU) to process the parallel operation via Compute Unified Device Architecture (CUDA) is a new technology in recent years. In the… (more)

Subjects/Keywords: Fourier transform; GPU; Magnetic Resonance Spectroscopy; CUDA; Magnetic Resonance Imaging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, C. (2010). GPU Acceleration of 3D MRSI using CUDA. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804110-144829

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chun-Cheng. “GPU Acceleration of 3D MRSI using CUDA.” 2010. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804110-144829.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chun-Cheng. “GPU Acceleration of 3D MRSI using CUDA.” 2010. Web. 22 Oct 2019.

Vancouver:

Chen C. GPU Acceleration of 3D MRSI using CUDA. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804110-144829.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. GPU Acceleration of 3D MRSI using CUDA. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804110-144829

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Hsu, Chao-yi. Design and implementation of a multi-thread unified SIMD graphics processor.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 This thesis presents a low-cost design and implementation of single-core multi-thread unified graphic processor unit (GPU) targeted for embedded graphics applications. The proposed GPU has… (more)

Subjects/Keywords: Multi-threading; Unified GPU; Thread control; Fill unit; Multi-texture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, C. (2013). Design and implementation of a multi-thread unified SIMD graphics processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chao-yi. “Design and implementation of a multi-thread unified SIMD graphics processor.” 2013. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chao-yi. “Design and implementation of a multi-thread unified SIMD graphics processor.” 2013. Web. 22 Oct 2019.

Vancouver:

Hsu C. Design and implementation of a multi-thread unified SIMD graphics processor. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Design and implementation of a multi-thread unified SIMD graphics processor. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Tang, En-shou. Design exploration of multi-core GPU architecture.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the rapid increase of graphics applications in mobile devices, how to develop an efficient embedded graphics processor unit (GPU) has become a very important… (more)

Subjects/Keywords: GPU; simulation platform; thread scheduling; back-face culling; clipping

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APA (6th Edition):

Tang, E. (2013). Design exploration of multi-core GPU architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tang, En-shou. “Design exploration of multi-core GPU architecture.” 2013. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tang, En-shou. “Design exploration of multi-core GPU architecture.” 2013. Web. 22 Oct 2019.

Vancouver:

Tang E. Design exploration of multi-core GPU architecture. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tang E. Design exploration of multi-core GPU architecture. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. yang, Ho-chun. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing demand of embedded graphic processing unit (GPU), how to develop an efficient GPU has become more and more important. This thesis proposed… (more)

Subjects/Keywords: Unified GPU; Multithreading; Branch divergence; Multi-core; SIMT

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APA (6th Edition):

yang, H. (2014). Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Web. 22 Oct 2019.

Vancouver:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Tsao, Kai-hsiang. Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Low-Power High-Speed graphics processing unit (GPU) is one of the key hardware components in modern mobile devices such as smart phones. In this thesis, we… (more)

Subjects/Keywords: OpenGL; Graphics; SIMD; Processing; Hazard; Architecture; Forwarding; Low Power; GPU

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APA (6th Edition):

Tsao, K. (2014). Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsao, Kai-hsiang. “Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor.” 2014. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsao, Kai-hsiang. “Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor.” 2014. Web. 22 Oct 2019.

Vancouver:

Tsao K. Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsao K. Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Hsu, Chien-te. Design of parallel computing processor based on OpenCL architecture.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In addition to pursuing more shader cores for better rendering performance, another important trend in the evolution of modern graphic processing units (GPU) is to… (more)

Subjects/Keywords: Scalar Processor; Multi-core; GPU; General Computing; OpenCL

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APA (6th Edition):

Hsu, C. (2015). Design of parallel computing processor based on OpenCL architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Web. 22 Oct 2019.

Vancouver:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Chang, Sheng-Chang. A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 This thesis looks at how the GPUâs processing of objects can be simplified (from the programmerâs point of view) and improved (from the run-time point… (more)

Subjects/Keywords: GPU; Occlusion; Object; Subobjects; Hulls; Software and Hardware Modification

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APA (6th Edition):

Chang, S. (2012). A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Sheng-Chang. “A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects.” 2012. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Sheng-Chang. “A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects.” 2012. Web. 22 Oct 2019.

Vancouver:

Chang S. A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects. [Internet] [Thesis]. NSYSU; 2012. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang S. A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

20. Ashari, Arash. Sparse Matrix-Vector Multiplication on GPU.

Degree: PhD, Computer Science and Engineering, 2014, The Ohio State University

 Sparse Matrix-Vector multiplication (SpMV) is one of the key operations in linear algebra. Overcoming thread divergence, load imbalance and un-coalesced and indirect memory access due… (more)

Subjects/Keywords: Computer Engineering; Computer Science; GPU; CUDA; Sparse; SpMV; BRC; ACSR

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APA (6th Edition):

Ashari, A. (2014). Sparse Matrix-Vector Multiplication on GPU. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1417770100

Chicago Manual of Style (16th Edition):

Ashari, Arash. “Sparse Matrix-Vector Multiplication on GPU.” 2014. Doctoral Dissertation, The Ohio State University. Accessed October 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1417770100.

MLA Handbook (7th Edition):

Ashari, Arash. “Sparse Matrix-Vector Multiplication on GPU.” 2014. Web. 22 Oct 2019.

Vancouver:

Ashari A. Sparse Matrix-Vector Multiplication on GPU. [Internet] [Doctoral dissertation]. The Ohio State University; 2014. [cited 2019 Oct 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1417770100.

Council of Science Editors:

Ashari A. Sparse Matrix-Vector Multiplication on GPU. [Doctoral Dissertation]. The Ohio State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1417770100


Penn State University

21. Kesten, Tuba. A FRAMEWORK FOR ANALYZING APPLICATION INTERFERENCE ON GPUS.

Degree: MS, Computer Science and Engineering, 2014, Penn State University

 Graphical Processor Units (GPUs) have a widespread usage in diverse areas such as manufacturing, research, health, life sciences, engineering etc. to accelerate general-purpose computation. To… (more)

Subjects/Keywords: GPU; multiple application; concurrent execution; CUDA; Hyper-Q; NVIDIA; Kepler

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APA (6th Edition):

Kesten, T. (2014). A FRAMEWORK FOR ANALYZING APPLICATION INTERFERENCE ON GPUS. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/23673

Chicago Manual of Style (16th Edition):

Kesten, Tuba. “A FRAMEWORK FOR ANALYZING APPLICATION INTERFERENCE ON GPUS.” 2014. Masters Thesis, Penn State University. Accessed October 22, 2019. https://etda.libraries.psu.edu/catalog/23673.

MLA Handbook (7th Edition):

Kesten, Tuba. “A FRAMEWORK FOR ANALYZING APPLICATION INTERFERENCE ON GPUS.” 2014. Web. 22 Oct 2019.

Vancouver:

Kesten T. A FRAMEWORK FOR ANALYZING APPLICATION INTERFERENCE ON GPUS. [Internet] [Masters thesis]. Penn State University; 2014. [cited 2019 Oct 22]. Available from: https://etda.libraries.psu.edu/catalog/23673.

Council of Science Editors:

Kesten T. A FRAMEWORK FOR ANALYZING APPLICATION INTERFERENCE ON GPUS. [Masters Thesis]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/23673


NSYSU

22. Yang, Yi-Hsun. Accelerating MRSI using Compressed Sensing: A retrospective study.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 MRSI can be used to obtained metabolic information in large area of human brain in vivo. By means of this technique, medical doctors can resolve… (more)

Subjects/Keywords: Magnetic Resonance Spectroscopic Imaging; GPU; Parallel Computing; Compressed Sensing

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APA (6th Edition):

Yang, Y. (2018). Accelerating MRSI using Compressed Sensing: A retrospective study. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0602118-150703

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Yi-Hsun. “Accelerating MRSI using Compressed Sensing: A retrospective study.” 2018. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0602118-150703.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Yi-Hsun. “Accelerating MRSI using Compressed Sensing: A retrospective study.” 2018. Web. 22 Oct 2019.

Vancouver:

Yang Y. Accelerating MRSI using Compressed Sensing: A retrospective study. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0602118-150703.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang Y. Accelerating MRSI using Compressed Sensing: A retrospective study. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0602118-150703

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

23. Thomas, Renji George George. Architectural Solutions For Mitigating Voltage Noise in GPUs.

Degree: PhD, Computer Science and Engineering, 2015, The Ohio State University

 Power efficiency, over the last several years, has become a first class design constraint.New architectures that make use of Single Instruction Multiple Data philosophy are… (more)

Subjects/Keywords: Computer Engineering; Computer Science; GPU, Voltage Noise, Computer Architecture

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APA (6th Edition):

Thomas, R. G. G. (2015). Architectural Solutions For Mitigating Voltage Noise in GPUs. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1449251893

Chicago Manual of Style (16th Edition):

Thomas, Renji George George. “Architectural Solutions For Mitigating Voltage Noise in GPUs.” 2015. Doctoral Dissertation, The Ohio State University. Accessed October 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1449251893.

MLA Handbook (7th Edition):

Thomas, Renji George George. “Architectural Solutions For Mitigating Voltage Noise in GPUs.” 2015. Web. 22 Oct 2019.

Vancouver:

Thomas RGG. Architectural Solutions For Mitigating Voltage Noise in GPUs. [Internet] [Doctoral dissertation]. The Ohio State University; 2015. [cited 2019 Oct 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1449251893.

Council of Science Editors:

Thomas RGG. Architectural Solutions For Mitigating Voltage Noise in GPUs. [Doctoral Dissertation]. The Ohio State University; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1449251893


University of Notre Dame

24. Kai Xiao. GPU Based Acceleration Techniques: Algorithms, Implementations, and Applications</h1>.

Degree: PhD, Computer Science and Engineering, 2016, University of Notre Dame

  Shared memory many-core processors such as GPUs have been extensively used in accelerating computation-intensive algorithms and applications. When porting existing algorithms from sequential or… (more)

Subjects/Keywords: GPU; computer graphics; parallel computing; data structure; radiation dose calculation

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APA (6th Edition):

Xiao, K. (2016). GPU Based Acceleration Techniques: Algorithms, Implementations, and Applications</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/4m90dv15x27

Chicago Manual of Style (16th Edition):

Xiao, Kai. “GPU Based Acceleration Techniques: Algorithms, Implementations, and Applications</h1>.” 2016. Doctoral Dissertation, University of Notre Dame. Accessed October 22, 2019. https://curate.nd.edu/show/4m90dv15x27.

MLA Handbook (7th Edition):

Xiao, Kai. “GPU Based Acceleration Techniques: Algorithms, Implementations, and Applications</h1>.” 2016. Web. 22 Oct 2019.

Vancouver:

Xiao K. GPU Based Acceleration Techniques: Algorithms, Implementations, and Applications</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2016. [cited 2019 Oct 22]. Available from: https://curate.nd.edu/show/4m90dv15x27.

Council of Science Editors:

Xiao K. GPU Based Acceleration Techniques: Algorithms, Implementations, and Applications</h1>. [Doctoral Dissertation]. University of Notre Dame; 2016. Available from: https://curate.nd.edu/show/4m90dv15x27


University of Notre Dame

25. Arun Francis Rodrigues. Programming Future Architectures: Dusty Decks, Memory Walls, and the Speed of Light</h1>.

Degree: PhD, Computer Science and Engineering, 2006, University of Notre Dame

  Due to advances in CMOS fabrication technology, high performance computing capabilities have continually grown. More capable hardware has allowed a range of complex scientific… (more)

Subjects/Keywords: programming model

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APA (6th Edition):

Rodrigues, A. F. (2006). Programming Future Architectures: Dusty Decks, Memory Walls, and the Speed of Light</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/1r66j100s2s

Chicago Manual of Style (16th Edition):

Rodrigues, Arun Francis. “Programming Future Architectures: Dusty Decks, Memory Walls, and the Speed of Light</h1>.” 2006. Doctoral Dissertation, University of Notre Dame. Accessed October 22, 2019. https://curate.nd.edu/show/1r66j100s2s.

MLA Handbook (7th Edition):

Rodrigues, Arun Francis. “Programming Future Architectures: Dusty Decks, Memory Walls, and the Speed of Light</h1>.” 2006. Web. 22 Oct 2019.

Vancouver:

Rodrigues AF. Programming Future Architectures: Dusty Decks, Memory Walls, and the Speed of Light</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2006. [cited 2019 Oct 22]. Available from: https://curate.nd.edu/show/1r66j100s2s.

Council of Science Editors:

Rodrigues AF. Programming Future Architectures: Dusty Decks, Memory Walls, and the Speed of Light</h1>. [Doctoral Dissertation]. University of Notre Dame; 2006. Available from: https://curate.nd.edu/show/1r66j100s2s

26. Weng, Hui-Ze. Performance Analysis of Graph Algorithms using Graphics Processing Units.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 The GPU significantly improves the computing power by increasing the number of cores in recent years. The design principle of GPU focuses on the parallism… (more)

Subjects/Keywords: GPU; Parallel computing; Multi-Core

…國立中山大學資訊工程學系 碩士論文 GPU 應用於圖演算法之計算效益分析 Performance Analysis of Graph Algorithms using… …稱(中) :GPU 應用於圖演算法之計算效益分析 論文名稱(英) :Performance Analysis of Graph Algorithms using Graphics… …英)名:Hui-Ze 指導教授(中)姓名:官大智 指導教授(英)姓名:D.J. Guan 關鍵字(中) :平行計算 關鍵字(中) :GPU 關鍵字(中) :多 心 關鍵字(英… …Parallel computing 關鍵字(英) :GPU 關鍵字(英) :Multi-Core 謝詞 轉眼消逝的兩年生涯, 回想起著實令人感觸良多, 過程中雖然充滿著許多困難 以及不適… …Computer Science & Engineering National Sun Yat-sen University 摘要 近年來, GPU 透過增 心的方式, 使得計算能力大幅提… 

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APA (6th Edition):

Weng, H. (2010). Performance Analysis of Graph Algorithms using Graphics Processing Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-135238

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Weng, Hui-Ze. “Performance Analysis of Graph Algorithms using Graphics Processing Units.” 2010. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-135238.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Weng, Hui-Ze. “Performance Analysis of Graph Algorithms using Graphics Processing Units.” 2010. Web. 22 Oct 2019.

Vancouver:

Weng H. Performance Analysis of Graph Algorithms using Graphics Processing Units. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-135238.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weng H. Performance Analysis of Graph Algorithms using Graphics Processing Units. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-135238

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Yeh, Chia-Yu. Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 Graphics processing unit (GPU) designs usually adopts various computer architecture techniques to boost the computation speed, including single-instruction multiple data (SIMD), very-long-instruction word (VLIW), multi-threading,… (more)

Subjects/Keywords: multi-threading; graphics processing unit (GPU); vertex shader; SIMD; matrix-vector multiplication; OpenGL ES 2.0

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeh, C. (2011). Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Chia-Yu. “Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics.” 2011. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Chia-Yu. “Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics.” 2011. Web. 22 Oct 2019.

Vancouver:

Yeh C. Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh C. Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

28. Zhao, Jishen. Rethinking the memory hierarchy design with nonvolatile memory technologies.

Degree: PhD, Computer Science and Engineering, 2014, Penn State University

 The memory hierarchy, including processor caches and the main memory, is an important component of various computer systems. The memory hierarchy is becoming a fundamental… (more)

Subjects/Keywords: Memory hierarchy; Nonvolatile memory; Persistence; Memory/storage stack; Energy efficiency; Graphics memory; CMP; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, J. (2014). Rethinking the memory hierarchy design with nonvolatile memory technologies. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/21345

Chicago Manual of Style (16th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Doctoral Dissertation, Penn State University. Accessed October 22, 2019. https://etda.libraries.psu.edu/catalog/21345.

MLA Handbook (7th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Web. 22 Oct 2019.

Vancouver:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2019 Oct 22]. Available from: https://etda.libraries.psu.edu/catalog/21345.

Council of Science Editors:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/21345


Penn State University

29. Chandrashekhar, Anusha. Acceleration of monocular depth extraction for images.

Degree: MS, Computer Science and Engineering, 2014, Penn State University

 This thesis evaluates and profiles a monocular depth estimation algorithm in which depth maps are generated from a single image using a non-parametric depth transfer… (more)

Subjects/Keywords: Monocular depth extraction; GPU; CUDA; Hardware acceleration; non-parametric depth; fast depth estimator; computer vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandrashekhar, A. (2014). Acceleration of monocular depth extraction for images. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/23442

Chicago Manual of Style (16th Edition):

Chandrashekhar, Anusha. “Acceleration of monocular depth extraction for images.” 2014. Masters Thesis, Penn State University. Accessed October 22, 2019. https://etda.libraries.psu.edu/catalog/23442.

MLA Handbook (7th Edition):

Chandrashekhar, Anusha. “Acceleration of monocular depth extraction for images.” 2014. Web. 22 Oct 2019.

Vancouver:

Chandrashekhar A. Acceleration of monocular depth extraction for images. [Internet] [Masters thesis]. Penn State University; 2014. [cited 2019 Oct 22]. Available from: https://etda.libraries.psu.edu/catalog/23442.

Council of Science Editors:

Chandrashekhar A. Acceleration of monocular depth extraction for images. [Masters Thesis]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/23442


University of California – San Diego

30. Lotfi, Atieh. Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators.

Degree: Computer Science and Engineering, 2018, University of California – San Diego

 Faced with the exponential growth in computing requirements, programmable hardware accelerators, such as GPUs and FPGAs, are becoming increasingly popular in high performance computing systems.… (more)

Subjects/Keywords: Computer science; Computer engineering; Error mitigation; FPGA; GPU; Hardware resource optimization; Programmable hardware accelerator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lotfi, A. (2018). Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/1ww3k3b8

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lotfi, Atieh. “Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators.” 2018. Thesis, University of California – San Diego. Accessed October 22, 2019. http://www.escholarship.org/uc/item/1ww3k3b8.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lotfi, Atieh. “Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators.” 2018. Web. 22 Oct 2019.

Vancouver:

Lotfi A. Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. [Internet] [Thesis]. University of California – San Diego; 2018. [cited 2019 Oct 22]. Available from: http://www.escholarship.org/uc/item/1ww3k3b8.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lotfi A. Fault-susceptibility Mitigation and Efficient Use of Resources in Programmable Hardware Accelerators. [Thesis]. University of California – San Diego; 2018. Available from: http://www.escholarship.org/uc/item/1ww3k3b8

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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