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You searched for subject:( Xilinx Floating Point Operator). Showing records 1 – 30 of 7001 total matches.

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Brno University of Technology

1. Štrympl, Martin. Výpočet vlastních čísel a vlastních vektorů hermitovské matice .

Degree: 2016, Brno University of Technology

 Tato práce se zabývá výpočtem vlastních čísel a vlastních vektorů hermitovské pozitivně-semidefinitní komplexní čtvercové matice řádu 4. Cílem je implementace výpočtu v jazyce VHDL pro… (more)

Subjects/Keywords: matice; vlastní čísla; vlastní vektory; symetrická matice; hermitovská matice; QR rozklad; třídiagonální matice; analýza algoritmů; VHDL; Xilinx Zynq-7000; Xilinx® Floating-Point Operator; matrix; eigenvalues; eigenvectors; symmetrix matrix; Hermitian matrix; QR decomposition; tridiagonal matrix; algorithm analyze; VHDL; Xilinx Zynq-7000; Xilinx® Floating-Point Operator

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APA (6th Edition):

Štrympl, M. (2016). Výpočet vlastních čísel a vlastních vektorů hermitovské matice . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/59861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Štrympl, Martin. “Výpočet vlastních čísel a vlastních vektorů hermitovské matice .” 2016. Thesis, Brno University of Technology. Accessed July 19, 2019. http://hdl.handle.net/11012/59861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Štrympl, Martin. “Výpočet vlastních čísel a vlastních vektorů hermitovské matice .” 2016. Web. 19 Jul 2019.

Vancouver:

Štrympl M. Výpočet vlastních čísel a vlastních vektorů hermitovské matice . [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/11012/59861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Štrympl M. Výpočet vlastních čísel a vlastních vektorů hermitovské matice . [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/59861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Lee, Hsin-mau. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis.… (more)

Subjects/Keywords: Floating-point; CORDIC

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APA (6th Edition):

Lee, H. (2008). Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Thesis, NSYSU. Accessed July 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Web. 19 Jul 2019.

Vancouver:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Jul 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Dagbagi, Mohamed. Simulation temps-réel embarquée de systèmes électriques au moyen de FPGA : FPGA-based Embedded real time simulation of electrical systems.

Degree: Docteur es, Génie électrique et électronique - Cergy, 2015, Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie)

 L'objectif de ce travail de thèse est de développer une bibliothèque de modules IPs (Intellectual Properties) de simulateurs temps réel embarqués qui simulent différents éléments… (more)

Subjects/Keywords: Fpga; Simulation temps réel embarquée; Systèmes électriques; Codage virgule flottante; Opérateur delta; Codage virgule fixe; Fpga; Embedded real-Time simulation; Electrical systems; Floating-Point quantization; Delta operator; Fixed-Point quantization

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APA (6th Edition):

Dagbagi, M. (2015). Simulation temps-réel embarquée de systèmes électriques au moyen de FPGA : FPGA-based Embedded real time simulation of electrical systems. (Doctoral Dissertation). Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie). Retrieved from http://www.theses.fr/2015CERG0808

Chicago Manual of Style (16th Edition):

Dagbagi, Mohamed. “Simulation temps-réel embarquée de systèmes électriques au moyen de FPGA : FPGA-based Embedded real time simulation of electrical systems.” 2015. Doctoral Dissertation, Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie). Accessed July 19, 2019. http://www.theses.fr/2015CERG0808.

MLA Handbook (7th Edition):

Dagbagi, Mohamed. “Simulation temps-réel embarquée de systèmes électriques au moyen de FPGA : FPGA-based Embedded real time simulation of electrical systems.” 2015. Web. 19 Jul 2019.

Vancouver:

Dagbagi M. Simulation temps-réel embarquée de systèmes électriques au moyen de FPGA : FPGA-based Embedded real time simulation of electrical systems. [Internet] [Doctoral dissertation]. Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie); 2015. [cited 2019 Jul 19]. Available from: http://www.theses.fr/2015CERG0808.

Council of Science Editors:

Dagbagi M. Simulation temps-réel embarquée de systèmes électriques au moyen de FPGA : FPGA-based Embedded real time simulation of electrical systems. [Doctoral Dissertation]. Cergy-Pontoise; École nationale d'ingénieurs de Tunis (Tunisie); 2015. Available from: http://www.theses.fr/2015CERG0808


University of Georgia

4. Yardi, Shrirang Madhav. A reconfigurable multi-processor custom integrated circuit for floating point intensive algorithms.

Degree: MS, Computer Science, 2003, University of Georgia

 Hardware support for floating-point intensive applications like multimedia and graphics processing is rapidly gaining importance. The use of add-on cards for graphics processing, image rendering… (more)

Subjects/Keywords: floating point intensive

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APA (6th Edition):

Yardi, S. M. (2003). A reconfigurable multi-processor custom integrated circuit for floating point intensive algorithms. (Masters Thesis). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/yardi_shrirang_m_200308_ms

Chicago Manual of Style (16th Edition):

Yardi, Shrirang Madhav. “A reconfigurable multi-processor custom integrated circuit for floating point intensive algorithms.” 2003. Masters Thesis, University of Georgia. Accessed July 19, 2019. http://purl.galileo.usg.edu/uga_etd/yardi_shrirang_m_200308_ms.

MLA Handbook (7th Edition):

Yardi, Shrirang Madhav. “A reconfigurable multi-processor custom integrated circuit for floating point intensive algorithms.” 2003. Web. 19 Jul 2019.

Vancouver:

Yardi SM. A reconfigurable multi-processor custom integrated circuit for floating point intensive algorithms. [Internet] [Masters thesis]. University of Georgia; 2003. [cited 2019 Jul 19]. Available from: http://purl.galileo.usg.edu/uga_etd/yardi_shrirang_m_200308_ms.

Council of Science Editors:

Yardi SM. A reconfigurable multi-processor custom integrated circuit for floating point intensive algorithms. [Masters Thesis]. University of Georgia; 2003. Available from: http://purl.galileo.usg.edu/uga_etd/yardi_shrirang_m_200308_ms


Oregon State University

5. Rajanala, Arunkumar V. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology.

Degree: MS, Electrical and Computer Engineering, 1988, Oregon State University

 Typically, a Floating Point processor will be attached to a general-purpose digital computer to extend and enhance its numeric processing capabilities. In this thesis a… (more)

Subjects/Keywords: Floating-point arithmetic

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APA (6th Edition):

Rajanala, A. V. (1988). IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39940

Chicago Manual of Style (16th Edition):

Rajanala, Arunkumar V. “IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology.” 1988. Masters Thesis, Oregon State University. Accessed July 19, 2019. http://hdl.handle.net/1957/39940.

MLA Handbook (7th Edition):

Rajanala, Arunkumar V. “IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology.” 1988. Web. 19 Jul 2019.

Vancouver:

Rajanala AV. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. [Internet] [Masters thesis]. Oregon State University; 1988. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/1957/39940.

Council of Science Editors:

Rajanala AV. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. [Masters Thesis]. Oregon State University; 1988. Available from: http://hdl.handle.net/1957/39940


Oregon State University

6. Lou, Junhui. Numerical Simulation, Laboratory and Field Experiments, Analysis and Design of Wave Energy Converter and Mooring System.

Degree: PhD, Civil Engineering, 2017, Oregon State University

 This dissertation studies the coupled fluid-structure interaction (FSI) of a wave energy converter (WEC) and evaluates the design of a WEC mooring system. The research… (more)

Subjects/Keywords: floating point absorber; Ocean wave power

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APA (6th Edition):

Lou, J. (2017). Numerical Simulation, Laboratory and Field Experiments, Analysis and Design of Wave Energy Converter and Mooring System. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/60625

Chicago Manual of Style (16th Edition):

Lou, Junhui. “Numerical Simulation, Laboratory and Field Experiments, Analysis and Design of Wave Energy Converter and Mooring System.” 2017. Doctoral Dissertation, Oregon State University. Accessed July 19, 2019. http://hdl.handle.net/1957/60625.

MLA Handbook (7th Edition):

Lou, Junhui. “Numerical Simulation, Laboratory and Field Experiments, Analysis and Design of Wave Energy Converter and Mooring System.” 2017. Web. 19 Jul 2019.

Vancouver:

Lou J. Numerical Simulation, Laboratory and Field Experiments, Analysis and Design of Wave Energy Converter and Mooring System. [Internet] [Doctoral dissertation]. Oregon State University; 2017. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/1957/60625.

Council of Science Editors:

Lou J. Numerical Simulation, Laboratory and Field Experiments, Analysis and Design of Wave Energy Converter and Mooring System. [Doctoral Dissertation]. Oregon State University; 2017. Available from: http://hdl.handle.net/1957/60625


University of Newcastle

7. Fitzpatrick, Chris. Firmwares for high-speed signal processing applications.

Degree: MPhil, 2016, University of Newcastle

Masters Research - Master of Philosophy (MPhil)

Matrix-vector multiplication is widely used in science and engineering. With the constant increase in data throughput rates, computing… (more)

Subjects/Keywords: VHDL; FPGA; matrix; vector; floating point; MAC

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APA (6th Edition):

Fitzpatrick, C. (2016). Firmwares for high-speed signal processing applications. (Masters Thesis). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/1312018

Chicago Manual of Style (16th Edition):

Fitzpatrick, Chris. “Firmwares for high-speed signal processing applications.” 2016. Masters Thesis, University of Newcastle. Accessed July 19, 2019. http://hdl.handle.net/1959.13/1312018.

MLA Handbook (7th Edition):

Fitzpatrick, Chris. “Firmwares for high-speed signal processing applications.” 2016. Web. 19 Jul 2019.

Vancouver:

Fitzpatrick C. Firmwares for high-speed signal processing applications. [Internet] [Masters thesis]. University of Newcastle; 2016. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/1959.13/1312018.

Council of Science Editors:

Fitzpatrick C. Firmwares for high-speed signal processing applications. [Masters Thesis]. University of Newcastle; 2016. Available from: http://hdl.handle.net/1959.13/1312018


NSYSU

8. Sun, Wei-Cheng. Transmission Modeling with Simulink and FPGA implementation of 3072-point FFT for the Homeplug AV system.

Degree: Master, Communications Engineering, 2011, NSYSU

 The rapid growth of communication technology with the success of internet, has brought huge profits and great convenience to our daily life. Computer networks can… (more)

Subjects/Keywords: MATLAB/Simulink; Homeplug AV; Xilinx System Generator; 3072-point FFT processor

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APA (6th Edition):

Sun, W. (2011). Transmission Modeling with Simulink and FPGA implementation of 3072-point FFT for the Homeplug AV system. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0720111-191656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Wei-Cheng. “Transmission Modeling with Simulink and FPGA implementation of 3072-point FFT for the Homeplug AV system.” 2011. Thesis, NSYSU. Accessed July 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0720111-191656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Wei-Cheng. “Transmission Modeling with Simulink and FPGA implementation of 3072-point FFT for the Homeplug AV system.” 2011. Web. 19 Jul 2019.

Vancouver:

Sun W. Transmission Modeling with Simulink and FPGA implementation of 3072-point FFT for the Homeplug AV system. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Jul 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0720111-191656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun W. Transmission Modeling with Simulink and FPGA implementation of 3072-point FFT for the Homeplug AV system. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0720111-191656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

9. Pimenta Pereira, Karl Savio. Characterization of FPGA-based High Performance Computers.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As CPU clock frequencies plateau and the doubling of CPU cores per processor exacerbate the memory wall, hybrid core computing, utilizing CPUs augmented with FPGAs… (more)

Subjects/Keywords: FFT; molecular dynamics; integer-point; floating-point; GPU; HPC; FPGA

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APA (6th Edition):

Pimenta Pereira, K. S. (2011). Characterization of FPGA-based High Performance Computers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34483

Chicago Manual of Style (16th Edition):

Pimenta Pereira, Karl Savio. “Characterization of FPGA-based High Performance Computers.” 2011. Masters Thesis, Virginia Tech. Accessed July 19, 2019. http://hdl.handle.net/10919/34483.

MLA Handbook (7th Edition):

Pimenta Pereira, Karl Savio. “Characterization of FPGA-based High Performance Computers.” 2011. Web. 19 Jul 2019.

Vancouver:

Pimenta Pereira KS. Characterization of FPGA-based High Performance Computers. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/10919/34483.

Council of Science Editors:

Pimenta Pereira KS. Characterization of FPGA-based High Performance Computers. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34483

10. Jourdan, Jingyan. Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection : Arithmétique à virgule flottante spécifique pour processeurs entiers : algorithmes, implémentation et sélection.

Degree: Docteur es, Informatique, 2012, Lyon, École normale supérieure

Les applications multimédia se composent généralement de blocs numériques exhibant des schémas de calcul flottant réguliers. Sur les processeurs sans support architectural pour l'arithmétique flottante,… (more)

Subjects/Keywords: Arithmétique virgule flottante; Opérateur dédié; Processeur embarqué entier; Architecture VLIW; Optimisation du compilateur; Sélection du code par le compilateur; IEEE floating-point arithmetic; Custom operator; Embedded integer processor; VLIW architecture; Compiler optimization; Compiler code selection

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APA (6th Edition):

Jourdan, J. (2012). Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection : Arithmétique à virgule flottante spécifique pour processeurs entiers : algorithmes, implémentation et sélection. (Doctoral Dissertation). Lyon, École normale supérieure. Retrieved from http://www.theses.fr/2012ENSL0762

Chicago Manual of Style (16th Edition):

Jourdan, Jingyan. “Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection : Arithmétique à virgule flottante spécifique pour processeurs entiers : algorithmes, implémentation et sélection.” 2012. Doctoral Dissertation, Lyon, École normale supérieure. Accessed July 19, 2019. http://www.theses.fr/2012ENSL0762.

MLA Handbook (7th Edition):

Jourdan, Jingyan. “Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection : Arithmétique à virgule flottante spécifique pour processeurs entiers : algorithmes, implémentation et sélection.” 2012. Web. 19 Jul 2019.

Vancouver:

Jourdan J. Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection : Arithmétique à virgule flottante spécifique pour processeurs entiers : algorithmes, implémentation et sélection. [Internet] [Doctoral dissertation]. Lyon, École normale supérieure; 2012. [cited 2019 Jul 19]. Available from: http://www.theses.fr/2012ENSL0762.

Council of Science Editors:

Jourdan J. Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection : Arithmétique à virgule flottante spécifique pour processeurs entiers : algorithmes, implémentation et sélection. [Doctoral Dissertation]. Lyon, École normale supérieure; 2012. Available from: http://www.theses.fr/2012ENSL0762


University of Kentucky

11. Kaveti, Akil. HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT.

Degree: 2008, University of Kentucky

 Processors used in lower-end scientific applications like graphic cards and video game consoles have IEEE single precision floating-point hardware [23]. Double precision offers higher precision… (more)

Subjects/Keywords: Native-pair floating-point unit residual VHDL; Electrical and Computer Engineering

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APA (6th Edition):

Kaveti, A. (2008). HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/538

Chicago Manual of Style (16th Edition):

Kaveti, Akil. “HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT.” 2008. Masters Thesis, University of Kentucky. Accessed July 19, 2019. http://uknowledge.uky.edu/gradschool_theses/538.

MLA Handbook (7th Edition):

Kaveti, Akil. “HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT.” 2008. Web. 19 Jul 2019.

Vancouver:

Kaveti A. HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT. [Internet] [Masters thesis]. University of Kentucky; 2008. [cited 2019 Jul 19]. Available from: http://uknowledge.uky.edu/gradschool_theses/538.

Council of Science Editors:

Kaveti A. HDL IMPLEMENTATION AND ANALYSIS OF A RESIDUAL REGISTER FOR A FLOATING-POINT ARITHMETIC UNIT. [Masters Thesis]. University of Kentucky; 2008. Available from: http://uknowledge.uky.edu/gradschool_theses/538


University of Sydney

12. Frechtling, Michael Kenneth. Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems .

Degree: 2015, University of Sydney

 Computer arithmetic is one of the more important topics within computer science and engineering. The earliest implementations of computer systems were designed to perform arithmetic… (more)

Subjects/Keywords: Computer Arithmetic; Floating Point Arithmetic; Numeric Analysis; Monte Carlo Arithmetic

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APA (6th Edition):

Frechtling, M. K. (2015). Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems . (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/13928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Frechtling, Michael Kenneth. “Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems .” 2015. Thesis, University of Sydney. Accessed July 19, 2019. http://hdl.handle.net/2123/13928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Frechtling, Michael Kenneth. “Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems .” 2015. Web. 19 Jul 2019.

Vancouver:

Frechtling MK. Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems . [Internet] [Thesis]. University of Sydney; 2015. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/2123/13928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Frechtling MK. Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems . [Thesis]. University of Sydney; 2015. Available from: http://hdl.handle.net/2123/13928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Sydney

13. Wilson, Huon. Computing fast and accurate convolutions .

Degree: 2016, University of Sydney

 The analysis of data often models random components as a sum of in- dependent random variables (RVs). These RVs are often assumed to be lattice-valued,… (more)

Subjects/Keywords: convolution; p-value; numerical analysis; fast Fourier transform; FFT; floating point

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APA (6th Edition):

Wilson, H. (2016). Computing fast and accurate convolutions . (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/15169

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wilson, Huon. “Computing fast and accurate convolutions .” 2016. Thesis, University of Sydney. Accessed July 19, 2019. http://hdl.handle.net/2123/15169.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wilson, Huon. “Computing fast and accurate convolutions .” 2016. Web. 19 Jul 2019.

Vancouver:

Wilson H. Computing fast and accurate convolutions . [Internet] [Thesis]. University of Sydney; 2016. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/2123/15169.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wilson H. Computing fast and accurate convolutions . [Thesis]. University of Sydney; 2016. Available from: http://hdl.handle.net/2123/15169

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

14. Taouil, M. A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product:.

Degree: 2009, Delft University of Technology

 One of the key kernels in scientific applications is the Sparse Matrix Vector Multiplication (SMVM). Profiling OpenFOAM, a sophisticated scientific Computational Fluid Dynamics tool, proved… (more)

Subjects/Keywords: FPGA; Double Precision Floating Point; Sparse Matrix dense Vector Product; OpenFOAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Taouil, M. (2009). A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ce583533-45ea-4237-b18d-fe31272ea1ee

Chicago Manual of Style (16th Edition):

Taouil, M. “A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product:.” 2009. Masters Thesis, Delft University of Technology. Accessed July 19, 2019. http://resolver.tudelft.nl/uuid:ce583533-45ea-4237-b18d-fe31272ea1ee.

MLA Handbook (7th Edition):

Taouil, M. “A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product:.” 2009. Web. 19 Jul 2019.

Vancouver:

Taouil M. A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Jul 19]. Available from: http://resolver.tudelft.nl/uuid:ce583533-45ea-4237-b18d-fe31272ea1ee.

Council of Science Editors:

Taouil M. A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:ce583533-45ea-4237-b18d-fe31272ea1ee


University of California – San Diego

15. Kohlbrenner, David William. Trusted Systems for Uncertain Times.

Degree: Computer Science, 2018, University of California – San Diego

 When software is designed, even with security in mind, assumptions are made about the details of hardware behavior. Unfortunately, the correctness of such assumptions can… (more)

Subjects/Keywords: Computer science; Computer Security; Floating Point; Timing Attacks

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APA (6th Edition):

Kohlbrenner, D. W. (2018). Trusted Systems for Uncertain Times. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/7st3z2ws

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kohlbrenner, David William. “Trusted Systems for Uncertain Times.” 2018. Thesis, University of California – San Diego. Accessed July 19, 2019. http://www.escholarship.org/uc/item/7st3z2ws.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kohlbrenner, David William. “Trusted Systems for Uncertain Times.” 2018. Web. 19 Jul 2019.

Vancouver:

Kohlbrenner DW. Trusted Systems for Uncertain Times. [Internet] [Thesis]. University of California – San Diego; 2018. [cited 2019 Jul 19]. Available from: http://www.escholarship.org/uc/item/7st3z2ws.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kohlbrenner DW. Trusted Systems for Uncertain Times. [Thesis]. University of California – San Diego; 2018. Available from: http://www.escholarship.org/uc/item/7st3z2ws

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kaunas University of Technology

16. Lešinskytė, Vaida. Dvigubo tikslumo slankaus kablelio daugybos realizavimas ir tyrimas.

Degree: Master, Informatics Engineering, 2011, Kaunas University of Technology

Darbe analizuojamos slankaus kablelio daugybos apskaičiavimo problemos. Pirmame darbo skyriuje analizuojamas slankaus kablelio vertimas iš dešimtainės sistemos į dvejetainę sistemą ir atvirkščiai. Tai reikalinga atlikti… (more)

Subjects/Keywords: Slankus kablelis; Dvigubas tikslumas; Daugyba; Floating point; Double precision; Multiplication

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lešinskytė, Vaida. (2011). Dvigubo tikslumo slankaus kablelio daugybos realizavimas ir tyrimas. (Masters Thesis). Kaunas University of Technology. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110902_092912-76295 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Lešinskytė, Vaida. “Dvigubo tikslumo slankaus kablelio daugybos realizavimas ir tyrimas.” 2011. Masters Thesis, Kaunas University of Technology. Accessed July 19, 2019. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110902_092912-76295 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Lešinskytė, Vaida. “Dvigubo tikslumo slankaus kablelio daugybos realizavimas ir tyrimas.” 2011. Web. 19 Jul 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Lešinskytė, Vaida. Dvigubo tikslumo slankaus kablelio daugybos realizavimas ir tyrimas. [Internet] [Masters thesis]. Kaunas University of Technology; 2011. [cited 2019 Jul 19]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110902_092912-76295 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Lešinskytė, Vaida. Dvigubo tikslumo slankaus kablelio daugybos realizavimas ir tyrimas. [Masters Thesis]. Kaunas University of Technology; 2011. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110902_092912-76295 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

17. Englund, Madeleine. Hybrid Floating-point Units in FPGAs.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

Floating point numbers are used in many applications that  would be well suited to a higher parallelism than that offered in a CPU. In … (more)

Subjects/Keywords: FPGA; Floating Point

…Why Higher Radix Floating Point Numbers? . . . . . . . . . . . . 6 1.2 Motivation for… …the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Floating Point Numbers… …11 2.1 Higher Radix Floating Point Numbers . . . . . . . . . . . . . . . . 12 2.2… …Previous Work on Reducing the Complexity of Floating Point Arithmetic… …Floating Point Units . . . . . . . . . . . . . . . . . . . . . . 16 3 The Calculation Steps for… 

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APA (6th Edition):

Englund, M. (2012). Hybrid Floating-point Units in FPGAs. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Englund, Madeleine. “Hybrid Floating-point Units in FPGAs.” 2012. Thesis, Linköping UniversityLinköping University. Accessed July 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Englund, Madeleine. “Hybrid Floating-point Units in FPGAs.” 2012. Web. 19 Jul 2019.

Vancouver:

Englund M. Hybrid Floating-point Units in FPGAs. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2019 Jul 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Englund M. Hybrid Floating-point Units in FPGAs. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Northridge

18. Jayasinghe, Heston. Gravitational Particle Simulator using FPGA.

Degree: MS, Department of Electrical & Computer Engineering, 2018, California State University – Northridge

 This hardware simulator will attempt to improve on the work of Mark Eiding and Brian Curless from Cornell University. Their project simulated particles of different… (more)

Subjects/Keywords: Floating-point; Dissertations, Academic  – CSUN  – Engineering  – Electrical and Computer Engineering.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jayasinghe, H. (2018). Gravitational Particle Simulator using FPGA. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.3/206427

Chicago Manual of Style (16th Edition):

Jayasinghe, Heston. “Gravitational Particle Simulator using FPGA.” 2018. Masters Thesis, California State University – Northridge. Accessed July 19, 2019. http://hdl.handle.net/10211.3/206427.

MLA Handbook (7th Edition):

Jayasinghe, Heston. “Gravitational Particle Simulator using FPGA.” 2018. Web. 19 Jul 2019.

Vancouver:

Jayasinghe H. Gravitational Particle Simulator using FPGA. [Internet] [Masters thesis]. California State University – Northridge; 2018. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/10211.3/206427.

Council of Science Editors:

Jayasinghe H. Gravitational Particle Simulator using FPGA. [Masters Thesis]. California State University – Northridge; 2018. Available from: http://hdl.handle.net/10211.3/206427


University of Southern California

19. Kwon, Taek-Jun. Floating-point unit design using Taylor-series expansion algorithms.

Degree: PhD, Electrical Engineering, 2009, University of Southern California

 Due to the constant advances in VLSI technology and the prevalence of many applications that require floating-point operations, hardware support for floating-point arithmetic is an… (more)

Subjects/Keywords: computer architecture; computer arithmetic; floating-point unit; division; square root

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kwon, T. (2009). Floating-point unit design using Taylor-series expansion algorithms. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/272512/rec/2845

Chicago Manual of Style (16th Edition):

Kwon, Taek-Jun. “Floating-point unit design using Taylor-series expansion algorithms.” 2009. Doctoral Dissertation, University of Southern California. Accessed July 19, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/272512/rec/2845.

MLA Handbook (7th Edition):

Kwon, Taek-Jun. “Floating-point unit design using Taylor-series expansion algorithms.” 2009. Web. 19 Jul 2019.

Vancouver:

Kwon T. Floating-point unit design using Taylor-series expansion algorithms. [Internet] [Doctoral dissertation]. University of Southern California; 2009. [cited 2019 Jul 19]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/272512/rec/2845.

Council of Science Editors:

Kwon T. Floating-point unit design using Taylor-series expansion algorithms. [Doctoral Dissertation]. University of Southern California; 2009. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/272512/rec/2845


Linköping University

20. Ross, Johan. Voice Codec for Floating Point Processor.

Degree: Electrical Engineering, 2008, Linköping University

  As part of an ongoing project at the department of electrical engineering, ISY, at Linköping University, a voice decoder using floating point formats has… (more)

Subjects/Keywords: Voice codec; floating point; GSM decoder; low precision codec; speech coding; TECHNOLOGY; TEKNIKVETENSKAP

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ross, J. (2008). Voice Codec for Floating Point Processor. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15763

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ross, Johan. “Voice Codec for Floating Point Processor.” 2008. Thesis, Linköping University. Accessed July 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15763.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ross, Johan. “Voice Codec for Floating Point Processor.” 2008. Web. 19 Jul 2019.

Vancouver:

Ross J. Voice Codec for Floating Point Processor. [Internet] [Thesis]. Linköping University; 2008. [cited 2019 Jul 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15763.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ross J. Voice Codec for Floating Point Processor. [Thesis]. Linköping University; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15763

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

21. Bainbridge, Christopher James. Digital control networks for virtual creatures.

Degree: 2010, University of Edinburgh

 Robot control systems evolved with genetic algorithms traditionally take the form of floating-point neural network models. This thesis proposes that digital control systems, such as… (more)

Subjects/Keywords: Robot control systems; quantised neural networks; floating-point neural network models; neural network

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bainbridge, C. J. (2010). Digital control networks for virtual creatures. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/4812

Chicago Manual of Style (16th Edition):

Bainbridge, Christopher James. “Digital control networks for virtual creatures.” 2010. Doctoral Dissertation, University of Edinburgh. Accessed July 19, 2019. http://hdl.handle.net/1842/4812.

MLA Handbook (7th Edition):

Bainbridge, Christopher James. “Digital control networks for virtual creatures.” 2010. Web. 19 Jul 2019.

Vancouver:

Bainbridge CJ. Digital control networks for virtual creatures. [Internet] [Doctoral dissertation]. University of Edinburgh; 2010. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/1842/4812.

Council of Science Editors:

Bainbridge CJ. Digital control networks for virtual creatures. [Doctoral Dissertation]. University of Edinburgh; 2010. Available from: http://hdl.handle.net/1842/4812


NSYSU

22. Lin, Bo-ting. Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 A multi-precision function interpolator generator and a multi-precision MAF generator, which is compliant in with the IEEE-754 single precision floating point standard, is proposed in… (more)

Subjects/Keywords: multi-mode floating point multiply-add-fused; low power; generator; multi-precision function interpolator

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APA (6th Edition):

Lin, B. (2014). Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716114-030526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Bo-ting. “Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application.” 2014. Thesis, NSYSU. Accessed July 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716114-030526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Bo-ting. “Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application.” 2014. Web. 19 Jul 2019.

Vancouver:

Lin B. Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716114-030526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin B. Low-power Multi-precision Functional Unit Generator for 3-D Graphics Application. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716114-030526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Yu, Kee-khuan. Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 In digital signal processing and multimedia applications, floating-point(FP) multiplication and addition are the most commonly used operations. In addition, FP multiplication operations are frequently followed… (more)

Subjects/Keywords: iterative multiplication; low power; truncated addition; multi-mode floating point multiply-add-fused

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, K. (2011). Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-105514

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Kee-khuan. “Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications.” 2011. Thesis, NSYSU. Accessed July 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-105514.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Kee-khuan. “Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications.” 2011. Web. 19 Jul 2019.

Vancouver:

Yu K. Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Jul 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-105514.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu K. Multi-Mode Floating-Point Multiply-Add Fused Unit for Low-Power Applications. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-105514

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Hsu, Li-wei. A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents a variable-precision floating-point arithmetic unit based on IEEE-754 single precision floating standard. This arithmetic unit combines special function interpolator and floating-point multiply-add-fused.… (more)

Subjects/Keywords: A Variable-precision floating point multiply-add-fused; low power; A Variable-precision function interpolator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, L. (2015). A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Li-wei. “A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation.” 2015. Thesis, NSYSU. Accessed July 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Li-wei. “A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation.” 2015. Web. 19 Jul 2019.

Vancouver:

Hsu L. A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Jul 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu L. A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Western Australia

25. Thorne, Chris. Origin-centric techniques for optimising scalability and the fidelity of motion, interaction and rendering.

Degree: PhD, 2007, University of Western Australia

 [Truncated abstract] This research addresses endemic problems in the fields of computer graphics and simulation such as jittery motion, spatial scalability, rendering problems such as… (more)

Subjects/Keywords: Computer simulation; Image processing; Floating point; Precision; Spatial jitter; Rendering; 3D graphics; Computation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thorne, C. (2007). Origin-centric techniques for optimising scalability and the fidelity of motion, interaction and rendering. (Doctoral Dissertation). University of Western Australia. Retrieved from http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=10284&local_base=GEN01-INS01

Chicago Manual of Style (16th Edition):

Thorne, Chris. “Origin-centric techniques for optimising scalability and the fidelity of motion, interaction and rendering.” 2007. Doctoral Dissertation, University of Western Australia. Accessed July 19, 2019. http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=10284&local_base=GEN01-INS01.

MLA Handbook (7th Edition):

Thorne, Chris. “Origin-centric techniques for optimising scalability and the fidelity of motion, interaction and rendering.” 2007. Web. 19 Jul 2019.

Vancouver:

Thorne C. Origin-centric techniques for optimising scalability and the fidelity of motion, interaction and rendering. [Internet] [Doctoral dissertation]. University of Western Australia; 2007. [cited 2019 Jul 19]. Available from: http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=10284&local_base=GEN01-INS01.

Council of Science Editors:

Thorne C. Origin-centric techniques for optimising scalability and the fidelity of motion, interaction and rendering. [Doctoral Dissertation]. University of Western Australia; 2007. Available from: http://repository.uwa.edu.au:80/R/?func=dbin-jump-full&object_id=10284&local_base=GEN01-INS01

26. Zitoun, Heytem. Stratégies de recherches dédiées à la résolution de systèmes de contraintes sur les flottants pour la vérification de programmes : Search strategies for solving constraint systems over floats for program verification.

Degree: Docteur es, Informatique, 2018, Côte d'Azur

La vérification des programmes est un enjeu majeur pour les applications critiques comme l'aviation, l'aérospatiale ou les systèmes embarqués. Les approches Bounded model checking (e.g.,… (more)

Subjects/Keywords: Vérification de programmes; Nombres flottants; Stratégies de recherches; Program verification; Floating point number; Search strategies

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APA (6th Edition):

Zitoun, H. (2018). Stratégies de recherches dédiées à la résolution de systèmes de contraintes sur les flottants pour la vérification de programmes : Search strategies for solving constraint systems over floats for program verification. (Doctoral Dissertation). Côte d'Azur. Retrieved from http://www.theses.fr/2018AZUR4089

Chicago Manual of Style (16th Edition):

Zitoun, Heytem. “Stratégies de recherches dédiées à la résolution de systèmes de contraintes sur les flottants pour la vérification de programmes : Search strategies for solving constraint systems over floats for program verification.” 2018. Doctoral Dissertation, Côte d'Azur. Accessed July 19, 2019. http://www.theses.fr/2018AZUR4089.

MLA Handbook (7th Edition):

Zitoun, Heytem. “Stratégies de recherches dédiées à la résolution de systèmes de contraintes sur les flottants pour la vérification de programmes : Search strategies for solving constraint systems over floats for program verification.” 2018. Web. 19 Jul 2019.

Vancouver:

Zitoun H. Stratégies de recherches dédiées à la résolution de systèmes de contraintes sur les flottants pour la vérification de programmes : Search strategies for solving constraint systems over floats for program verification. [Internet] [Doctoral dissertation]. Côte d'Azur; 2018. [cited 2019 Jul 19]. Available from: http://www.theses.fr/2018AZUR4089.

Council of Science Editors:

Zitoun H. Stratégies de recherches dédiées à la résolution de systèmes de contraintes sur les flottants pour la vérification de programmes : Search strategies for solving constraint systems over floats for program verification. [Doctoral Dissertation]. Côte d'Azur; 2018. Available from: http://www.theses.fr/2018AZUR4089

27. Nehmeh, Riham. Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective.

Degree: Docteur es, Traitement du Signal et de l'Image, 2017, Rennes, INSA

 Le temps de mise sur le marché et les coûts d’implantation sont les deux critères principaux à prendre en compte dans l'automatisation du processus de… (more)

Subjects/Keywords: Optimisation; Applications; Floating-point arithmetic; Embedded computer systems; Computer simulation; Computer hardware description languages; 621.382

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APA (6th Edition):

Nehmeh, R. (2017). Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective. (Doctoral Dissertation). Rennes, INSA. Retrieved from http://www.theses.fr/2017ISAR0020

Chicago Manual of Style (16th Edition):

Nehmeh, Riham. “Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective.” 2017. Doctoral Dissertation, Rennes, INSA. Accessed July 19, 2019. http://www.theses.fr/2017ISAR0020.

MLA Handbook (7th Edition):

Nehmeh, Riham. “Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective.” 2017. Web. 19 Jul 2019.

Vancouver:

Nehmeh R. Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective. [Internet] [Doctoral dissertation]. Rennes, INSA; 2017. [cited 2019 Jul 19]. Available from: http://www.theses.fr/2017ISAR0020.

Council of Science Editors:

Nehmeh R. Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective. [Doctoral Dissertation]. Rennes, INSA; 2017. Available from: http://www.theses.fr/2017ISAR0020


Luleå University of Technology

28. Ekeroot, Jonas. Audio software development : an audio quality perspective.

Degree: 2008, Luleå University of Technology

Audio Technology as an academic discipline at Luleå University of Technology does not yet have a long research tradition and is therefore in the… (more)

Subjects/Keywords: Technology; audio; software; development; API; signal path; C++; floating point; dither; quality; Teknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ekeroot, J. (2008). Audio software development : an audio quality perspective. (Thesis). Luleå University of Technology. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-52723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ekeroot, Jonas. “Audio software development : an audio quality perspective.” 2008. Thesis, Luleå University of Technology. Accessed July 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-52723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ekeroot, Jonas. “Audio software development : an audio quality perspective.” 2008. Web. 19 Jul 2019.

Vancouver:

Ekeroot J. Audio software development : an audio quality perspective. [Internet] [Thesis]. Luleå University of Technology; 2008. [cited 2019 Jul 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-52723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ekeroot J. Audio software development : an audio quality perspective. [Thesis]. Luleå University of Technology; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-52723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

29. Min, Jae Hong. Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier.

Degree: Electrical and Computer Engineering, 2010, University of Texas – Austin

 Fused floating-point arithmetic units such as a floating-point fused Dot-Product (fused DP) and a floating-point fused Add-Subtract (fused AS) are employed for the implementation of… (more)

Subjects/Keywords: Fused floating-point arithmetic unit; Multiple-constant multiplier; Butterfly unit of FFT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Min, J. H. (2010). Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-12-2495

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Min, Jae Hong. “Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier.” 2010. Thesis, University of Texas – Austin. Accessed July 19, 2019. http://hdl.handle.net/2152/ETD-UT-2010-12-2495.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Min, Jae Hong. “Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier.” 2010. Web. 19 Jul 2019.

Vancouver:

Min JH. Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier. [Internet] [Thesis]. University of Texas – Austin; 2010. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-12-2495.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Min JH. Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier. [Thesis]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-12-2495

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Chohra, Chemseddine. Towards reproducible, accurately rounded and efficient BLAS : Aspects algorithmiques et structurels des relations d'ordre partiel sur les graphes.

Degree: Docteur es, Informatique, 2017, Perpignan

Le problème de non-reproductibilté numérique surgit dans les calculs parallèles principalement à cause de la non-associativité de l’addition flottante. Les environnements parallèles changent dynamiquement l’ordre… (more)

Subjects/Keywords: Reproductibilité; BLAS; Efficacité; Parallélisme; Précision; Reproducibility; Accuracy; Efficiency; BLAS; Parallelism; Floating-point; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chohra, C. (2017). Towards reproducible, accurately rounded and efficient BLAS : Aspects algorithmiques et structurels des relations d'ordre partiel sur les graphes. (Doctoral Dissertation). Perpignan. Retrieved from http://www.theses.fr/2017PERP0065

Chicago Manual of Style (16th Edition):

Chohra, Chemseddine. “Towards reproducible, accurately rounded and efficient BLAS : Aspects algorithmiques et structurels des relations d'ordre partiel sur les graphes.” 2017. Doctoral Dissertation, Perpignan. Accessed July 19, 2019. http://www.theses.fr/2017PERP0065.

MLA Handbook (7th Edition):

Chohra, Chemseddine. “Towards reproducible, accurately rounded and efficient BLAS : Aspects algorithmiques et structurels des relations d'ordre partiel sur les graphes.” 2017. Web. 19 Jul 2019.

Vancouver:

Chohra C. Towards reproducible, accurately rounded and efficient BLAS : Aspects algorithmiques et structurels des relations d'ordre partiel sur les graphes. [Internet] [Doctoral dissertation]. Perpignan; 2017. [cited 2019 Jul 19]. Available from: http://www.theses.fr/2017PERP0065.

Council of Science Editors:

Chohra C. Towards reproducible, accurately rounded and efficient BLAS : Aspects algorithmiques et structurels des relations d'ordre partiel sur les graphes. [Doctoral Dissertation]. Perpignan; 2017. Available from: http://www.theses.fr/2017PERP0065

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