Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:( VHDL). Showing records 1 – 30 of 472 total matches.

[1] [2] [3] [4] [5] … [16]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Languages

Country

▼ Search Limiters


University of Debrecen

1. Sebők, Ágnes Mária. Programozható logikai eszközök oktatásához szükséges segédanyagok, eszközök fejlesztése, elkészítése .

Degree: DE – TEK – Természettudományi és Technológiai Kar – Fizikai Intézet, 2012, University of Debrecen

A Fizika Intézetben található CPLD-k bemutatása, programozásukhoz szükséges VHDL nyelv ismertetése példaprogramokon keresztül. Advisors/Committee Members: Misák, Sándor (advisor).

Subjects/Keywords: CPLD; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sebők, . M. (2012). Programozható logikai eszközök oktatásához szükséges segédanyagok, eszközök fejlesztése, elkészítése . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/128923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sebők, Ágnes Mária. “Programozható logikai eszközök oktatásához szükséges segédanyagok, eszközök fejlesztése, elkészítése .” 2012. Thesis, University of Debrecen. Accessed August 20, 2019. http://hdl.handle.net/2437/128923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sebők, Ágnes Mária. “Programozható logikai eszközök oktatásához szükséges segédanyagok, eszközök fejlesztése, elkészítése .” 2012. Web. 20 Aug 2019.

Vancouver:

Sebők M. Programozható logikai eszközök oktatásához szükséges segédanyagok, eszközök fejlesztése, elkészítése . [Internet] [Thesis]. University of Debrecen; 2012. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/2437/128923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sebők M. Programozható logikai eszközök oktatásához szükséges segédanyagok, eszközök fejlesztése, elkészítése . [Thesis]. University of Debrecen; 2012. Available from: http://hdl.handle.net/2437/128923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

2. Szőke, Zoltán. Egyszerű videojáték implementálása FPGA-ra .

Degree: DE – TEK – Természettudományi és Technológiai Kar – Fizikai Intézet, 2010, University of Debrecen

 Napjainkban a digitális technika fejlődése megköveteli a fejlesztésben való új eszközök használatát. A témaválasztás egy ilyen eszköz megismerésére és használatára irányul. Az FPGA egy olyan… (more)

Subjects/Keywords: FPGA; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Szőke, Z. (2010). Egyszerű videojáték implementálása FPGA-ra . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/100517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Szőke, Zoltán. “Egyszerű videojáték implementálása FPGA-ra .” 2010. Thesis, University of Debrecen. Accessed August 20, 2019. http://hdl.handle.net/2437/100517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Szőke, Zoltán. “Egyszerű videojáték implementálása FPGA-ra .” 2010. Web. 20 Aug 2019.

Vancouver:

Szőke Z. Egyszerű videojáték implementálása FPGA-ra . [Internet] [Thesis]. University of Debrecen; 2010. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/2437/100517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Szőke Z. Egyszerű videojáték implementálása FPGA-ra . [Thesis]. University of Debrecen; 2010. Available from: http://hdl.handle.net/2437/100517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

3. Mokánszki, Ádám. Egyszerű Videójáték Implementálása FPGA-ra .

Degree: DE – TEK – Természettudományi és Technológiai Kar – Fizikai Intézet, 2010, University of Debrecen

 A projekt célja a Xilinx Spartan-3E FPGA család megismerése és a HDL nyelvek alapszintű ismeretének elsajátítása volt. A projekt fejlesztése során két személy dolgozott összhangban… (more)

Subjects/Keywords: FPGA; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mokánszki, . (2010). Egyszerű Videójáték Implementálása FPGA-ra . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/100529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mokánszki, Ádám. “Egyszerű Videójáték Implementálása FPGA-ra .” 2010. Thesis, University of Debrecen. Accessed August 20, 2019. http://hdl.handle.net/2437/100529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mokánszki, Ádám. “Egyszerű Videójáték Implementálása FPGA-ra .” 2010. Web. 20 Aug 2019.

Vancouver:

Mokánszki . Egyszerű Videójáték Implementálása FPGA-ra . [Internet] [Thesis]. University of Debrecen; 2010. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/2437/100529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mokánszki . Egyszerű Videójáték Implementálása FPGA-ra . [Thesis]. University of Debrecen; 2010. Available from: http://hdl.handle.net/2437/100529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

4. Angelo, Rubinei Peske. Implicações do estilo de descrição de códigos VHDL na testabilidade.

Degree: 2005, Universidade do Rio Grande do Sul

 Devido ao aumento da complexidade dos circuitos integrados atuais, os projetos são desenvolvidos utilizando linguagens de descrição de hardware (por exemplo, VHDL) e os circuitos… (more)

Subjects/Keywords: Microeletrônica; Vhdl

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Angelo, R. P. (2005). Implicações do estilo de descrição de códigos VHDL na testabilidade. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/4777

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Angelo, Rubinei Peske. “Implicações do estilo de descrição de códigos VHDL na testabilidade.” 2005. Thesis, Universidade do Rio Grande do Sul. Accessed August 20, 2019. http://hdl.handle.net/10183/4777.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Angelo, Rubinei Peske. “Implicações do estilo de descrição de códigos VHDL na testabilidade.” 2005. Web. 20 Aug 2019.

Vancouver:

Angelo RP. Implicações do estilo de descrição de códigos VHDL na testabilidade. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2005. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/10183/4777.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Angelo RP. Implicações do estilo de descrição de códigos VHDL na testabilidade. [Thesis]. Universidade do Rio Grande do Sul; 2005. Available from: http://hdl.handle.net/10183/4777

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

5. Schoneveld, G.J. VHDL to SystemC: The Design of a Translator:.

Degree: 2009, Delft University of Technology

VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to… (more)

Subjects/Keywords: VHDL; SystemC; translator; converter; compiler

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schoneveld, G. J. (2009). VHDL to SystemC: The Design of a Translator:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968

Chicago Manual of Style (16th Edition):

Schoneveld, G J. “VHDL to SystemC: The Design of a Translator:.” 2009. Masters Thesis, Delft University of Technology. Accessed August 20, 2019. http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968.

MLA Handbook (7th Edition):

Schoneveld, G J. “VHDL to SystemC: The Design of a Translator:.” 2009. Web. 20 Aug 2019.

Vancouver:

Schoneveld GJ. VHDL to SystemC: The Design of a Translator:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Aug 20]. Available from: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968.

Council of Science Editors:

Schoneveld GJ. VHDL to SystemC: The Design of a Translator:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968


University of Texas – Austin

6. Loyola, Jose Luis. Eksen : regression test selection for VHDL.

Degree: Electrical and Computer Engineering, 2018, University of Texas – Austin

 Regression testing - running tests after a change - has become a critical component of software development, but as projects grow bigger it becomes a… (more)

Subjects/Keywords: Regression; Test; Selection; VHDL; RTS

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Loyola, J. L. (2018). Eksen : regression test selection for VHDL. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Loyola, Jose Luis. “Eksen : regression test selection for VHDL.” 2018. Thesis, University of Texas – Austin. Accessed August 20, 2019. http://hdl.handle.net/2152/63753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Loyola, Jose Luis. “Eksen : regression test selection for VHDL.” 2018. Web. 20 Aug 2019.

Vancouver:

Loyola JL. Eksen : regression test selection for VHDL. [Internet] [Thesis]. University of Texas – Austin; 2018. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/2152/63753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Loyola JL. Eksen : regression test selection for VHDL. [Thesis]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

7. Frandina, Peter. VHDL modeling and synthesis of the JPEG-XR inverse transform.

Degree: Computer Engineering, 2009, Rochester Institute of Technology

 This work presents a pipelined VHDL implementation of the inverse lapped biorthogonal transform used in the decompression process of the soon to be released JPEG-XR… (more)

Subjects/Keywords: FPGA; ILBT; JPEG-XR; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Frandina, P. (2009). VHDL modeling and synthesis of the JPEG-XR inverse transform. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Frandina, Peter. “VHDL modeling and synthesis of the JPEG-XR inverse transform.” 2009. Thesis, Rochester Institute of Technology. Accessed August 20, 2019. https://scholarworks.rit.edu/theses/3157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Frandina, Peter. “VHDL modeling and synthesis of the JPEG-XR inverse transform.” 2009. Web. 20 Aug 2019.

Vancouver:

Frandina P. VHDL modeling and synthesis of the JPEG-XR inverse transform. [Internet] [Thesis]. Rochester Institute of Technology; 2009. [cited 2019 Aug 20]. Available from: https://scholarworks.rit.edu/theses/3157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Frandina P. VHDL modeling and synthesis of the JPEG-XR inverse transform. [Thesis]. Rochester Institute of Technology; 2009. Available from: https://scholarworks.rit.edu/theses/3157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kaunas University of Technology

8. Chaladauskas, Mindaugas. GSM LPC komponento realizavimas ir tyrimas.

Degree: Master, Informatics, 2010, Kaunas University of Technology

Kiekvienas, kuris kuria aparatūrinę įrangą, nori, tai atlikti kiek įmanoma greičiau ir už kuo mažesnius kaštus. Gaminys turi greitai patekti į rinką, nes egzistuojanti konkurencija… (more)

Subjects/Keywords: LPC; HLS; Sintezė; VHDL; LPC; HLS; Synthesis; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chaladauskas, Mindaugas. (2010). GSM LPC komponento realizavimas ir tyrimas. (Masters Thesis). Kaunas University of Technology. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Chaladauskas, Mindaugas. “GSM LPC komponento realizavimas ir tyrimas.” 2010. Masters Thesis, Kaunas University of Technology. Accessed August 20, 2019. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Chaladauskas, Mindaugas. “GSM LPC komponento realizavimas ir tyrimas.” 2010. Web. 20 Aug 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Chaladauskas, Mindaugas. GSM LPC komponento realizavimas ir tyrimas. [Internet] [Masters thesis]. Kaunas University of Technology; 2010. [cited 2019 Aug 20]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Chaladauskas, Mindaugas. GSM LPC komponento realizavimas ir tyrimas. [Masters Thesis]. Kaunas University of Technology; 2010. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

9. Κουκούλα, Βαλσαμίνα. Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα.

Degree: 2013, University of Patras

Η απεικόνιση και συμπίεση χωρικών δεδομένων έχει γίνει ένα θέμα έμφασης και προσοχής για τον τομέα των computer graphics και για εφαρμογές επεξεργασίας εικόνας. Τα… (more)

Subjects/Keywords: Αλγόριθμος quadtree; Γλώσσα VHDL; 006.693; Quadtrees; VHDL language

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Κουκούλα, . (2013). Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα. (Masters Thesis). University of Patras. Retrieved from http://hdl.handle.net/10889/6437

Chicago Manual of Style (16th Edition):

Κουκούλα, Βαλσαμίνα. “Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα.” 2013. Masters Thesis, University of Patras. Accessed August 20, 2019. http://hdl.handle.net/10889/6437.

MLA Handbook (7th Edition):

Κουκούλα, Βαλσαμίνα. “Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα.” 2013. Web. 20 Aug 2019.

Vancouver:

Κουκούλα . Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα. [Internet] [Masters thesis]. University of Patras; 2013. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/10889/6437.

Council of Science Editors:

Κουκούλα . Σχεδίαση του αλγόριθμου quadtree decomposition με γλώσσα περιγραφής VHDL για grayscale τετραγωνική εικόνα. [Masters Thesis]. University of Patras; 2013. Available from: http://hdl.handle.net/10889/6437


Kaunas University of Technology

10. Barys, Mindaugas. Failinių sistemų realizacijų, skirtų mikrovaldikliams, tyrimas ir tobulinimas.

Degree: Master, Informatics Engineering, 2011, Kaunas University of Technology

Elektronika per paskutinius 60 metų labai išsivystė. Šiuolaikiniai mikrovaldikliai yra sudėtingi ir produktyvūs elektronikos įrenginiai. Elektroninės technikos gamintojai stengiasi suteikti savo produkcijai kuo daugiau funkcijų,… (more)

Subjects/Keywords: FPGA; VHDL; Mikrovaldikliai; AVR; FPGA; VHDL; Microcontrollers; AVR

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Barys, Mindaugas. (2011). Failinių sistemų realizacijų, skirtų mikrovaldikliams, tyrimas ir tobulinimas. (Masters Thesis). Kaunas University of Technology. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110831_145358-22361 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Barys, Mindaugas. “Failinių sistemų realizacijų, skirtų mikrovaldikliams, tyrimas ir tobulinimas.” 2011. Masters Thesis, Kaunas University of Technology. Accessed August 20, 2019. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110831_145358-22361 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Barys, Mindaugas. “Failinių sistemų realizacijų, skirtų mikrovaldikliams, tyrimas ir tobulinimas.” 2011. Web. 20 Aug 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Barys, Mindaugas. Failinių sistemų realizacijų, skirtų mikrovaldikliams, tyrimas ir tobulinimas. [Internet] [Masters thesis]. Kaunas University of Technology; 2011. [cited 2019 Aug 20]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110831_145358-22361 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Barys, Mindaugas. Failinių sistemų realizacijų, skirtų mikrovaldikliams, tyrimas ir tobulinimas. [Masters Thesis]. Kaunas University of Technology; 2011. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110831_145358-22361 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Kaunas University of Technology

11. Riešutas, Andrius. Atvirojo kodo vaizdo generavimo modulių realizacijų, skirtų FPGA matricoms, tyrimas bei tobulinimas.

Degree: Master, Informatics Engineering, 2011, Kaunas University of Technology

Vis labiau modernėjant technologijoms, atsirandant naujoms specifinėms sistemoms ir poreikiams joms, turi būti tobulinamos esamos sistemos, kad atitiktų tiek profesionalų, tiek mėgėjų lūkesčius. Sistemos turi… (more)

Subjects/Keywords: FPGA; VGA; VHDL; Vaizdo perdavimas; FPGA; VGA; VHDL; Video transmission

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Riešutas, Andrius. (2011). Atvirojo kodo vaizdo generavimo modulių realizacijų, skirtų FPGA matricoms, tyrimas bei tobulinimas. (Masters Thesis). Kaunas University of Technology. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110901_123001-37524 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Riešutas, Andrius. “Atvirojo kodo vaizdo generavimo modulių realizacijų, skirtų FPGA matricoms, tyrimas bei tobulinimas.” 2011. Masters Thesis, Kaunas University of Technology. Accessed August 20, 2019. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110901_123001-37524 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Riešutas, Andrius. “Atvirojo kodo vaizdo generavimo modulių realizacijų, skirtų FPGA matricoms, tyrimas bei tobulinimas.” 2011. Web. 20 Aug 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Riešutas, Andrius. Atvirojo kodo vaizdo generavimo modulių realizacijų, skirtų FPGA matricoms, tyrimas bei tobulinimas. [Internet] [Masters thesis]. Kaunas University of Technology; 2011. [cited 2019 Aug 20]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110901_123001-37524 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Riešutas, Andrius. Atvirojo kodo vaizdo generavimo modulių realizacijų, skirtų FPGA matricoms, tyrimas bei tobulinimas. [Masters Thesis]. Kaunas University of Technology; 2011. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110901_123001-37524 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Brno University of Technology

12. Suchanek, Michal. Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA .

Degree: 2019, Brno University of Technology

 Cílem této bakalářské práce je seznámit se se standardem 25/50 Gigabit Ethernet Consortium, jenž definuje 50Gb/s Ethernet. Prostudovat specifikace pro PCS a PMA podvrstvy fyzické… (more)

Subjects/Keywords: FPGA; ethernet; VHDL; fyzická vrstva; FPGA; ethernet; VHDL; physical layer

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suchanek, M. (2019). Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/173798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Suchanek, Michal. “Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA .” 2019. Thesis, Brno University of Technology. Accessed August 20, 2019. http://hdl.handle.net/11012/173798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Suchanek, Michal. “Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA .” 2019. Web. 20 Aug 2019.

Vancouver:

Suchanek M. Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA . [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/11012/173798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Suchanek M. Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA . [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/173798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

13. Foltýn, Tomáš. Implementace kryptografických algoritmů v FPGA .

Degree: 2016, Brno University of Technology

 Tato práce se zabývá návrhem a implementací šifrovacího algoritmu AES v programovatelném hradlovém poli (FPGA). Návrh jednotky se zaměřuje na kompaktní design a výsledná datová… (more)

Subjects/Keywords: Kryptografie; FPGA; AES; FITkit; VHDL; Cryptography; FPGA; AES; FITkit; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Foltýn, T. (2016). Implementace kryptografických algoritmů v FPGA . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Foltýn, Tomáš. “Implementace kryptografických algoritmů v FPGA .” 2016. Thesis, Brno University of Technology. Accessed August 20, 2019. http://hdl.handle.net/11012/61809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Foltýn, Tomáš. “Implementace kryptografických algoritmů v FPGA .” 2016. Web. 20 Aug 2019.

Vancouver:

Foltýn T. Implementace kryptografických algoritmů v FPGA . [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/11012/61809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Foltýn T. Implementace kryptografických algoritmů v FPGA . [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/61809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

14. Bartek, Tomáš. Rozhraní pro ovládání průmyslových modulů LED .

Degree: 2014, Brno University of Technology

 Práce se zabývá modernizací na poli informačních LED panelů. Jejím cílem je vytvoření nového způsobu řízení LED modulů, který bude využívat výhody plynoucí z použití… (more)

Subjects/Keywords: Informační panely; LED; VHDL; FPGA; Information panels; LED; VHDL; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bartek, T. (2014). Rozhraní pro ovládání průmyslových modulů LED . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/33986

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bartek, Tomáš. “Rozhraní pro ovládání průmyslových modulů LED .” 2014. Thesis, Brno University of Technology. Accessed August 20, 2019. http://hdl.handle.net/11012/33986.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bartek, Tomáš. “Rozhraní pro ovládání průmyslových modulů LED .” 2014. Web. 20 Aug 2019.

Vancouver:

Bartek T. Rozhraní pro ovládání průmyslových modulů LED . [Internet] [Thesis]. Brno University of Technology; 2014. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/11012/33986.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bartek T. Rozhraní pro ovládání průmyslových modulů LED . [Thesis]. Brno University of Technology; 2014. Available from: http://hdl.handle.net/11012/33986

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

15. Dolejší, Miloš. Řízení barevného grafického LED displeje pomocí FPGA .

Degree: 2017, Brno University of Technology

 Tato diplomová práce se věnuje řízení barevného grafického LED displeje pomocí FPGA. V teoretické části byly popsány vlastnosti použitého FPGA, zdroj dat a princip řízení… (more)

Subjects/Keywords: FPGA; LED displej; VHDL; BRAM; FPGA; LED display; VHDL; BRAM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dolejší, M. (2017). Řízení barevného grafického LED displeje pomocí FPGA . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/65793

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dolejší, Miloš. “Řízení barevného grafického LED displeje pomocí FPGA .” 2017. Thesis, Brno University of Technology. Accessed August 20, 2019. http://hdl.handle.net/11012/65793.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dolejší, Miloš. “Řízení barevného grafického LED displeje pomocí FPGA .” 2017. Web. 20 Aug 2019.

Vancouver:

Dolejší M. Řízení barevného grafického LED displeje pomocí FPGA . [Internet] [Thesis]. Brno University of Technology; 2017. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/11012/65793.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dolejší M. Řízení barevného grafického LED displeje pomocí FPGA . [Thesis]. Brno University of Technology; 2017. Available from: http://hdl.handle.net/11012/65793

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

16. Matušová, Lucie. Perfektní hašování v FPGA .

Degree: 2011, Brno University of Technology

 Tato práce se zabývá návrhem a implementací perfektního hašování do FPGA pomocí metody FCH. Metoda vyniká paměťovou složitostí 2.6 bitů na klíč. Pro účely referenční… (more)

Subjects/Keywords: FPGA; perfektní hašování; VHDL; FPGA; perfect hashing; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matušová, L. (2011). Perfektní hašování v FPGA . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55789

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matušová, Lucie. “Perfektní hašování v FPGA .” 2011. Thesis, Brno University of Technology. Accessed August 20, 2019. http://hdl.handle.net/11012/55789.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matušová, Lucie. “Perfektní hašování v FPGA .” 2011. Web. 20 Aug 2019.

Vancouver:

Matušová L. Perfektní hašování v FPGA . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/11012/55789.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matušová L. Perfektní hašování v FPGA . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/55789

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

17. Kliment, Vojtěch. Pokročilý editor VHDL souborů .

Degree: 2012, Brno University of Technology

 Tato bakálářská práce se zabývá vývojem aplikace, která umožňuje návrháři číslicových obvodů snadněji vkládat a propojovat jednotlivé komponenty VHDL entity. Práce vysvětluje základní principy jazyka… (more)

Subjects/Keywords: VHDL; syntetizovatelné šablony; editor; VHDL; synthesizable templates; editor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kliment, V. (2012). Pokročilý editor VHDL souborů . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55259

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kliment, Vojtěch. “Pokročilý editor VHDL souborů .” 2012. Thesis, Brno University of Technology. Accessed August 20, 2019. http://hdl.handle.net/11012/55259.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kliment, Vojtěch. “Pokročilý editor VHDL souborů .” 2012. Web. 20 Aug 2019.

Vancouver:

Kliment V. Pokročilý editor VHDL souborů . [Internet] [Thesis]. Brno University of Technology; 2012. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/11012/55259.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kliment V. Pokročilý editor VHDL souborů . [Thesis]. Brno University of Technology; 2012. Available from: http://hdl.handle.net/11012/55259

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Addis Ababa University

18. Kibret, Abebe. Design of 3D Graphics Accelerator Core for FPGA .

Degree: 2013, Addis Ababa University

 In this thesis we designed and synthesized 3D graphics accelerator Intellectual Property (IP) using VHDL. The main parts which were designed in this work include:… (more)

Subjects/Keywords: 3D graphics; VHDL; Accelerator Core; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kibret, A. (2013). Design of 3D Graphics Accelerator Core for FPGA . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/4500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kibret, Abebe. “Design of 3D Graphics Accelerator Core for FPGA .” 2013. Thesis, Addis Ababa University. Accessed August 20, 2019. http://etd.aau.edu.et/dspace/handle/123456789/4500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kibret, Abebe. “Design of 3D Graphics Accelerator Core for FPGA .” 2013. Web. 20 Aug 2019.

Vancouver:

Kibret A. Design of 3D Graphics Accelerator Core for FPGA . [Internet] [Thesis]. Addis Ababa University; 2013. [cited 2019 Aug 20]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kibret A. Design of 3D Graphics Accelerator Core for FPGA . [Thesis]. Addis Ababa University; 2013. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

19. REVANURU, MURTHY N. MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS.

Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati

 The limitations of the SPICE language has given rise to new simulation languages and environments. VHDL-AMS is one such language, which supports analog and mixed-mode… (more)

Subjects/Keywords: VHDL-AMS MODELING

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

REVANURU, M. N. (2001). MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin984506181

Chicago Manual of Style (16th Edition):

REVANURU, MURTHY N. “MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS.” 2001. Masters Thesis, University of Cincinnati. Accessed August 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin984506181.

MLA Handbook (7th Edition):

REVANURU, MURTHY N. “MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS.” 2001. Web. 20 Aug 2019.

Vancouver:

REVANURU MN. MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS. [Internet] [Masters thesis]. University of Cincinnati; 2001. [cited 2019 Aug 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin984506181.

Council of Science Editors:

REVANURU MN. MODELING AND SIMULATION OF AN FM RECEIVER USING VHDL-AMS. [Masters Thesis]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin984506181


Universidade do Rio Grande do Sul

20. Rosa, Vagner Santos da. Uma ferramenta para geração de filtros FIR paralelos otimizados com coeficientes constantes.

Degree: 2005, Universidade do Rio Grande do Sul

 Esta dissertação trata da elaboração de uma ferrramenta para a geração de filtros FIR otimizados paralelos com coeficientes constantes. A ferramenta desenvolvida é capaz de… (more)

Subjects/Keywords: Filtros digitais; Vhdl

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rosa, V. S. d. (2005). Uma ferramenta para geração de filtros FIR paralelos otimizados com coeficientes constantes. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/5661

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rosa, Vagner Santos da. “Uma ferramenta para geração de filtros FIR paralelos otimizados com coeficientes constantes.” 2005. Thesis, Universidade do Rio Grande do Sul. Accessed August 20, 2019. http://hdl.handle.net/10183/5661.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rosa, Vagner Santos da. “Uma ferramenta para geração de filtros FIR paralelos otimizados com coeficientes constantes.” 2005. Web. 20 Aug 2019.

Vancouver:

Rosa VSd. Uma ferramenta para geração de filtros FIR paralelos otimizados com coeficientes constantes. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2005. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/10183/5661.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rosa VSd. Uma ferramenta para geração de filtros FIR paralelos otimizados com coeficientes constantes. [Thesis]. Universidade do Rio Grande do Sul; 2005. Available from: http://hdl.handle.net/10183/5661

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Uppsala University

21. Götbring, Sebastian. Power Optimization of Image Filtering with FPGA.

Degree: 2018, Uppsala University

  High speed real time video processing puts a lot of demand on hardware and Field Programmable Gate Arrays (FPGA) are becoming more popular for… (more)

Subjects/Keywords: FPGA; VHDL; Power; Filtering; Signal Processing; Signalbehandling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Götbring, S. (2018). Power Optimization of Image Filtering with FPGA. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-353775

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Götbring, Sebastian. “Power Optimization of Image Filtering with FPGA.” 2018. Thesis, Uppsala University. Accessed August 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-353775.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Götbring, Sebastian. “Power Optimization of Image Filtering with FPGA.” 2018. Web. 20 Aug 2019.

Vancouver:

Götbring S. Power Optimization of Image Filtering with FPGA. [Internet] [Thesis]. Uppsala University; 2018. [cited 2019 Aug 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-353775.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Götbring S. Power Optimization of Image Filtering with FPGA. [Thesis]. Uppsala University; 2018. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-353775

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Cifredo-Chacón, María Ángeles. Un procedimiento para la clasificación y verificación priorizada de FPGAS de bajo coste ante aplicaciones sectoriales electrónicas.

Degree: 2018, Universidad de Cádiz

Subjects/Keywords: FPGA; VHDL; BENCHMARK

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cifredo-Chacón, M. . (2018). Un procedimiento para la clasificación y verificación priorizada de FPGAS de bajo coste ante aplicaciones sectoriales electrónicas. (Thesis). Universidad de Cádiz. Retrieved from http://hdl.handle.net/10498/16751

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cifredo-Chacón, María Ángeles. “Un procedimiento para la clasificación y verificación priorizada de FPGAS de bajo coste ante aplicaciones sectoriales electrónicas.” 2018. Thesis, Universidad de Cádiz. Accessed August 20, 2019. http://hdl.handle.net/10498/16751.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cifredo-Chacón, María Ángeles. “Un procedimiento para la clasificación y verificación priorizada de FPGAS de bajo coste ante aplicaciones sectoriales electrónicas.” 2018. Web. 20 Aug 2019.

Vancouver:

Cifredo-Chacón M. Un procedimiento para la clasificación y verificación priorizada de FPGAS de bajo coste ante aplicaciones sectoriales electrónicas. [Internet] [Thesis]. Universidad de Cádiz; 2018. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/10498/16751.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cifredo-Chacón M. Un procedimiento para la clasificación y verificación priorizada de FPGAS de bajo coste ante aplicaciones sectoriales electrónicas. [Thesis]. Universidad de Cádiz; 2018. Available from: http://hdl.handle.net/10498/16751

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Mid Sweden University

23. Mulder, Aart. Robust and flexible hardware implementation of ITU-G4.

Degree: Electronics Design, 2014, Mid Sweden University

  This project was carried out as thesis work during the last semester of my Master studies Electronics Design at the Mid Sweden University. Firstly,… (more)

Subjects/Keywords: VHDL; Image compression; Fax4; ITU-G4

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mulder, A. (2014). Robust and flexible hardware implementation of ITU-G4. (Thesis). Mid Sweden University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-24022

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mulder, Aart. “Robust and flexible hardware implementation of ITU-G4.” 2014. Thesis, Mid Sweden University. Accessed August 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-24022.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mulder, Aart. “Robust and flexible hardware implementation of ITU-G4.” 2014. Web. 20 Aug 2019.

Vancouver:

Mulder A. Robust and flexible hardware implementation of ITU-G4. [Internet] [Thesis]. Mid Sweden University; 2014. [cited 2019 Aug 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-24022.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mulder A. Robust and flexible hardware implementation of ITU-G4. [Thesis]. Mid Sweden University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-24022

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Nordmark, Daniel. Implementering av en mjuk CPU i FPGA.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

Målet med examensarbetet är att implementera en mjuk CPU i en FPGA-krets som finns tillgänglig på ett ALTERA DE2 Board. Denna mjuka processor integreras… (more)

Subjects/Keywords: SOPC; Quartus; VHDL; Mjuk CPU; Nios II

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nordmark, D. (2012). Implementering av en mjuk CPU i FPGA. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79337

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nordmark, Daniel. “Implementering av en mjuk CPU i FPGA.” 2012. Thesis, Linköping UniversityLinköping University. Accessed August 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79337.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nordmark, Daniel. “Implementering av en mjuk CPU i FPGA.” 2012. Web. 20 Aug 2019.

Vancouver:

Nordmark D. Implementering av en mjuk CPU i FPGA. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2019 Aug 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79337.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nordmark D. Implementering av en mjuk CPU i FPGA. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79337

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Uppsala University

25. Halvarsson, Tomas. Ett kommunikationssystem för fiberoptisk överföring av bilddata förvärvad av en miniatyriserad undervattensfarkost.

Degree: Ångström Space Technology Centre (ÅSTC), 2011, Uppsala University

This report describes the development and implementation of a system for transmitting digital information at high speeds from a miniaturized submersible developed by the… (more)

Subjects/Keywords: Datakommunikation; FPGA; Informationsöverföring; VHDL; Electronics; Elektronik

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Halvarsson, T. (2011). Ett kommunikationssystem för fiberoptisk överföring av bilddata förvärvad av en miniatyriserad undervattensfarkost. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-152148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Halvarsson, Tomas. “Ett kommunikationssystem för fiberoptisk överföring av bilddata förvärvad av en miniatyriserad undervattensfarkost.” 2011. Thesis, Uppsala University. Accessed August 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-152148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Halvarsson, Tomas. “Ett kommunikationssystem för fiberoptisk överföring av bilddata förvärvad av en miniatyriserad undervattensfarkost.” 2011. Web. 20 Aug 2019.

Vancouver:

Halvarsson T. Ett kommunikationssystem för fiberoptisk överföring av bilddata förvärvad av en miniatyriserad undervattensfarkost. [Internet] [Thesis]. Uppsala University; 2011. [cited 2019 Aug 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-152148.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Halvarsson T. Ett kommunikationssystem för fiberoptisk överföring av bilddata förvärvad av en miniatyriserad undervattensfarkost. [Thesis]. Uppsala University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-152148

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

26. Van der Sluijs, R. Hardware implementation of digital signal processing algorithms for long distance pipeline inspections:.

Degree: 2010, Delft University of Technology

 Inspections on transmission pipelines in the petrochemical industry are regularly conducted in order to guarantee safety of operations. Inspection devices are sent through the lines… (more)

Subjects/Keywords: FPGA; DSP; VHDL; Linux; PCI-Express

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Van der Sluijs, R. (2010). Hardware implementation of digital signal processing algorithms for long distance pipeline inspections:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:34c62679-c826-4169-a84f-f101d012478e

Chicago Manual of Style (16th Edition):

Van der Sluijs, R. “Hardware implementation of digital signal processing algorithms for long distance pipeline inspections:.” 2010. Masters Thesis, Delft University of Technology. Accessed August 20, 2019. http://resolver.tudelft.nl/uuid:34c62679-c826-4169-a84f-f101d012478e.

MLA Handbook (7th Edition):

Van der Sluijs, R. “Hardware implementation of digital signal processing algorithms for long distance pipeline inspections:.” 2010. Web. 20 Aug 2019.

Vancouver:

Van der Sluijs R. Hardware implementation of digital signal processing algorithms for long distance pipeline inspections:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2019 Aug 20]. Available from: http://resolver.tudelft.nl/uuid:34c62679-c826-4169-a84f-f101d012478e.

Council of Science Editors:

Van der Sluijs R. Hardware implementation of digital signal processing algorithms for long distance pipeline inspections:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:34c62679-c826-4169-a84f-f101d012478e

27. Holstensson, Oskar. Study of Interferer Canceling Systems in a Software Defined Radio Receiver.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  This thesis describes the work related to an interferer rejection system employing frequency analysis and cancellation through phase-opposed signal injection. The first device in… (more)

Subjects/Keywords: ASIC; FFT; Interferer Cancellation; RF; SDR; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Holstensson, O. (2013). Study of Interferer Canceling Systems in a Software Defined Radio Receiver. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Holstensson, Oskar. “Study of Interferer Canceling Systems in a Software Defined Radio Receiver.” 2013. Thesis, Linköping UniversityLinköping University. Accessed August 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Holstensson, Oskar. “Study of Interferer Canceling Systems in a Software Defined Radio Receiver.” 2013. Web. 20 Aug 2019.

Vancouver:

Holstensson O. Study of Interferer Canceling Systems in a Software Defined Radio Receiver. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2019 Aug 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Holstensson O. Study of Interferer Canceling Systems in a Software Defined Radio Receiver. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92757

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Hansson, Felix. Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  FPGA-kort är ett bra verktyg för företag som snabbt vill kunna ta fram en prototyp för nya projekt, då de är omprogrammeringsbara så att… (more)

Subjects/Keywords: FPGA; NIOS2; SOPC Builder; QSYS; VHDL; VGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hansson, F. (2013). Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94340

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hansson, Felix. “Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores.” 2013. Thesis, Linköping UniversityLinköping University. Accessed August 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94340.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hansson, Felix. “Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores.” 2013. Web. 20 Aug 2019.

Vancouver:

Hansson F. Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2019 Aug 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94340.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hansson F. Jämförelse av VGA-lösningar till NIOS2-system i SOPC Builder och QSYS med Altera University Program IP-Cores. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94340

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Commonwealth University

29. DeMott, Robert. Development of a Flexible FPGA-Based Platform for Flight Control System Research.

Degree: MS, Engineering, 2010, Virginia Commonwealth University

 This work is part of ongoing research conducted at Virginia Commonwealth University relating to unmanned aerial vehicles. The primary objective of this thesis was to… (more)

Subjects/Keywords: FPGA; UAV; FCS; Autopilot; VHDL; PCB; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

DeMott, R. (2010). Development of a Flexible FPGA-Based Platform for Flight Control System Research. (Thesis). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/2321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DeMott, Robert. “Development of a Flexible FPGA-Based Platform for Flight Control System Research.” 2010. Thesis, Virginia Commonwealth University. Accessed August 20, 2019. https://scholarscompass.vcu.edu/etd/2321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DeMott, Robert. “Development of a Flexible FPGA-Based Platform for Flight Control System Research.” 2010. Web. 20 Aug 2019.

Vancouver:

DeMott R. Development of a Flexible FPGA-Based Platform for Flight Control System Research. [Internet] [Thesis]. Virginia Commonwealth University; 2010. [cited 2019 Aug 20]. Available from: https://scholarscompass.vcu.edu/etd/2321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DeMott R. Development of a Flexible FPGA-Based Platform for Flight Control System Research. [Thesis]. Virginia Commonwealth University; 2010. Available from: https://scholarscompass.vcu.edu/etd/2321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Newcastle

30. Fitzpatrick, Chris. Firmwares for high-speed signal processing applications.

Degree: MPhil, 2016, University of Newcastle

Masters Research - Master of Philosophy (MPhil)

Matrix-vector multiplication is widely used in science and engineering. With the constant increase in data throughput rates, computing… (more)

Subjects/Keywords: VHDL; FPGA; matrix; vector; floating point; MAC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fitzpatrick, C. (2016). Firmwares for high-speed signal processing applications. (Masters Thesis). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/1312018

Chicago Manual of Style (16th Edition):

Fitzpatrick, Chris. “Firmwares for high-speed signal processing applications.” 2016. Masters Thesis, University of Newcastle. Accessed August 20, 2019. http://hdl.handle.net/1959.13/1312018.

MLA Handbook (7th Edition):

Fitzpatrick, Chris. “Firmwares for high-speed signal processing applications.” 2016. Web. 20 Aug 2019.

Vancouver:

Fitzpatrick C. Firmwares for high-speed signal processing applications. [Internet] [Masters thesis]. University of Newcastle; 2016. [cited 2019 Aug 20]. Available from: http://hdl.handle.net/1959.13/1312018.

Council of Science Editors:

Fitzpatrick C. Firmwares for high-speed signal processing applications. [Masters Thesis]. University of Newcastle; 2016. Available from: http://hdl.handle.net/1959.13/1312018

[1] [2] [3] [4] [5] … [16]

.