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You searched for subject:( Redes em chip NoC ). Showing records 1 – 30 of 30729 total matches.

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1. Sílvio Roberto Fernandes de Araújo. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em <em class="hilite">redesem> em chip sem processadores: sistema IPNoSys.

Degree: 2008, Universidade Federal do Rio Grande do Norte

O aumento na capacidade de integração de transistores permitiu o desenvolvimento de sistemas completos, com inúmeros componentes, dentro de um único chip, são os chamados… (more)

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; SISTEMAS DE COMPUTACAO; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Thesis, Universidade Federal do Rio Grande do Norte. Accessed May 31, 2020. http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys.” 2008. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. [cited 2020 May 31]. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys. [Thesis]. Universidade Federal do Rio Grande do Norte; 2008. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=1541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

2. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em <em class="hilite">Redesem> em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

 It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features… (more)

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17948.

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2012. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948


Universidade do Rio Grande do Norte

3. Araújo, Sílvio Roberto Fernandes de. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em <em class="hilite">redesem> em chip sem processadores: sistema IPNoSys .

Degree: 2008, Universidade do Rio Grande do Norte

 The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the… (more)

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Masters Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17969.

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17969.

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Masters Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969


Universidade do Rio Grande do Norte

4. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em <em class="hilite">Redesem> em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

 It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features… (more)

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

5. Araújo, Sílvio Roberto Fernandes de. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em <em class="hilite">redesem> em chip sem processadores: sistema IPNoSys .

Degree: 2008, Universidade do Rio Grande do Norte

 The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the… (more)

Subjects/Keywords: Sistema em chip (SoC); Redes em chip (NoC); Algoritmo spiral complement; Sistema IPNoSys; System-on-chip (SoC); Network-on-chip (NoC); Spiral complement algorithm; IPNoSys system

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2008). Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys .” 2008. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2008. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2008. Available from: http://repositorio.ufrn.br/handle/123456789/17969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

6. Oliveira, Tadeu Ferreira. Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios .

Degree: 2010, Universidade do Rio Grande do Norte

 The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with… (more)

Subjects/Keywords: sistema operacional; biblioteca de função; MPSoC; multiprocessor systema-on-Chip; redes em chip; NoC; network-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, T. F. (2010). Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18053

Chicago Manual of Style (16th Edition):

Oliveira, Tadeu Ferreira. “Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios .” 2010. Masters Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/18053.

MLA Handbook (7th Edition):

Oliveira, Tadeu Ferreira. “Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios .” 2010. Web. 31 May 2020.

Vancouver:

Oliveira TF. Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2010. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/18053.

Council of Science Editors:

Oliveira TF. Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios . [Masters Thesis]. Universidade do Rio Grande do Norte; 2010. Available from: http://repositorio.ufrn.br/handle/123456789/18053


Universidade do Rio Grande do Norte

7. Oliveira, Tadeu Ferreira. Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios .

Degree: 2010, Universidade do Rio Grande do Norte

 The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with… (more)

Subjects/Keywords: sistema operacional; biblioteca de função; MPSoC; multiprocessor systema-on-Chip; redes em chip; NoC; network-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, T. F. (2010). Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Tadeu Ferreira. “Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios .” 2010. Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/18053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Tadeu Ferreira. “Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios .” 2010. Web. 31 May 2020.

Vancouver:

Oliveira TF. Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2010. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/18053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira TF. Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios . [Thesis]. Universidade do Rio Grande do Norte; 2010. Available from: http://repositorio.ufrn.br/handle/123456789/18053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. KAMEI, Camila Ascendina Nunes. Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC .

Degree: 2015, Universidade Federal de Pernambuco

 Duas questões são críticas em sistemas com paralelismo de memória em rede NoC baseados em MPSoC, a ordem de entrega da mensagem e o congestionamento… (more)

Subjects/Keywords: NoC - Network-on-Chip; Congestionamento em NoC; Algoritmo Adaptativo; NoC - Network-on-Chip; Congestion on NoC; Adaptative Algorithm

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

KAMEI, C. A. N. (2015). Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC . (Masters Thesis). Universidade Federal de Pernambuco. Retrieved from https://repositorio.ufpe.br/handle/123456789/17243

Chicago Manual of Style (16th Edition):

KAMEI, Camila Ascendina Nunes. “Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC .” 2015. Masters Thesis, Universidade Federal de Pernambuco. Accessed May 31, 2020. https://repositorio.ufpe.br/handle/123456789/17243.

MLA Handbook (7th Edition):

KAMEI, Camila Ascendina Nunes. “Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC .” 2015. Web. 31 May 2020.

Vancouver:

KAMEI CAN. Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC . [Internet] [Masters thesis]. Universidade Federal de Pernambuco; 2015. [cited 2020 May 31]. Available from: https://repositorio.ufpe.br/handle/123456789/17243.

Council of Science Editors:

KAMEI CAN. Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC . [Masters Thesis]. Universidade Federal de Pernambuco; 2015. Available from: https://repositorio.ufpe.br/handle/123456789/17243


Universidade do Rio Grande do Norte

9. Medeiros, Aparecida Lopes de. Implementação da técnica de software pipelining na rede em chip IPNoSyS .

Degree: 2014, Universidade do Rio Grande do Norte

 Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors,… (more)

Subjects/Keywords: Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho; Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Medeiros, A. L. d. (2014). Implementação da técnica de software pipelining na rede em chip IPNoSyS . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18100

Chicago Manual of Style (16th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Masters Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/18100.

MLA Handbook (7th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Web. 31 May 2020.

Vancouver:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/18100.

Council of Science Editors:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Masters Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/18100


Universidade do Rio Grande do Norte

10. Medeiros, Aparecida Lopes de. Implementação da técnica de software pipelining na rede em chip IPNoSyS .

Degree: 2014, Universidade do Rio Grande do Norte

 Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors,… (more)

Subjects/Keywords: Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho; Redes em chip. Processadores. IPNoSyS. Paralelismo. Software Pipelining. Desempenho

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Medeiros, A. L. d. (2014). Implementação da técnica de software pipelining na rede em chip IPNoSyS . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/18100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Medeiros, Aparecida Lopes de. “Implementação da técnica de software pipelining na rede em chip IPNoSyS .” 2014. Web. 31 May 2020.

Vancouver:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/18100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Medeiros ALd. Implementação da técnica de software pipelining na rede em chip IPNoSyS . [Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/18100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Sepúlveda Flórez, Martha Johanna. Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança.

Degree: PhD, Microeletrônica, 2011, University of São Paulo

Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a… (more)

Subjects/Keywords: Estrutura de comunicação; Network-on-Chip (NoC); Qualidade de serviços; Quality of Security Service (QoSS); Quality-of-Service (QoS); Redes; Security; Segurança; Silício (Sistemas; Projeto); System-on-Chip (SoC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sepúlveda Flórez, M. J. (2011). Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;

Chicago Manual of Style (16th Edition):

Sepúlveda Flórez, Martha Johanna. “Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança.” 2011. Doctoral Dissertation, University of São Paulo. Accessed May 31, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;.

MLA Handbook (7th Edition):

Sepúlveda Flórez, Martha Johanna. “Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança.” 2011. Web. 31 May 2020.

Vancouver:

Sepúlveda Flórez MJ. Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança. [Internet] [Doctoral dissertation]. University of São Paulo; 2011. [cited 2020 May 31]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;.

Council of Science Editors:

Sepúlveda Flórez MJ. Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança. [Doctoral Dissertation]. University of São Paulo; 2011. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/ ;


Universidade Estadual de Campinas

12. Abdnur, Thiago Borges, 1984-. Construção e avaliação de uma solução eficiente para comunicação entre processadores SPARCv8 .

Degree: 2012, Universidade Estadual de Campinas

 Resumo: Com a mudança da maior parte das arquiteturas convencionais para multi-core a comunica _cão entre as diferentes unidades de processamento se torna um problema… (more)

Subjects/Keywords: Arquitetura de computador; Redes - em - chip; Circuitos integrados digitais

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abdnur, Thiago Borges, 1. (2012). Construção e avaliação de uma solução eficiente para comunicação entre processadores SPARCv8 . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/275660

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abdnur, Thiago Borges, 1984-. “Construção e avaliação de uma solução eficiente para comunicação entre processadores SPARCv8 .” 2012. Thesis, Universidade Estadual de Campinas. Accessed May 31, 2020. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275660.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abdnur, Thiago Borges, 1984-. “Construção e avaliação de uma solução eficiente para comunicação entre processadores SPARCv8 .” 2012. Web. 31 May 2020.

Vancouver:

Abdnur, Thiago Borges 1. Construção e avaliação de uma solução eficiente para comunicação entre processadores SPARCv8 . [Internet] [Thesis]. Universidade Estadual de Campinas; 2012. [cited 2020 May 31]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/275660.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abdnur, Thiago Borges 1. Construção e avaliação de uma solução eficiente para comunicação entre processadores SPARCv8 . [Thesis]. Universidade Estadual de Campinas; 2012. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/275660

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

13. Mesquita, Jonathan Wanderley de. Exploração de espaço de projeto para geração de <em class="hilite">redesem> em chip de topologias irregulares otimizadas: a rede UTNoC .

Degree: 2016, Universidade do Rio Grande do Norte

 During the design of multiprocessor architectures, the design space exploration step may be aided by tools that assist and accelerate this process. The project of… (more)

Subjects/Keywords: Redes em chip; Topologia irregular; Exploração de espaço de projeto

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mesquita, J. W. d. (2016). Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/22558

Chicago Manual of Style (16th Edition):

Mesquita, Jonathan Wanderley de. “Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC .” 2016. Masters Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/22558.

MLA Handbook (7th Edition):

Mesquita, Jonathan Wanderley de. “Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC .” 2016. Web. 31 May 2020.

Vancouver:

Mesquita JWd. Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2016. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/22558.

Council of Science Editors:

Mesquita JWd. Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC . [Masters Thesis]. Universidade do Rio Grande do Norte; 2016. Available from: http://repositorio.ufrn.br/handle/123456789/22558


University of Cincinnati

14. SWAMINATHAN, VIJAY. PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

 Most of the NoCs that exist today for FPGA use a single clock. The performance of a single clock system is limited by the delay… (more)

Subjects/Keywords: FPGA; Network On Chip; NoC; Multiclock NoC; Reconfigurable Systems; Multiclock

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SWAMINATHAN, V. (2007). PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922

Chicago Manual of Style (16th Edition):

SWAMINATHAN, VIJAY. “PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA.” 2007. Masters Thesis, University of Cincinnati. Accessed May 31, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922.

MLA Handbook (7th Edition):

SWAMINATHAN, VIJAY. “PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA.” 2007. Web. 31 May 2020.

Vancouver:

SWAMINATHAN V. PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2020 May 31]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922.

Council of Science Editors:

SWAMINATHAN V. PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922


Texas A&M University

15. Park, Sungho. A verilog-hdl implementation of virtual channels in a network-on-chip router.

Degree: 2009, Texas A&M University

 As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a… (more)

Subjects/Keywords: NoC; Virtual Channels; Network-on-Chip; router

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, S. (2009). A verilog-hdl implementation of virtual channels in a network-on-chip router. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2890

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Sungho. “A verilog-hdl implementation of virtual channels in a network-on-chip router.” 2009. Thesis, Texas A&M University. Accessed May 31, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2890.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Sungho. “A verilog-hdl implementation of virtual channels in a network-on-chip router.” 2009. Web. 31 May 2020.

Vancouver:

Park S. A verilog-hdl implementation of virtual channels in a network-on-chip router. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 May 31]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2890.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park S. A verilog-hdl implementation of virtual channels in a network-on-chip router. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2890

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de València

16. Roca Pérez, Antoni. Floorplan-Aware High Performance NoC Design .

Degree: 2012, Universitat Politècnica de València

 Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las <em class="hilite">redesem>… (more)

Subjects/Keywords: Noc; Switch design; On-chip networks; Vlsi

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/17844

Chicago Manual of Style (16th Edition):

Roca Pérez, Antoni. “Floorplan-Aware High Performance NoC Design .” 2012. Doctoral Dissertation, Universitat Politècnica de València. Accessed May 31, 2020. http://hdl.handle.net/10251/17844.

MLA Handbook (7th Edition):

Roca Pérez, Antoni. “Floorplan-Aware High Performance NoC Design .” 2012. Web. 31 May 2020.

Vancouver:

Roca Pérez A. Floorplan-Aware High Performance NoC Design . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2012. [cited 2020 May 31]. Available from: http://hdl.handle.net/10251/17844.

Council of Science Editors:

Roca Pérez A. Floorplan-Aware High Performance NoC Design . [Doctoral Dissertation]. Universitat Politècnica de València; 2012. Available from: http://hdl.handle.net/10251/17844

17. Bruno Cruz de Oliveira. Simulação de reservatórios de petróleo em ambiente MPSoC.

Degree: 2009, Universidade Federal do Rio Grande do Norte

 O constante aumento da complexidade das aplicações demanda um suporte de hardware computacionalmente mais poderoso. Com a aproximação do limite de velocidade dos processadores, a… (more)

Subjects/Keywords: Modelos de memória; Simulação de reservatórios; SISTEMAS DE COMPUTACAO; Multiprocessor system-on-chip; Network-on-chip; Sistemas-em-chip multiprocessados; Redes-em-chip; Memory models; Reservoir simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, B. C. d. (2009). Simulação de reservatórios de petróleo em ambiente MPSoC. (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=2706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Bruno Cruz de. “Simulação de reservatórios de petróleo em ambiente MPSoC.” 2009. Thesis, Universidade Federal do Rio Grande do Norte. Accessed May 31, 2020. http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=2706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Bruno Cruz de. “Simulação de reservatórios de petróleo em ambiente MPSoC.” 2009. Web. 31 May 2020.

Vancouver:

Oliveira BCd. Simulação de reservatórios de petróleo em ambiente MPSoC. [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2009. [cited 2020 May 31]. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=2706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira BCd. Simulação de reservatórios de petróleo em ambiente MPSoC. [Thesis]. Universidade Federal do Rio Grande do Norte; 2009. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=2706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

18. Oliveira, Bruno Cruz de. Simulação de reservatórios de petróleo em ambiente MPSoC .

Degree: 2009, Universidade do Rio Grande do Norte

 The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit,… (more)

Subjects/Keywords: Sistemas-em-chip multiprocessados; Redes-em-chip; Modelos de memória; Simulação de reservatórios; Multiprocessor system-on-chip; Network-on-chip; Memory models; Reservoir simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, B. C. d. (2009). Simulação de reservatórios de petróleo em ambiente MPSoC . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17996

Chicago Manual of Style (16th Edition):

Oliveira, Bruno Cruz de. “Simulação de reservatórios de petróleo em ambiente MPSoC .” 2009. Masters Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17996.

MLA Handbook (7th Edition):

Oliveira, Bruno Cruz de. “Simulação de reservatórios de petróleo em ambiente MPSoC .” 2009. Web. 31 May 2020.

Vancouver:

Oliveira BCd. Simulação de reservatórios de petróleo em ambiente MPSoC . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2009. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17996.

Council of Science Editors:

Oliveira BCd. Simulação de reservatórios de petróleo em ambiente MPSoC . [Masters Thesis]. Universidade do Rio Grande do Norte; 2009. Available from: http://repositorio.ufrn.br/handle/123456789/17996


Universidade do Rio Grande do Norte

19. Oliveira, Bruno Cruz de. Simulação de reservatórios de petróleo em ambiente MPSoC .

Degree: 2009, Universidade do Rio Grande do Norte

 The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit,… (more)

Subjects/Keywords: Sistemas-em-chip multiprocessados; Redes-em-chip; Modelos de memória; Simulação de reservatórios; Multiprocessor system-on-chip; Network-on-chip; Memory models; Reservoir simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, B. C. d. (2009). Simulação de reservatórios de petróleo em ambiente MPSoC . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17996

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Bruno Cruz de. “Simulação de reservatórios de petróleo em ambiente MPSoC .” 2009. Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17996.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Bruno Cruz de. “Simulação de reservatórios de petróleo em ambiente MPSoC .” 2009. Web. 31 May 2020.

Vancouver:

Oliveira BCd. Simulação de reservatórios de petróleo em ambiente MPSoC . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2009. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17996.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira BCd. Simulação de reservatórios de petróleo em ambiente MPSoC . [Thesis]. Universidade do Rio Grande do Norte; 2009. Available from: http://repositorio.ufrn.br/handle/123456789/17996

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

20. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Thesis, Texas A&M University. Accessed May 31, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 31 May 2020.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 May 31]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

21. Escudero Martínez, M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.

Degree: 2010, Delft University of Technology

 Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new… (more)

Subjects/Keywords: network on chip; NoC; system on chip; SoC; bridge; FPGA; prototyping

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APA (6th Edition):

Escudero Martínez, M. (2010). An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847

Chicago Manual of Style (16th Edition):

Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Masters Thesis, Delft University of Technology. Accessed May 31, 2020. http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.

MLA Handbook (7th Edition):

Escudero Martínez, M. “An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:.” 2010. Web. 31 May 2020.

Vancouver:

Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 May 31]. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847.

Council of Science Editors:

Escudero Martínez M. An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:c9772109-7e5e-4858-8c10-6c880cbbf847


University of Toronto

22. Hesse, Robert. Fine-grained Adaptivity for Dynamic On-chip Networks.

Degree: PhD, 2016, University of Toronto

 A key challenge of building chip multiprocessors (CMPs) is providing an efficient communication infrastructure for their increasing communication demands. Networks-on-Chip (NoCs) offer a scalable, high-bandwidth,… (more)

Subjects/Keywords: chip multiprocessor; computer architecture; many-core; Network-on-Chip; NoC; 0464

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APA (6th Edition):

Hesse, R. (2016). Fine-grained Adaptivity for Dynamic On-chip Networks. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/73014

Chicago Manual of Style (16th Edition):

Hesse, Robert. “Fine-grained Adaptivity for Dynamic On-chip Networks.” 2016. Doctoral Dissertation, University of Toronto. Accessed May 31, 2020. http://hdl.handle.net/1807/73014.

MLA Handbook (7th Edition):

Hesse, Robert. “Fine-grained Adaptivity for Dynamic On-chip Networks.” 2016. Web. 31 May 2020.

Vancouver:

Hesse R. Fine-grained Adaptivity for Dynamic On-chip Networks. [Internet] [Doctoral dissertation]. University of Toronto; 2016. [cited 2020 May 31]. Available from: http://hdl.handle.net/1807/73014.

Council of Science Editors:

Hesse R. Fine-grained Adaptivity for Dynamic On-chip Networks. [Doctoral Dissertation]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/73014

23. Douglas Rossi de Melo. Extensible communication interface to SoCIN network-on-chip.

Degree: 2012, Universidade do Vale do Itajaí

Os avanços tecnológicos têm permitido o desenvolvimento de sistemas integrados com nível acentuado de complexidade e com requisitos diferenciados em relação aos sistemas atuais, como,… (more)

Subjects/Keywords: Serviços de Comunicação; Redes-em-Chip; Interfaces de Rede; CIENCIA DA COMPUTACAO; Interfaces (Computadores); Communication Services; Networks-on-Chip; Network Interfaces

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APA (6th Edition):

Melo, D. R. d. (2012). Extensible communication interface to SoCIN network-on-chip. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1134

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Melo, Douglas Rossi de. “Extensible communication interface to SoCIN network-on-chip.” 2012. Thesis, Universidade do Vale do Itajaí. Accessed May 31, 2020. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1134.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Melo, Douglas Rossi de. “Extensible communication interface to SoCIN network-on-chip.” 2012. Web. 31 May 2020.

Vancouver:

Melo DRd. Extensible communication interface to SoCIN network-on-chip. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2012. [cited 2020 May 31]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1134.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Melo DRd. Extensible communication interface to SoCIN network-on-chip. [Thesis]. Universidade do Vale do Itajaí; 2012. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1134

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

24. Mishra, Asit Kumar. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors.

Degree: PhD, Computer Science and Engineering, 2011, Penn State University

 Rarely has there been as challenging and exciting a time for research in computer architecture as now. While, the proverbial Moore’s law has consistently helped… (more)

Subjects/Keywords: NoC; network-on-chip; router; heterogeneous NoC; heterogeneous networks; multicore; CMP; STT-RAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mishra, A. K. (2011). Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/11995

Chicago Manual of Style (16th Edition):

Mishra, Asit Kumar. “Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors.” 2011. Doctoral Dissertation, Penn State University. Accessed May 31, 2020. https://etda.libraries.psu.edu/catalog/11995.

MLA Handbook (7th Edition):

Mishra, Asit Kumar. “Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors.” 2011. Web. 31 May 2020.

Vancouver:

Mishra AK. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2020 May 31]. Available from: https://etda.libraries.psu.edu/catalog/11995.

Council of Science Editors:

Mishra AK. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/11995

25. Thiago Felski Pereira. Mecanismos para provimento de tolerância a faltas em uma rede-em-chip.

Degree: 2012, Universidade do Vale do Itajaí

The constant reduction in the size of components of integrated circuits, as well as the growing operating frequency, increases the vulnerability to internal and external… (more)

Subjects/Keywords: Redes-em-Chip; Tolerância a Faltas; Modelo de Erro; CIENCIA DA COMPUTACAO; Redes de computação; Networks-on-Chip; Fault Tolerance; Error Model

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APA (6th Edition):

Pereira, T. F. (2012). Mecanismos para provimento de tolerância a faltas em uma rede-em-chip. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1185

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pereira, Thiago Felski. “Mecanismos para provimento de tolerância a faltas em uma rede-em-chip.” 2012. Thesis, Universidade do Vale do Itajaí. Accessed May 31, 2020. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1185.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pereira, Thiago Felski. “Mecanismos para provimento de tolerância a faltas em uma rede-em-chip.” 2012. Web. 31 May 2020.

Vancouver:

Pereira TF. Mecanismos para provimento de tolerância a faltas em uma rede-em-chip. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2012. [cited 2020 May 31]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1185.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pereira TF. Mecanismos para provimento de tolerância a faltas em uma rede-em-chip. [Thesis]. Universidade do Vale do Itajaí; 2012. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=1185

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

26. Ahmad, Balal. Communication centric platforms for future high data intensive applications.

Degree: 2009, University of Edinburgh

 The notion of platform based design is considered as a viable solution to boost the design productivity by favouring reuse design methodology. With the scaling… (more)

Subjects/Keywords: 621.3; network-on-chip; NoC; dynamically reconfigurable NoC; On-chip communication; hybrid communication medium; communication centric platforms; SOCCAD tool

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmad, B. (2009). Communication centric platforms for future high data intensive applications. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/3814

Chicago Manual of Style (16th Edition):

Ahmad, Balal. “Communication centric platforms for future high data intensive applications.” 2009. Doctoral Dissertation, University of Edinburgh. Accessed May 31, 2020. http://hdl.handle.net/1842/3814.

MLA Handbook (7th Edition):

Ahmad, Balal. “Communication centric platforms for future high data intensive applications.” 2009. Web. 31 May 2020.

Vancouver:

Ahmad B. Communication centric platforms for future high data intensive applications. [Internet] [Doctoral dissertation]. University of Edinburgh; 2009. [cited 2020 May 31]. Available from: http://hdl.handle.net/1842/3814.

Council of Science Editors:

Ahmad B. Communication centric platforms for future high data intensive applications. [Doctoral Dissertation]. University of Edinburgh; 2009. Available from: http://hdl.handle.net/1842/3814

27. SILVEIRA, Maria Cireno Ribeiro. Algoritmo de prefetching de dados temporizado para sistemas multiprocessadores baseados em NOC .

Degree: 2015, Universidade Federal de Pernambuco

 O prefetching é uma técnica considerada e ciente para mitigar um problema já conhecido em sistemas computacionais: a diferença entre o desempenho do processador e… (more)

Subjects/Keywords: Multiprocessador; Manycore; Prefetching; NoC - Network-on-Chip; Coerência de cache; Multiprocessor; Manycore; Prefetching; NoC - Network-on-Chip; Cache coherence

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APA (6th Edition):

SILVEIRA, M. C. R. (2015). Algoritmo de prefetching de dados temporizado para sistemas multiprocessadores baseados em NOC . (Masters Thesis). Universidade Federal de Pernambuco. Retrieved from https://repositorio.ufpe.br/handle/123456789/15963

Chicago Manual of Style (16th Edition):

SILVEIRA, Maria Cireno Ribeiro. “Algoritmo de prefetching de dados temporizado para sistemas multiprocessadores baseados em NOC .” 2015. Masters Thesis, Universidade Federal de Pernambuco. Accessed May 31, 2020. https://repositorio.ufpe.br/handle/123456789/15963.

MLA Handbook (7th Edition):

SILVEIRA, Maria Cireno Ribeiro. “Algoritmo de prefetching de dados temporizado para sistemas multiprocessadores baseados em NOC .” 2015. Web. 31 May 2020.

Vancouver:

SILVEIRA MCR. Algoritmo de prefetching de dados temporizado para sistemas multiprocessadores baseados em NOC . [Internet] [Masters thesis]. Universidade Federal de Pernambuco; 2015. [cited 2020 May 31]. Available from: https://repositorio.ufpe.br/handle/123456789/15963.

Council of Science Editors:

SILVEIRA MCR. Algoritmo de prefetching de dados temporizado para sistemas multiprocessadores baseados em NOC . [Masters Thesis]. Universidade Federal de Pernambuco; 2015. Available from: https://repositorio.ufpe.br/handle/123456789/15963


Indian Institute of Science

28. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: 2013, Indian Institute of Science

 Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basavaraj, T. (2013). NoC Design & Optimization of Multicore Media Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Thesis, Indian Institute of Science. Accessed May 31, 2020. http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Web. 31 May 2020.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 May 31]. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

29. [No author]. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .

Degree: 2017, Washington State University

 In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and… (more)

Subjects/Keywords: Computer engineering; Big Data; Graph Analytics; MapReduce; Network-on-Chip; System-on-Chip; Wireless NoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2017). COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Thesis, Washington State University. Accessed May 31, 2020. http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING .” 2017. Web. 31 May 2020.

Vancouver:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Internet] [Thesis]. Washington State University; 2017. [cited 2020 May 31]. Available from: http://hdl.handle.net/2376/13038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING . [Thesis]. Washington State University; 2017. Available from: http://hdl.handle.net/2376/13038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

30. Zhao, Hui. Improving The Reliability And Power-efficiency.

Degree: PhD, Computer Science and Engineering, 2014, Penn State University

 In recent years, many-core multiprocessors have become the focus of attention in computer architecture design. Designers are permitted by Moore’s Law to integrate a large… (more)

Subjects/Keywords: Chip Multiprocessors; reliability; power efficiency; program scalability; NoC design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, H. (2014). Improving The Reliability And Power-efficiency. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/23335

Chicago Manual of Style (16th Edition):

Zhao, Hui. “Improving The Reliability And Power-efficiency.” 2014. Doctoral Dissertation, Penn State University. Accessed May 31, 2020. https://etda.libraries.psu.edu/catalog/23335.

MLA Handbook (7th Edition):

Zhao, Hui. “Improving The Reliability And Power-efficiency.” 2014. Web. 31 May 2020.

Vancouver:

Zhao H. Improving The Reliability And Power-efficiency. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2020 May 31]. Available from: https://etda.libraries.psu.edu/catalog/23335.

Council of Science Editors:

Zhao H. Improving The Reliability And Power-efficiency. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/23335

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