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You searched for subject:( PVT variation). Showing records 1 – 6 of 6 total matches.

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1. Tang, Aoxiang. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .

Degree: PhD, 2015, Princeton University

 Technology scaling has been one of the most fundamental ways to improve chip performance and reduce power consumption. However, as the industry dives deeper into… (more)

Subjects/Keywords: delay modeling; FinFET; genetic algorithm; power modeling; PVT variation; SSTA

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APA (6th Edition):

Tang, A. (2015). Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01z890rw568

Chicago Manual of Style (16th Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Doctoral Dissertation, Princeton University. Accessed April 04, 2020. http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

MLA Handbook (7th Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Web. 04 Apr 2020.

Vancouver:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Internet] [Doctoral dissertation]. Princeton University; 2015. [cited 2020 Apr 04]. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

Council of Science Editors:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Doctoral Dissertation]. Princeton University; 2015. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568


Princeton University

2. Chen, Xianmin. FinFET-based System Modeling and Low-Power System Design .

Degree: PhD, 2016, Princeton University

 FinFET has begun to replace MOSFET at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has higher on-current and lower leakage due… (more)

Subjects/Keywords: 3D IC; FinFET; Low-power; NoC; PVT variation; System modeling

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APA (6th Edition):

Chen, X. (2016). FinFET-based System Modeling and Low-Power System Design . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp016t053j389

Chicago Manual of Style (16th Edition):

Chen, Xianmin. “FinFET-based System Modeling and Low-Power System Design .” 2016. Doctoral Dissertation, Princeton University. Accessed April 04, 2020. http://arks.princeton.edu/ark:/88435/dsp016t053j389.

MLA Handbook (7th Edition):

Chen, Xianmin. “FinFET-based System Modeling and Low-Power System Design .” 2016. Web. 04 Apr 2020.

Vancouver:

Chen X. FinFET-based System Modeling and Low-Power System Design . [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2020 Apr 04]. Available from: http://arks.princeton.edu/ark:/88435/dsp016t053j389.

Council of Science Editors:

Chen X. FinFET-based System Modeling and Low-Power System Design . [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp016t053j389


Delft University of Technology

3. Nigam, A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.

Degree: 2010, Delft University of Technology

 As we are moving toward nanometre technology, the variability in the circuit parameters and operating environment (Process, Voltage and Temperature (PVT)) are increasing, causing uncertainty… (more)

Subjects/Keywords: STA; SSTA; digital circuit; timing analysis; EDA; PVT; variation; Monte Carlo; 45nm; methodology; simulation; MODERN

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APA (6th Edition):

Nigam, A. (2010). Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78

Chicago Manual of Style (16th Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Masters Thesis, Delft University of Technology. Accessed April 04, 2020. http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

MLA Handbook (7th Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Web. 04 Apr 2020.

Vancouver:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Apr 04]. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

Council of Science Editors:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78


Rice University

4. Kirolos, Sami M. PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits.

Degree: PhD, Engineering, 2008, Rice University

 Over the last few years, considerable variability in deep submicron integrated circuits has become a major concern for designers since the actual performance can vary… (more)

Subjects/Keywords: Electrical engineering; Applied sciences; Adaptive circuits; Integrated circuits; PVT variation; Robust circuits

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APA (6th Edition):

Kirolos, S. M. (2008). PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/103550

Chicago Manual of Style (16th Edition):

Kirolos, Sami M. “PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits.” 2008. Doctoral Dissertation, Rice University. Accessed April 04, 2020. http://hdl.handle.net/1911/103550.

MLA Handbook (7th Edition):

Kirolos, Sami M. “PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits.” 2008. Web. 04 Apr 2020.

Vancouver:

Kirolos SM. PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits. [Internet] [Doctoral dissertation]. Rice University; 2008. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1911/103550.

Council of Science Editors:

Kirolos SM. PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits. [Doctoral Dissertation]. Rice University; 2008. Available from: http://hdl.handle.net/1911/103550


Northeastern University

5. Choi, Yongsuk. High speed DRAM transceiver design for low voltage applications with process and temperature variation-aware calibration.

Degree: PhD, Department of Electrical and Computer Engineering, 2016, Northeastern University

 Scaling down of integrated circuits (ICs) enables continuous improvement of the operation frequency on many processor and memory capacity. On the contrary, bus performance and… (more)

Subjects/Keywords: DRAM; high-speed; low voltage; PVT calibration; transceiver design; variation-aware design; Radio; Transmitter-receivers; Design and construction; Radio; Transmitter-receivers; Effect of temperature on; Impedance (Electricity); Dynamic random access memory; Calibration; Signal processing; Low voltage systems

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APA (6th Edition):

Choi, Y. (2016). High speed DRAM transceiver design for low voltage applications with process and temperature variation-aware calibration. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20236967

Chicago Manual of Style (16th Edition):

Choi, Yongsuk. “High speed DRAM transceiver design for low voltage applications with process and temperature variation-aware calibration.” 2016. Doctoral Dissertation, Northeastern University. Accessed April 04, 2020. http://hdl.handle.net/2047/D20236967.

MLA Handbook (7th Edition):

Choi, Yongsuk. “High speed DRAM transceiver design for low voltage applications with process and temperature variation-aware calibration.” 2016. Web. 04 Apr 2020.

Vancouver:

Choi Y. High speed DRAM transceiver design for low voltage applications with process and temperature variation-aware calibration. [Internet] [Doctoral dissertation]. Northeastern University; 2016. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2047/D20236967.

Council of Science Editors:

Choi Y. High speed DRAM transceiver design for low voltage applications with process and temperature variation-aware calibration. [Doctoral Dissertation]. Northeastern University; 2016. Available from: http://hdl.handle.net/2047/D20236967


University of New Mexico

6. Uzzal, Mohammad. Avalanche ISFET Sensing Chip for DNA Sequencing.

Degree: Electrical and Computer Engineering, 2016, University of New Mexico

  DNA sequencing is a fundamental tool for biological science, aimed primarily at uncovering the genetic contributions to diseases. The first Human DNA sequence, which… (more)

Subjects/Keywords: Avalanche ISFET (A-ISFET); Readout Circuits; pH-to-Current Sensitivity; Avalanche Breakdown; Genome Sequencing; PVT variation; Signal-to-Noise Ratio (SNR); Multiplication Factor; Excess Noise Factor; Avalanche region of operation; ion sensitive field effect transistor; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Uzzal, M. (2016). Avalanche ISFET Sensing Chip for DNA Sequencing. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/33056

Chicago Manual of Style (16th Edition):

Uzzal, Mohammad. “Avalanche ISFET Sensing Chip for DNA Sequencing.” 2016. Doctoral Dissertation, University of New Mexico. Accessed April 04, 2020. http://hdl.handle.net/1928/33056.

MLA Handbook (7th Edition):

Uzzal, Mohammad. “Avalanche ISFET Sensing Chip for DNA Sequencing.” 2016. Web. 04 Apr 2020.

Vancouver:

Uzzal M. Avalanche ISFET Sensing Chip for DNA Sequencing. [Internet] [Doctoral dissertation]. University of New Mexico; 2016. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1928/33056.

Council of Science Editors:

Uzzal M. Avalanche ISFET Sensing Chip for DNA Sequencing. [Doctoral Dissertation]. University of New Mexico; 2016. Available from: http://hdl.handle.net/1928/33056

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