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You searched for subject:( Integrated circuits Large scale integration Data processing ). Showing records 1 – 30 of 80339 total matches.

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Oregon State University

1. Ruggeri, Thomas L. TIMR : Time Interleaved Multi Rail.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration

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APA (6th Edition):

Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070

Chicago Manual of Style (16th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed January 18, 2020. http://hdl.handle.net/1957/29070.

MLA Handbook (7th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 18 Jan 2020.

Vancouver:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1957/29070.

Council of Science Editors:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070


University of Arizona

2. Guarini, Marcello W. NUMERICAL INTEGRATION OF DYNAMIC SYSTEMS VIA WAVEFORM RELAXATION TECHNIQUES; IMPLEMENTATION AND TESTING.

Degree: 1983, University of Arizona

Subjects/Keywords: Dynamics  – Mathematical models  – Data processing.; Integrated circuits  – Large scale integration.; Integrated circuits  – Large scale integration  – Data processing.

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APA (6th Edition):

Guarini, M. W. (1983). NUMERICAL INTEGRATION OF DYNAMIC SYSTEMS VIA WAVEFORM RELAXATION TECHNIQUES; IMPLEMENTATION AND TESTING. (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/274839

Chicago Manual of Style (16th Edition):

Guarini, Marcello W. “NUMERICAL INTEGRATION OF DYNAMIC SYSTEMS VIA WAVEFORM RELAXATION TECHNIQUES; IMPLEMENTATION AND TESTING. ” 1983. Masters Thesis, University of Arizona. Accessed January 18, 2020. http://hdl.handle.net/10150/274839.

MLA Handbook (7th Edition):

Guarini, Marcello W. “NUMERICAL INTEGRATION OF DYNAMIC SYSTEMS VIA WAVEFORM RELAXATION TECHNIQUES; IMPLEMENTATION AND TESTING. ” 1983. Web. 18 Jan 2020.

Vancouver:

Guarini MW. NUMERICAL INTEGRATION OF DYNAMIC SYSTEMS VIA WAVEFORM RELAXATION TECHNIQUES; IMPLEMENTATION AND TESTING. [Internet] [Masters thesis]. University of Arizona; 1983. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10150/274839.

Council of Science Editors:

Guarini MW. NUMERICAL INTEGRATION OF DYNAMIC SYSTEMS VIA WAVEFORM RELAXATION TECHNIQUES; IMPLEMENTATION AND TESTING. [Masters Thesis]. University of Arizona; 1983. Available from: http://hdl.handle.net/10150/274839


University of Hong Kong

3. Lei, Chi-un. VLSI macromodeling and signal integrity analysis via digital signal processing techniques.

Degree: PhD, 2011, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Doctoral

Doctor of Philosophy

Advisors/Committee Members: Wong, N, Ng, TS.

Subjects/Keywords: Signal processing - Digital techniques.; Integrated circuits - Very large scale integration - Mathematicalmodels.; Signal integrity (Electronics)

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APA (6th Edition):

Lei, C. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Doctoral Dissertation). University of Hong Kong. Retrieved from Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220

Chicago Manual of Style (16th Edition):

Lei, Chi-un. “VLSI macromodeling and signal integrity analysis via digital signal processing techniques.” 2011. Doctoral Dissertation, University of Hong Kong. Accessed January 18, 2020. Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220.

MLA Handbook (7th Edition):

Lei, Chi-un. “VLSI macromodeling and signal integrity analysis via digital signal processing techniques.” 2011. Web. 18 Jan 2020.

Vancouver:

Lei C. VLSI macromodeling and signal integrity analysis via digital signal processing techniques. [Internet] [Doctoral dissertation]. University of Hong Kong; 2011. [cited 2020 Jan 18]. Available from: Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220.

Council of Science Editors:

Lei C. VLSI macromodeling and signal integrity analysis via digital signal processing techniques. [Doctoral Dissertation]. University of Hong Kong; 2011. Available from: Lei, C. [李志遠]. (2011). VLSI macromodeling and signal integrity analysis via digital signal processing techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4570058 ; http://dx.doi.org/10.5353/th_b4570058 ; http://hdl.handle.net/10722/133220


McGill University

4. Ivanov, André. Dynamic testibility measures and their use in ATPG.

Degree: M. Eng., Department of Electrical Engineering., 1985, McGill University

Subjects/Keywords: Integrated circuits  – Design and construction  – Data processing.; Integrated circuits  – Testing.; Integrated circuits  – Very large scale integration  – Design and construction.; Integrated circuits  – Very large scale integration  – Testing.

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APA (6th Edition):

Ivanov, A. (1985). Dynamic testibility measures and their use in ATPG. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile63324.pdf

Chicago Manual of Style (16th Edition):

Ivanov, André. “Dynamic testibility measures and their use in ATPG.” 1985. Masters Thesis, McGill University. Accessed January 18, 2020. http://digitool.library.mcgill.ca/thesisfile63324.pdf.

MLA Handbook (7th Edition):

Ivanov, André. “Dynamic testibility measures and their use in ATPG.” 1985. Web. 18 Jan 2020.

Vancouver:

Ivanov A. Dynamic testibility measures and their use in ATPG. [Internet] [Masters thesis]. McGill University; 1985. [cited 2020 Jan 18]. Available from: http://digitool.library.mcgill.ca/thesisfile63324.pdf.

Council of Science Editors:

Ivanov A. Dynamic testibility measures and their use in ATPG. [Masters Thesis]. McGill University; 1985. Available from: http://digitool.library.mcgill.ca/thesisfile63324.pdf


Texas A&M University

5. Ledford, Gordon Lee. A restructurable logic simulator.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Integrated circuits - Very large scale integration - Mathematical models.; Integrated circuits - Very large scale integration - Data processing.

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APA (6th Edition):

Ledford, G. L. (2012). A restructurable logic simulator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-L472

Chicago Manual of Style (16th Edition):

Ledford, Gordon Lee. “A restructurable logic simulator.” 2012. Masters Thesis, Texas A&M University. Accessed January 18, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-L472.

MLA Handbook (7th Edition):

Ledford, Gordon Lee. “A restructurable logic simulator.” 2012. Web. 18 Jan 2020.

Vancouver:

Ledford GL. A restructurable logic simulator. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-L472.

Council of Science Editors:

Ledford GL. A restructurable logic simulator. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-L472


University of Victoria

6. Sunder, Sreenivasachar. VLSI implementation of digital filters.

Degree: Department of Electrical and Computer Engineering, 2018, University of Victoria

 In this thesis we describe a method of mapping one-dimensional and multidimensional filter algorithms onto systolic architectures using the z-domain approach. In this approach the… (more)

Subjects/Keywords: Integrated circuits, very large scale integration; Parallel processing (Electronic computers); Digital filters (Mathematics); Signal processing, digital techniques

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APA (6th Edition):

Sunder, S. (2018). VLSI implementation of digital filters. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/9571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sunder, Sreenivasachar. “VLSI implementation of digital filters.” 2018. Thesis, University of Victoria. Accessed January 18, 2020. https://dspace.library.uvic.ca//handle/1828/9571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sunder, Sreenivasachar. “VLSI implementation of digital filters.” 2018. Web. 18 Jan 2020.

Vancouver:

Sunder S. VLSI implementation of digital filters. [Internet] [Thesis]. University of Victoria; 2018. [cited 2020 Jan 18]. Available from: https://dspace.library.uvic.ca//handle/1828/9571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sunder S. VLSI implementation of digital filters. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/9571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

7. Harwood, Ann Elizabeth Gelber. A VSLI design rule check program generator.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Integrated circuits - Very large scale integration - Data processing.; Integrated circuits - Design and construction - Data processing.

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APA (6th Edition):

Harwood, A. E. G. (2012). A VSLI design rule check program generator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-H343

Chicago Manual of Style (16th Edition):

Harwood, Ann Elizabeth Gelber. “A VSLI design rule check program generator.” 2012. Masters Thesis, Texas A&M University. Accessed January 18, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-H343.

MLA Handbook (7th Edition):

Harwood, Ann Elizabeth Gelber. “A VSLI design rule check program generator.” 2012. Web. 18 Jan 2020.

Vancouver:

Harwood AEG. A VSLI design rule check program generator. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-H343.

Council of Science Editors:

Harwood AEG. A VSLI design rule check program generator. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-H343


McGill University

8. Somani, Arun K. (Arun Kumar). Unsorted VLSI dictionary machines.

Degree: M. Eng., Department of Electrical Engineering., 1983, McGill University

Subjects/Keywords: Integrated circuits  – Very large scale integration.; Data dictionaries.; Algorithms.

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APA (6th Edition):

Somani, A. K. (. K. (1983). Unsorted VLSI dictionary machines. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile64569.pdf

Chicago Manual of Style (16th Edition):

Somani, Arun K (Arun Kumar). “Unsorted VLSI dictionary machines.” 1983. Masters Thesis, McGill University. Accessed January 18, 2020. http://digitool.library.mcgill.ca/thesisfile64569.pdf.

MLA Handbook (7th Edition):

Somani, Arun K (Arun Kumar). “Unsorted VLSI dictionary machines.” 1983. Web. 18 Jan 2020.

Vancouver:

Somani AK(K. Unsorted VLSI dictionary machines. [Internet] [Masters thesis]. McGill University; 1983. [cited 2020 Jan 18]. Available from: http://digitool.library.mcgill.ca/thesisfile64569.pdf.

Council of Science Editors:

Somani AK(K. Unsorted VLSI dictionary machines. [Masters Thesis]. McGill University; 1983. Available from: http://digitool.library.mcgill.ca/thesisfile64569.pdf


Massey University

9. Ahmad, Nabihah Nornabihah. Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology.

Degree: PhD, Engineering, 2013, Massey University

 Implementations of the Advanced Encryption Standard (AES) have rapidly grown in various applications including telecommunications, finance and networks that require a low power consumption and… (more)

Subjects/Keywords: Advanced Encryption Standard (AES); Data encryption; Integrated circuits; Very large scale integration (VLSI); CMOS; Crypto-processor; Power consumption (Computing); Computer algorithms

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APA (6th Edition):

Ahmad, N. N. (2013). Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology. (Doctoral Dissertation). Massey University. Retrieved from http://hdl.handle.net/10179/5308

Chicago Manual of Style (16th Edition):

Ahmad, Nabihah Nornabihah. “Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology.” 2013. Doctoral Dissertation, Massey University. Accessed January 18, 2020. http://hdl.handle.net/10179/5308.

MLA Handbook (7th Edition):

Ahmad, Nabihah Nornabihah. “Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology.” 2013. Web. 18 Jan 2020.

Vancouver:

Ahmad NN. Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology. [Internet] [Doctoral dissertation]. Massey University; 2013. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10179/5308.

Council of Science Editors:

Ahmad NN. Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology. [Doctoral Dissertation]. Massey University; 2013. Available from: http://hdl.handle.net/10179/5308


University of Hong Kong

10. Zhang, Zheng. Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation.

Degree: M. Phil., 2010, University of Hong Kong

The Best MPhil Thesis in the Faculties of Dentistry, Engineering, Medicine and Science (University of Hong Kong), Li Ka Shing Prize,2009-2010

published_or_final_version

Electrical and Electronic Engineering

Master

Master of Philosophy

Advisors/Committee Members: Wong, N.

Subjects/Keywords: Linear time invariant systems.; Integrated circuits - Very large scale integration - Computersimulation.

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APA (6th Edition):

Zhang, Z. (2010). Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. (Masters Thesis). University of Hong Kong. Retrieved from Zhang, Z. [张政]. (2010). Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490905 ; http://dx.doi.org/10.5353/th_b4490905 ; http://hdl.handle.net/10722/130767

Chicago Manual of Style (16th Edition):

Zhang, Zheng. “Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation.” 2010. Masters Thesis, University of Hong Kong. Accessed January 18, 2020. Zhang, Z. [张政]. (2010). Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490905 ; http://dx.doi.org/10.5353/th_b4490905 ; http://hdl.handle.net/10722/130767.

MLA Handbook (7th Edition):

Zhang, Zheng. “Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation.” 2010. Web. 18 Jan 2020.

Vancouver:

Zhang Z. Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. [Internet] [Masters thesis]. University of Hong Kong; 2010. [cited 2020 Jan 18]. Available from: Zhang, Z. [张政]. (2010). Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490905 ; http://dx.doi.org/10.5353/th_b4490905 ; http://hdl.handle.net/10722/130767.

Council of Science Editors:

Zhang Z. Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. [Masters Thesis]. University of Hong Kong; 2010. Available from: Zhang, Z. [张政]. (2010). Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490905 ; http://dx.doi.org/10.5353/th_b4490905 ; http://hdl.handle.net/10722/130767


University of Hong Kong

11. 趙文慧; Zhao, Wenhui. Efficient circuit simulation via adaptive moment matching and matrix exponential techniques.

Degree: M. Phil., 2013, University of Hong Kong

This dissertation presents two efficient circuit simulation techniques for very large scale integrated (VLSI) circuits. Model order reduction (MOR) plays a significant role in VLSI… (more)

Subjects/Keywords: Integrated circuits - Very large scale integration - Computer simulation

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APA (6th Edition):

趙文慧; Zhao, W. (2013). Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. (Masters Thesis). University of Hong Kong. Retrieved from Zhao, W. [趙文慧]. (2013). Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5194742 ; http://dx.doi.org/10.5353/th_b5194742 ; http://hdl.handle.net/10722/197488

Chicago Manual of Style (16th Edition):

趙文慧; Zhao, Wenhui. “Efficient circuit simulation via adaptive moment matching and matrix exponential techniques.” 2013. Masters Thesis, University of Hong Kong. Accessed January 18, 2020. Zhao, W. [趙文慧]. (2013). Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5194742 ; http://dx.doi.org/10.5353/th_b5194742 ; http://hdl.handle.net/10722/197488.

MLA Handbook (7th Edition):

趙文慧; Zhao, Wenhui. “Efficient circuit simulation via adaptive moment matching and matrix exponential techniques.” 2013. Web. 18 Jan 2020.

Vancouver:

趙文慧; Zhao W. Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. [Internet] [Masters thesis]. University of Hong Kong; 2013. [cited 2020 Jan 18]. Available from: Zhao, W. [趙文慧]. (2013). Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5194742 ; http://dx.doi.org/10.5353/th_b5194742 ; http://hdl.handle.net/10722/197488.

Council of Science Editors:

趙文慧; Zhao W. Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. [Masters Thesis]. University of Hong Kong; 2013. Available from: Zhao, W. [趙文慧]. (2013). Efficient circuit simulation via adaptive moment matching and matrix exponential techniques. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5194742 ; http://dx.doi.org/10.5353/th_b5194742 ; http://hdl.handle.net/10722/197488


Massey University

12. Alam, Sadia. Modelling, analysis and design of bioelectronic circuits in VLSI.

Degree: PhD, Electronics and Computer Engineering, 2015, Massey University

 Biological phenomena at the molecular level are being imitated by electronic circuits. The immense effectiveness and versatility of bioelectronic circuits have yielded multiple benefits to… (more)

Subjects/Keywords: Integrated circuits; Very large scale integration; Design and construction; Bioelectronics

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APA (6th Edition):

Alam, S. (2015). Modelling, analysis and design of bioelectronic circuits in VLSI. (Doctoral Dissertation). Massey University. Retrieved from http://hdl.handle.net/10179/7731

Chicago Manual of Style (16th Edition):

Alam, Sadia. “Modelling, analysis and design of bioelectronic circuits in VLSI.” 2015. Doctoral Dissertation, Massey University. Accessed January 18, 2020. http://hdl.handle.net/10179/7731.

MLA Handbook (7th Edition):

Alam, Sadia. “Modelling, analysis and design of bioelectronic circuits in VLSI.” 2015. Web. 18 Jan 2020.

Vancouver:

Alam S. Modelling, analysis and design of bioelectronic circuits in VLSI. [Internet] [Doctoral dissertation]. Massey University; 2015. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10179/7731.

Council of Science Editors:

Alam S. Modelling, analysis and design of bioelectronic circuits in VLSI. [Doctoral Dissertation]. Massey University; 2015. Available from: http://hdl.handle.net/10179/7731


Massey University

13. Khurram, Muhammad. VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 .

Degree: 2011, Massey University

 The wide operating bandwidth of the ultra-wideband (UWB) signal leads to new circuit design challenges and methodologies. Similar to any other RF system, the most… (more)

Subjects/Keywords: Integrated circuits; Very large scale integration; Computer-aided design; VLSI; CMOS

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APA (6th Edition):

Khurram, M. (2011). VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 . (Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/3701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khurram, Muhammad. “VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 .” 2011. Thesis, Massey University. Accessed January 18, 2020. http://hdl.handle.net/10179/3701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khurram, Muhammad. “VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 .” 2011. Web. 18 Jan 2020.

Vancouver:

Khurram M. VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 . [Internet] [Thesis]. Massey University; 2011. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10179/3701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khurram M. VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011 . [Thesis]. Massey University; 2011. Available from: http://hdl.handle.net/10179/3701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

14. Kim, Hyungsik. Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI).

Degree: 2018, Columbia University

 Two dimensional (2D) materials have been explosively researched since the discovery of graphene but the applications of 2D materials have been extremely constrained because of… (more)

Subjects/Keywords: Electrical engineering; Graphene; Integrated circuits – Very large scale integration; Materials

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APA (6th Edition):

Kim, H. (2018). Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI). (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8Z33GMR

Chicago Manual of Style (16th Edition):

Kim, Hyungsik. “Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI).” 2018. Doctoral Dissertation, Columbia University. Accessed January 18, 2020. https://doi.org/10.7916/D8Z33GMR.

MLA Handbook (7th Edition):

Kim, Hyungsik. “Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI).” 2018. Web. 18 Jan 2020.

Vancouver:

Kim H. Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI). [Internet] [Doctoral dissertation]. Columbia University; 2018. [cited 2020 Jan 18]. Available from: https://doi.org/10.7916/D8Z33GMR.

Council of Science Editors:

Kim H. Unconventional CVD Graphene and MoO3 Electronics for Very Large Scale Integration (VLSI). [Doctoral Dissertation]. Columbia University; 2018. Available from: https://doi.org/10.7916/D8Z33GMR


Virginia Tech

15. Kim, Kwanghyun. An interactive design rule checker for integrated circuit layout.

Degree: MS, Electrical Engineering, 1985, Virginia Tech

Subjects/Keywords: LD5655.V855 1985.K538; Integrated circuits  – Very large scale integration; Integrated circuits  – Design and construction  – Data processing

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APA (6th Edition):

Kim, K. (1985). An interactive design rule checker for integrated circuit layout. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50034

Chicago Manual of Style (16th Edition):

Kim, Kwanghyun. “An interactive design rule checker for integrated circuit layout.” 1985. Masters Thesis, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/50034.

MLA Handbook (7th Edition):

Kim, Kwanghyun. “An interactive design rule checker for integrated circuit layout.” 1985. Web. 18 Jan 2020.

Vancouver:

Kim K. An interactive design rule checker for integrated circuit layout. [Internet] [Masters thesis]. Virginia Tech; 1985. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/50034.

Council of Science Editors:

Kim K. An interactive design rule checker for integrated circuit layout. [Masters Thesis]. Virginia Tech; 1985. Available from: http://hdl.handle.net/10919/50034


Virginia Tech

16. Kim, Kwanghyun. An expert system for self-testable hardware design.

Degree: PhD, Electrical Engineering, 1989, Virginia Tech

Subjects/Keywords: LD5655.V856 1989.K574; Integrated circuits  – Very large scale integration  – Testing  – Automation; Integrated circuits  – Design and construction  – Data processing

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APA (6th Edition):

Kim, K. (1989). An expert system for self-testable hardware design. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/54216

Chicago Manual of Style (16th Edition):

Kim, Kwanghyun. “An expert system for self-testable hardware design.” 1989. Doctoral Dissertation, Virginia Tech. Accessed January 18, 2020. http://hdl.handle.net/10919/54216.

MLA Handbook (7th Edition):

Kim, Kwanghyun. “An expert system for self-testable hardware design.” 1989. Web. 18 Jan 2020.

Vancouver:

Kim K. An expert system for self-testable hardware design. [Internet] [Doctoral dissertation]. Virginia Tech; 1989. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10919/54216.

Council of Science Editors:

Kim K. An expert system for self-testable hardware design. [Doctoral Dissertation]. Virginia Tech; 1989. Available from: http://hdl.handle.net/10919/54216


Texas A&M University

17. Oh, Chuldong. A modified greedy channel router with net assignment at the left edge.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Integrated circuits - Very large scale integration.; Integrated circuits - Design and construction - Data processing.; Electronic circuit design - Data processing.

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APA (6th Edition):

Oh, C. (2012). A modified greedy channel router with net assignment at the left edge. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-O36

Chicago Manual of Style (16th Edition):

Oh, Chuldong. “A modified greedy channel router with net assignment at the left edge.” 2012. Masters Thesis, Texas A&M University. Accessed January 18, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-O36.

MLA Handbook (7th Edition):

Oh, Chuldong. “A modified greedy channel router with net assignment at the left edge.” 2012. Web. 18 Jan 2020.

Vancouver:

Oh C. A modified greedy channel router with net assignment at the left edge. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-O36.

Council of Science Editors:

Oh C. A modified greedy channel router with net assignment at the left edge. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-O36


Texas A&M University

18. Fernando, M. A. Susith Rohana. A Knowledge Based Digital Control Flow Synthesizer.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Digital integrated circuits - Design and construction - Data processing.; Integrated circuits - Very large scale integration.; Engineering design - Data processing.; Artificial intelligence.

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APA (6th Edition):

Fernando, M. A. S. R. (2012). A Knowledge Based Digital Control Flow Synthesizer. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-F3635

Chicago Manual of Style (16th Edition):

Fernando, M A Susith Rohana. “A Knowledge Based Digital Control Flow Synthesizer.” 2012. Masters Thesis, Texas A&M University. Accessed January 18, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-F3635.

MLA Handbook (7th Edition):

Fernando, M A Susith Rohana. “A Knowledge Based Digital Control Flow Synthesizer.” 2012. Web. 18 Jan 2020.

Vancouver:

Fernando MASR. A Knowledge Based Digital Control Flow Synthesizer. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-F3635.

Council of Science Editors:

Fernando MASR. A Knowledge Based Digital Control Flow Synthesizer. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-F3635


University of Adelaide

19. Tonkin, Bruce A. (Bruce Archibald). A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin.

Degree: 1990, University of Adelaide

Subjects/Keywords: 621.395 20; Integrated circuits  – Design and construction  – Data processing; Integrated circuits  – Very large scale integration  – Design and construction  – Data processing; Computer-aided design

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APA (6th Edition):

Tonkin, B. A. (. A. (1990). A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin. (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/19215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tonkin, Bruce A (Bruce Archibald). “A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin.” 1990. Thesis, University of Adelaide. Accessed January 18, 2020. http://hdl.handle.net/2440/19215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tonkin, Bruce A (Bruce Archibald). “A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin.” 1990. Web. 18 Jan 2020.

Vancouver:

Tonkin BA(A. A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin. [Internet] [Thesis]. University of Adelaide; 1990. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/2440/19215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tonkin BA(A. A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin. [Thesis]. University of Adelaide; 1990. Available from: http://hdl.handle.net/2440/19215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McGill University

20. Hong, Won-kook. Single layer routing : mapping topological to geometric solutions.

Degree: MS, School of Computer Science., 1986, McGill University

Subjects/Keywords: Algorithms.; Integrated circuits  – Large scale integration.; Integrated circuits  – Very large scale integration.

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APA (6th Edition):

Hong, W. (1986). Single layer routing : mapping topological to geometric solutions. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile66030.pdf

Chicago Manual of Style (16th Edition):

Hong, Won-kook. “Single layer routing : mapping topological to geometric solutions.” 1986. Masters Thesis, McGill University. Accessed January 18, 2020. http://digitool.library.mcgill.ca/thesisfile66030.pdf.

MLA Handbook (7th Edition):

Hong, Won-kook. “Single layer routing : mapping topological to geometric solutions.” 1986. Web. 18 Jan 2020.

Vancouver:

Hong W. Single layer routing : mapping topological to geometric solutions. [Internet] [Masters thesis]. McGill University; 1986. [cited 2020 Jan 18]. Available from: http://digitool.library.mcgill.ca/thesisfile66030.pdf.

Council of Science Editors:

Hong W. Single layer routing : mapping topological to geometric solutions. [Masters Thesis]. McGill University; 1986. Available from: http://digitool.library.mcgill.ca/thesisfile66030.pdf


University of Arizona

21. Matsumori, Barry Alan. QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS.

Degree: 1985, University of Arizona

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Reliability.; Integrated circuits  – Large scale integration  – Reliability.

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APA (6th Edition):

Matsumori, B. A. (1985). QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/275313

Chicago Manual of Style (16th Edition):

Matsumori, Barry Alan. “QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. ” 1985. Masters Thesis, University of Arizona. Accessed January 18, 2020. http://hdl.handle.net/10150/275313.

MLA Handbook (7th Edition):

Matsumori, Barry Alan. “QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. ” 1985. Web. 18 Jan 2020.

Vancouver:

Matsumori BA. QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. [Internet] [Masters thesis]. University of Arizona; 1985. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10150/275313.

Council of Science Editors:

Matsumori BA. QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS. [Masters Thesis]. University of Arizona; 1985. Available from: http://hdl.handle.net/10150/275313


Ryerson University

22. Javaheri, Mohammad R.S. Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors.

Degree: 2010, Ryerson University

 Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Testing; Integrated circuits  – Fault tolerance; Fault-tolerant computing; Field programmable gate arrays

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APA (6th Edition):

Javaheri, M. R. S. (2010). Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Javaheri, Mohammad R S. “Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors.” 2010. Thesis, Ryerson University. Accessed January 18, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A1855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Javaheri, Mohammad R S. “Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors.” 2010. Web. 18 Jan 2020.

Vancouver:

Javaheri MRS. Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Jan 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Javaheri MRS. Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

23. Sagahyroon, Assim Abdelrahman. An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits .

Degree: 1989, University of Arizona

 This paper discusses an intelligence driven test system for generation of test sequences for stuck-open faults in CMOS VLSI sequential circuits. The networks in system… (more)

Subjects/Keywords: Integrated circuits  – Large scale integration.; Integrated circuits  – Testing.

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APA (6th Edition):

Sagahyroon, A. A. (1989). An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/184763

Chicago Manual of Style (16th Edition):

Sagahyroon, Assim Abdelrahman. “An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits .” 1989. Doctoral Dissertation, University of Arizona. Accessed January 18, 2020. http://hdl.handle.net/10150/184763.

MLA Handbook (7th Edition):

Sagahyroon, Assim Abdelrahman. “An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits .” 1989. Web. 18 Jan 2020.

Vancouver:

Sagahyroon AA. An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits . [Internet] [Doctoral dissertation]. University of Arizona; 1989. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10150/184763.

Council of Science Editors:

Sagahyroon AA. An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits . [Doctoral Dissertation]. University of Arizona; 1989. Available from: http://hdl.handle.net/10150/184763


Michigan State University

24. Leung, Yu-Ying Jackson. Performance tradeoffs in the hierarchical design of regular VLSI structures.

Degree: PhD, Department of Electrical Engineering and Systems Science, 1986, Michigan State University

Subjects/Keywords: Integrated circuits – Very large scale integration; Integrated circuits

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APA (6th Edition):

Leung, Y. J. (1986). Performance tradeoffs in the hierarchical design of regular VLSI structures. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:35539

Chicago Manual of Style (16th Edition):

Leung, Yu-Ying Jackson. “Performance tradeoffs in the hierarchical design of regular VLSI structures.” 1986. Doctoral Dissertation, Michigan State University. Accessed January 18, 2020. http://etd.lib.msu.edu/islandora/object/etd:35539.

MLA Handbook (7th Edition):

Leung, Yu-Ying Jackson. “Performance tradeoffs in the hierarchical design of regular VLSI structures.” 1986. Web. 18 Jan 2020.

Vancouver:

Leung YJ. Performance tradeoffs in the hierarchical design of regular VLSI structures. [Internet] [Doctoral dissertation]. Michigan State University; 1986. [cited 2020 Jan 18]. Available from: http://etd.lib.msu.edu/islandora/object/etd:35539.

Council of Science Editors:

Leung YJ. Performance tradeoffs in the hierarchical design of regular VLSI structures. [Doctoral Dissertation]. Michigan State University; 1986. Available from: http://etd.lib.msu.edu/islandora/object/etd:35539


Michigan State University

25. Singh, Tej Pal. Testability design of the DKS chip.

Degree: MS, Department of Electrical Engineering, 1988, Michigan State University

Subjects/Keywords: Integrated circuits – Testing; Integrated circuits – Very large scale integration

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APA (6th Edition):

Singh, T. P. (1988). Testability design of the DKS chip. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:20233

Chicago Manual of Style (16th Edition):

Singh, Tej Pal. “Testability design of the DKS chip.” 1988. Masters Thesis, Michigan State University. Accessed January 18, 2020. http://etd.lib.msu.edu/islandora/object/etd:20233.

MLA Handbook (7th Edition):

Singh, Tej Pal. “Testability design of the DKS chip.” 1988. Web. 18 Jan 2020.

Vancouver:

Singh TP. Testability design of the DKS chip. [Internet] [Masters thesis]. Michigan State University; 1988. [cited 2020 Jan 18]. Available from: http://etd.lib.msu.edu/islandora/object/etd:20233.

Council of Science Editors:

Singh TP. Testability design of the DKS chip. [Masters Thesis]. Michigan State University; 1988. Available from: http://etd.lib.msu.edu/islandora/object/etd:20233


Oregon State University

26. Lim, Daniel. VLSI design methodologies and computer tools.

Degree: MS, Electrical and Computer Engineering, 1985, Oregon State University

 The rapid development of semiconductor technology and the increasing complexity of VLSI chips have prompted both the industry and the academic community alike to take… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

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APA (6th Edition):

Lim, D. (1985). VLSI design methodologies and computer tools. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/40378

Chicago Manual of Style (16th Edition):

Lim, Daniel. “VLSI design methodologies and computer tools.” 1985. Masters Thesis, Oregon State University. Accessed January 18, 2020. http://hdl.handle.net/1957/40378.

MLA Handbook (7th Edition):

Lim, Daniel. “VLSI design methodologies and computer tools.” 1985. Web. 18 Jan 2020.

Vancouver:

Lim D. VLSI design methodologies and computer tools. [Internet] [Masters thesis]. Oregon State University; 1985. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1957/40378.

Council of Science Editors:

Lim D. VLSI design methodologies and computer tools. [Masters Thesis]. Oregon State University; 1985. Available from: http://hdl.handle.net/1957/40378


University of Hong Kong

27. 陈全; Chen, Quan. Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation.

Degree: PhD, 2010, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Doctoral

Doctor of Philosophy

Advisors/Committee Members: Wong, N, Ng, TS.

Subjects/Keywords: Electromagnetism - Mathematical Models.; Integrated circuits - Very large scale integration.; Surface roughness - Mathematical models.

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APA (6th Edition):

陈全; Chen, Q. (2010). Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation. (Doctoral Dissertation). University of Hong Kong. Retrieved from Chen, Q. [陈全]. (2010). Efficient high-frequency electromagnetic simulation in VLSI : rough surface effects and electromagnetic-semiconductor coupled simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490494 ; http://dx.doi.org/10.5353/th_b4490494 ; http://hdl.handle.net/10722/130941

Chicago Manual of Style (16th Edition):

陈全; Chen, Quan. “Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation.” 2010. Doctoral Dissertation, University of Hong Kong. Accessed January 18, 2020. Chen, Q. [陈全]. (2010). Efficient high-frequency electromagnetic simulation in VLSI : rough surface effects and electromagnetic-semiconductor coupled simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490494 ; http://dx.doi.org/10.5353/th_b4490494 ; http://hdl.handle.net/10722/130941.

MLA Handbook (7th Edition):

陈全; Chen, Quan. “Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation.” 2010. Web. 18 Jan 2020.

Vancouver:

陈全; Chen Q. Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation. [Internet] [Doctoral dissertation]. University of Hong Kong; 2010. [cited 2020 Jan 18]. Available from: Chen, Q. [陈全]. (2010). Efficient high-frequency electromagnetic simulation in VLSI : rough surface effects and electromagnetic-semiconductor coupled simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490494 ; http://dx.doi.org/10.5353/th_b4490494 ; http://hdl.handle.net/10722/130941.

Council of Science Editors:

陈全; Chen Q. Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation. [Doctoral Dissertation]. University of Hong Kong; 2010. Available from: Chen, Q. [陈全]. (2010). Efficient high-frequency electromagnetic simulation in VLSI : rough surface effects and electromagnetic-semiconductor coupled simulation. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4490494 ; http://dx.doi.org/10.5353/th_b4490494 ; http://hdl.handle.net/10722/130941

28. Gracia nirmala rani D. Analysis and optimization of Floorplanning algorithms for VLSI physical design;.

Degree: Analysis and optimization of Floorplanning algorithms for VLSI physical design, 2015, Anna University

Rapid advances in semiconductor technologies have led to a newlinedramatic increase in the complexity of Very Large Scale Integration VLSI newlinecircuits With fabrication technology entering… (more)

Subjects/Keywords: Computer Aided Design; Integrated Circuits; Non Deterministic Polynomial time; Very Large Scale Integration

Page 1

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APA (6th Edition):

D, G. n. r. (2015). Analysis and optimization of Floorplanning algorithms for VLSI physical design;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/38605

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

D, Gracia nirmala rani. “Analysis and optimization of Floorplanning algorithms for VLSI physical design;.” 2015. Thesis, Anna University. Accessed January 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/38605.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

D, Gracia nirmala rani. “Analysis and optimization of Floorplanning algorithms for VLSI physical design;.” 2015. Web. 18 Jan 2020.

Vancouver:

D Gnr. Analysis and optimization of Floorplanning algorithms for VLSI physical design;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Jan 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38605.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

D Gnr. Analysis and optimization of Floorplanning algorithms for VLSI physical design;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/38605

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

29. Mitra, Sanjay Nirendra. VLSI implementation of a high speed systolic finite field constant multiplier.

Degree: College of Engineering, 1991, Montana State University

Subjects/Keywords: Integrated circuits Very large scale integration.

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APA (6th Edition):

Mitra, S. N. (1991). VLSI implementation of a high speed systolic finite field constant multiplier. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/7141

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mitra, Sanjay Nirendra. “VLSI implementation of a high speed systolic finite field constant multiplier.” 1991. Thesis, Montana State University. Accessed January 18, 2020. https://scholarworks.montana.edu/xmlui/handle/1/7141.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mitra, Sanjay Nirendra. “VLSI implementation of a high speed systolic finite field constant multiplier.” 1991. Web. 18 Jan 2020.

Vancouver:

Mitra SN. VLSI implementation of a high speed systolic finite field constant multiplier. [Internet] [Thesis]. Montana State University; 1991. [cited 2020 Jan 18]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/7141.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mitra SN. VLSI implementation of a high speed systolic finite field constant multiplier. [Thesis]. Montana State University; 1991. Available from: https://scholarworks.montana.edu/xmlui/handle/1/7141

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

30. Zheng, Yue-Peng. Mapping of recursive algorithms onto multi-rate arrays.

Degree: PhD, Electrical and Computer Engineering, 1994, Oregon State University

 In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zheng, Y. (1994). Mapping of recursive algorithms onto multi-rate arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/34997

Chicago Manual of Style (16th Edition):

Zheng, Yue-Peng. “Mapping of recursive algorithms onto multi-rate arrays.” 1994. Doctoral Dissertation, Oregon State University. Accessed January 18, 2020. http://hdl.handle.net/1957/34997.

MLA Handbook (7th Edition):

Zheng, Yue-Peng. “Mapping of recursive algorithms onto multi-rate arrays.” 1994. Web. 18 Jan 2020.

Vancouver:

Zheng Y. Mapping of recursive algorithms onto multi-rate arrays. [Internet] [Doctoral dissertation]. Oregon State University; 1994. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1957/34997.

Council of Science Editors:

Zheng Y. Mapping of recursive algorithms onto multi-rate arrays. [Doctoral Dissertation]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/34997

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