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You searched for subject:( Int gration monolithique BEOL). Showing records 1 – 30 of 57 total matches.

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Université de Sherbrooke

1. Lee Sang, Bruno. Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS .

Degree: 2016, Université de Sherbrooke

 Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais… (more)

Subjects/Keywords: Transistor monoélectronique (SET); CMOS; Intégration 3D monolithique; BEOL; Gravure plasma; Électrolithographie; Nanodamascène; Nanofabrication; Single electron transistor (SET); 3D monolithic integration; Plasma etching; Electrolithography; Nanodamascene

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APA (6th Edition):

Lee Sang, B. (2016). Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/8955

Chicago Manual of Style (16th Edition):

Lee Sang, Bruno. “Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS .” 2016. Doctoral Dissertation, Université de Sherbrooke. Accessed January 19, 2020. http://hdl.handle.net/11143/8955.

MLA Handbook (7th Edition):

Lee Sang, Bruno. “Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS .” 2016. Web. 19 Jan 2020.

Vancouver:

Lee Sang B. Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2016. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/11143/8955.

Council of Science Editors:

Lee Sang B. Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS . [Doctoral Dissertation]. Université de Sherbrooke; 2016. Available from: http://hdl.handle.net/11143/8955


Université de Sherbrooke

2. Labalette, Marina. Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS .

Degree: 2018, Université de Sherbrooke

 Les dispositifs mémoires résistives, notamment ceux à base d’oxyde de commutation OxRRAM, se placent parmi les dispositifs mémoires émergentes les plus attractifs pour remplacer les… (more)

Subjects/Keywords: Filière CMOS; Mémoires résistives OxRRAM; Dispositifs CRS; Intégration monolithique BEOL; Caractérisations en mode QS et pulsé; Architecture mémoire haute densité; Configuration 1T1R; Oxide based resistive memories OxRRAM; CRS dispositive; CMOS BEOL; 3D monolithic integration; DC and pulsed electrical characterization; High density of integration; 1T1R configuration

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APA (6th Edition):

Labalette, M. (2018). Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/12267

Chicago Manual of Style (16th Edition):

Labalette, Marina. “Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS .” 2018. Doctoral Dissertation, Université de Sherbrooke. Accessed January 19, 2020. http://hdl.handle.net/11143/12267.

MLA Handbook (7th Edition):

Labalette, Marina. “Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS .” 2018. Web. 19 Jan 2020.

Vancouver:

Labalette M. Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2018. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/11143/12267.

Council of Science Editors:

Labalette M. Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS . [Doctoral Dissertation]. Université de Sherbrooke; 2018. Available from: http://hdl.handle.net/11143/12267

3. Labalette, Marina. Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line.

Degree: Docteur es, Electronique, électrotechnique et automatique, 2018, Lyon; Université de Sherbrooke (Québec, Canada)

La gestion, la manipulation et le stockage de données sont aujourd’hui de réels challenges. Pour supporter cette réalité, le besoin de technologies mémoires plus efficaces,… (more)

Subjects/Keywords: Electronique; Microélectronique; Mémoires en microélectronique; Filière CMOS; Mémoires résistives OxRRAM; Mémoires resistives complémentaires - CRS; Intégration monolithique BEOL - back end of line; Caractérisation électrique en mode quasi statique - QS; Caractérisation électrique en mode pulsé; Architecture de mémoire haute densité; Configuration 1T1R; Procédé nanodamascène; Electronics; Microelectronics; Memory on Silicon; Oxide based resistive memories OxRRAM; Complementary resistive switching devices - CRS; Cmos beol; 3D monolithic integration; DC and pulsed electrical characterization; High density integration; 1T1R configuration; 621.397 072

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APA (6th Edition):

Labalette, M. (2018). Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line. (Doctoral Dissertation). Lyon; Université de Sherbrooke (Québec, Canada). Retrieved from http://www.theses.fr/2018LYSEI037

Chicago Manual of Style (16th Edition):

Labalette, Marina. “Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line.” 2018. Doctoral Dissertation, Lyon; Université de Sherbrooke (Québec, Canada). Accessed January 19, 2020. http://www.theses.fr/2018LYSEI037.

MLA Handbook (7th Edition):

Labalette, Marina. “Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line.” 2018. Web. 19 Jan 2020.

Vancouver:

Labalette M. Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line. [Internet] [Doctoral dissertation]. Lyon; Université de Sherbrooke (Québec, Canada); 2018. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2018LYSEI037.

Council of Science Editors:

Labalette M. Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line. [Doctoral Dissertation]. Lyon; Université de Sherbrooke (Québec, Canada); 2018. Available from: http://www.theses.fr/2018LYSEI037


Penn State University

4. Bittel, Brad. STUDY OF DEFECT STRUCTURE AND ELECTRICAL TRANSPORT IN.

Degree: PhD, Materials Science and Engineering, 2011, Penn State University

 SiC MOSFETs show great potential for use in high power and high temperature environments. However, the technology is still in its infancy and is limited… (more)

Subjects/Keywords: magnetic resonance; EPR; low-k; BEOL; SiC

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APA (6th Edition):

Bittel, B. (2011). STUDY OF DEFECT STRUCTURE AND ELECTRICAL TRANSPORT IN. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12636

Chicago Manual of Style (16th Edition):

Bittel, Brad. “STUDY OF DEFECT STRUCTURE AND ELECTRICAL TRANSPORT IN.” 2011. Doctoral Dissertation, Penn State University. Accessed January 19, 2020. https://etda.libraries.psu.edu/catalog/12636.

MLA Handbook (7th Edition):

Bittel, Brad. “STUDY OF DEFECT STRUCTURE AND ELECTRICAL TRANSPORT IN.” 2011. Web. 19 Jan 2020.

Vancouver:

Bittel B. STUDY OF DEFECT STRUCTURE AND ELECTRICAL TRANSPORT IN. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2020 Jan 19]. Available from: https://etda.libraries.psu.edu/catalog/12636.

Council of Science Editors:

Bittel B. STUDY OF DEFECT STRUCTURE AND ELECTRICAL TRANSPORT IN. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12636


Université de Sherbrooke

5. Valverde, Lucas. Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory » .

Degree: 2015, Université de Sherbrooke

 Avec le développement des technologies portables, les mémoires de type flash sont de plus en plus utilisées. Les compétences requises pour répondre au marché florissant… (more)

Subjects/Keywords: RRAM; BRS; BEOL; Mémoire; Procédé damascène

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APA (6th Edition):

Valverde, L. (2015). Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory » . (Masters Thesis). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/6041

Chicago Manual of Style (16th Edition):

Valverde, Lucas. “Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory » .” 2015. Masters Thesis, Université de Sherbrooke. Accessed January 19, 2020. http://hdl.handle.net/11143/6041.

MLA Handbook (7th Edition):

Valverde, Lucas. “Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory » .” 2015. Web. 19 Jan 2020.

Vancouver:

Valverde L. Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory » . [Internet] [Masters thesis]. Université de Sherbrooke; 2015. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/11143/6041.

Council of Science Editors:

Valverde L. Conception de cellules bipolaires commutables pour la technologie « Resistive Random Access Memory » . [Masters Thesis]. Université de Sherbrooke; 2015. Available from: http://hdl.handle.net/11143/6041


Virginia Tech

6. Guzman, Francisco J. Separation of Colloidal Particles in a Packed Column using Depletion Forces.

Degree: MS, Chemical Engineering, 2012, Virginia Tech

 Depletion forces were used to separate an equinumber density binary dispersion of 1.5 and 0.82 µm polystyrene sulfate (PS) particles. Experiments consisted of injecting a… (more)

Subjects/Keywords: Colloid Transport; Depletion Forces; Depletion Int

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APA (6th Edition):

Guzman, F. J. (2012). Separation of Colloidal Particles in a Packed Column using Depletion Forces. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34831

Chicago Manual of Style (16th Edition):

Guzman, Francisco J. “Separation of Colloidal Particles in a Packed Column using Depletion Forces.” 2012. Masters Thesis, Virginia Tech. Accessed January 19, 2020. http://hdl.handle.net/10919/34831.

MLA Handbook (7th Edition):

Guzman, Francisco J. “Separation of Colloidal Particles in a Packed Column using Depletion Forces.” 2012. Web. 19 Jan 2020.

Vancouver:

Guzman FJ. Separation of Colloidal Particles in a Packed Column using Depletion Forces. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/10919/34831.

Council of Science Editors:

Guzman FJ. Separation of Colloidal Particles in a Packed Column using Depletion Forces. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34831

7. Deprat, Fabien. Etude et optimisation de la stabilité thermique du silicure et du beol intermédiaire pour l'intégration 3D séquentielle : Study and optimization of silicide and intermediate beol thermal stability for 3D sequential integration.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2017, Grenoble Alpes

 Une alternative à la réduction des dimensions caractéristiques des transistors est la 3D séquentielle. L’intégration 3D séquentielle requiert la fabrication de plusieurs niveaux de composant… (more)

Subjects/Keywords: Intégration 3D séquentielle; Stabilité thermique; Tungstène; Siliciure; Fdsoi; BEOL intermédiaire; 3D sequential integration; Thermal stability; Tungsten; Silicide; Fdsoi; Intermediate BEOL; 620

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APA (6th Edition):

Deprat, F. (2017). Etude et optimisation de la stabilité thermique du silicure et du beol intermédiaire pour l'intégration 3D séquentielle : Study and optimization of silicide and intermediate beol thermal stability for 3D sequential integration. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT015

Chicago Manual of Style (16th Edition):

Deprat, Fabien. “Etude et optimisation de la stabilité thermique du silicure et du beol intermédiaire pour l'intégration 3D séquentielle : Study and optimization of silicide and intermediate beol thermal stability for 3D sequential integration.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed January 19, 2020. http://www.theses.fr/2017GREAT015.

MLA Handbook (7th Edition):

Deprat, Fabien. “Etude et optimisation de la stabilité thermique du silicure et du beol intermédiaire pour l'intégration 3D séquentielle : Study and optimization of silicide and intermediate beol thermal stability for 3D sequential integration.” 2017. Web. 19 Jan 2020.

Vancouver:

Deprat F. Etude et optimisation de la stabilité thermique du silicure et du beol intermédiaire pour l'intégration 3D séquentielle : Study and optimization of silicide and intermediate beol thermal stability for 3D sequential integration. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2017GREAT015.

Council of Science Editors:

Deprat F. Etude et optimisation de la stabilité thermique du silicure et du beol intermédiaire pour l'intégration 3D séquentielle : Study and optimization of silicide and intermediate beol thermal stability for 3D sequential integration. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT015


Texas A&M University

8. Zhou, Ying. Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.

Degree: 2010, Texas A&M University

 With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is… (more)

Subjects/Keywords: capacitance extraction; BEOL impact; lithography effect; physical synthesis flow

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APA (6th Edition):

Zhou, Y. (2010). Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Ying. “Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.” 2010. Thesis, Texas A&M University. Accessed January 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Ying. “Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.” 2010. Web. 19 Jan 2020.

Vancouver:

Zhou Y. Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou Y. Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Sherbrooke

9. Parekh, Rutu. Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation .

Degree: 2012, Université de Sherbrooke

 The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a systematic approach… (more)

Subjects/Keywords: (SET)-CMOS circuits; CMOS back-end-of-line (BEOL); SET technology

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APA (6th Edition):

Parekh, R. (2012). Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/6137

Chicago Manual of Style (16th Edition):

Parekh, Rutu. “Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation .” 2012. Doctoral Dissertation, Université de Sherbrooke. Accessed January 19, 2020. http://hdl.handle.net/11143/6137.

MLA Handbook (7th Edition):

Parekh, Rutu. “Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation .” 2012. Web. 19 Jan 2020.

Vancouver:

Parekh R. Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2012. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/11143/6137.

Council of Science Editors:

Parekh R. Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation . [Doctoral Dissertation]. Université de Sherbrooke; 2012. Available from: http://hdl.handle.net/11143/6137


University of Arizona

10. Govindarajan, Rajkumar. Oxidative Removal of Implanted Photoresists and Barrier Metals in Semiconductor Processing .

Degree: 2012, University of Arizona

 Chemical systems containing oxidants are widely used at various stages in semiconductor processing, particularly for wet cleaning and polishing applications. This dissertation presents a series… (more)

Subjects/Keywords: FEOL; Galvanic Corrosion; HDIS; Semicondutor Processing; Materials Science & Engineering; BEOL; ECMP

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APA (6th Edition):

Govindarajan, R. (2012). Oxidative Removal of Implanted Photoresists and Barrier Metals in Semiconductor Processing . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/217074

Chicago Manual of Style (16th Edition):

Govindarajan, Rajkumar. “Oxidative Removal of Implanted Photoresists and Barrier Metals in Semiconductor Processing .” 2012. Doctoral Dissertation, University of Arizona. Accessed January 19, 2020. http://hdl.handle.net/10150/217074.

MLA Handbook (7th Edition):

Govindarajan, Rajkumar. “Oxidative Removal of Implanted Photoresists and Barrier Metals in Semiconductor Processing .” 2012. Web. 19 Jan 2020.

Vancouver:

Govindarajan R. Oxidative Removal of Implanted Photoresists and Barrier Metals in Semiconductor Processing . [Internet] [Doctoral dissertation]. University of Arizona; 2012. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/10150/217074.

Council of Science Editors:

Govindarajan R. Oxidative Removal of Implanted Photoresists and Barrier Metals in Semiconductor Processing . [Doctoral Dissertation]. University of Arizona; 2012. Available from: http://hdl.handle.net/10150/217074


Cleveland State University

11. Venn, Madan R. CONVOLUTIONAL CODED GENERALIZED DIRECT SEQUENCE SPREAD SPECTRUM.

Degree: MSin Electrical Engineering, Fenn College of Engineering, 2008, Cleveland State University

  In this thesis we investigate the worst-case performance of coded ordinary and coded generalized direct sequence spread spectrum (DSSS) systems in a communication channel… (more)

Subjects/Keywords: Electrical Engineering; CONVOLUTIONAL; DSSS; int; interleaver; Encoder; constraint lengths; code rates

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APA (6th Edition):

Venn, M. R. (2008). CONVOLUTIONAL CODED GENERALIZED DIRECT SEQUENCE SPREAD SPECTRUM. (Masters Thesis). Cleveland State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=csu1212066245

Chicago Manual of Style (16th Edition):

Venn, Madan R. “CONVOLUTIONAL CODED GENERALIZED DIRECT SEQUENCE SPREAD SPECTRUM.” 2008. Masters Thesis, Cleveland State University. Accessed January 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=csu1212066245.

MLA Handbook (7th Edition):

Venn, Madan R. “CONVOLUTIONAL CODED GENERALIZED DIRECT SEQUENCE SPREAD SPECTRUM.” 2008. Web. 19 Jan 2020.

Vancouver:

Venn MR. CONVOLUTIONAL CODED GENERALIZED DIRECT SEQUENCE SPREAD SPECTRUM. [Internet] [Masters thesis]. Cleveland State University; 2008. [cited 2020 Jan 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=csu1212066245.

Council of Science Editors:

Venn MR. CONVOLUTIONAL CODED GENERALIZED DIRECT SEQUENCE SPREAD SPECTRUM. [Masters Thesis]. Cleveland State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=csu1212066245

12. Maurya, Rubina. Explaining consumer perspectives on mobile news services: a study in South Africa.

Degree: PhD, Information Systems, 2019, University of Cape Town

 Access to news supports the development of democratic societies. News can promote sustainable community development and encourage healthy social, political, and economic engagement. Mobile news… (more)

Subjects/Keywords: Mobile news services; technology adoption; technology acceptance; news consumers; accessibility; int

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APA (6th Edition):

Maurya, R. (2019). Explaining consumer perspectives on mobile news services: a study in South Africa. (Doctoral Dissertation). University of Cape Town. Retrieved from http://hdl.handle.net/11427/30105

Chicago Manual of Style (16th Edition):

Maurya, Rubina. “Explaining consumer perspectives on mobile news services: a study in South Africa.” 2019. Doctoral Dissertation, University of Cape Town. Accessed January 19, 2020. http://hdl.handle.net/11427/30105.

MLA Handbook (7th Edition):

Maurya, Rubina. “Explaining consumer perspectives on mobile news services: a study in South Africa.” 2019. Web. 19 Jan 2020.

Vancouver:

Maurya R. Explaining consumer perspectives on mobile news services: a study in South Africa. [Internet] [Doctoral dissertation]. University of Cape Town; 2019. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/11427/30105.

Council of Science Editors:

Maurya R. Explaining consumer perspectives on mobile news services: a study in South Africa. [Doctoral Dissertation]. University of Cape Town; 2019. Available from: http://hdl.handle.net/11427/30105


Karlstad University

13. Andersson, Jan-Olof. Offloading INTCollector Events with P4.

Degree: Mathematics and Computer Science (from 2013), 2019, Karlstad University

  In-Band Network Telemetry (INT) is a new technique in the area of Software-defined networking (SDN) for monitoring SDN enabled networks. INT monitoring provides fine-grained… (more)

Subjects/Keywords: INT; INTCollector; P4; Event detection; SDN; Computer Engineering; Datorteknik

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APA (6th Edition):

Andersson, J. (2019). Offloading INTCollector Events with P4. (Thesis). Karlstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-74508

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Andersson, Jan-Olof. “Offloading INTCollector Events with P4.” 2019. Thesis, Karlstad University. Accessed January 19, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-74508.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Andersson, Jan-Olof. “Offloading INTCollector Events with P4.” 2019. Web. 19 Jan 2020.

Vancouver:

Andersson J. Offloading INTCollector Events with P4. [Internet] [Thesis]. Karlstad University; 2019. [cited 2020 Jan 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-74508.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Andersson J. Offloading INTCollector Events with P4. [Thesis]. Karlstad University; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-74508

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

14. Varughese, Eunice A. Mechanisms of Cryptosporidium Parvum Invasion Using an Improved Human Epithelial Cell Model.

Degree: PhD, Medicine: Toxicology (Environmental Health), 2015, University of Cincinnati

 <i>Cryptosporidiosis</i> is an environmentally-associated human diarrheal disease caused by the etiological agent, <i>Cryptosporidium</i>. This parasitic pathogen is an intestinal protozoan that is abundant in the… (more)

Subjects/Keywords: Environmental Health; Cryptosporidium; SHP-2; in vitro; FHs 74 Int; parasitology; pathogenesis

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APA (6th Edition):

Varughese, E. A. (2015). Mechanisms of Cryptosporidium Parvum Invasion Using an Improved Human Epithelial Cell Model. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447688891

Chicago Manual of Style (16th Edition):

Varughese, Eunice A. “Mechanisms of Cryptosporidium Parvum Invasion Using an Improved Human Epithelial Cell Model.” 2015. Doctoral Dissertation, University of Cincinnati. Accessed January 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447688891.

MLA Handbook (7th Edition):

Varughese, Eunice A. “Mechanisms of Cryptosporidium Parvum Invasion Using an Improved Human Epithelial Cell Model.” 2015. Web. 19 Jan 2020.

Vancouver:

Varughese EA. Mechanisms of Cryptosporidium Parvum Invasion Using an Improved Human Epithelial Cell Model. [Internet] [Doctoral dissertation]. University of Cincinnati; 2015. [cited 2020 Jan 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447688891.

Council of Science Editors:

Varughese EA. Mechanisms of Cryptosporidium Parvum Invasion Using an Improved Human Epithelial Cell Model. [Doctoral Dissertation]. University of Cincinnati; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447688891

15. El Haddad, Fadi. Modélisation des problèmes de grandes déformations multi-domaines par une approche Eulérienne monolithique massivement parallèle : Modelling multi-domain large deformation problems using an Eulerian monolithic approach in a massively parallel environment.

Degree: Docteur es, Mécanique numérique, 2015, Paris, ENMP

La modélisation des problèmes multi-domaine est abordée dans un cadre purement Eulérien. Un maillage unique, ne représentant plus la matière, est utilisé. Les différentes frontières… (more)

Subjects/Keywords: Approche monolithique; Grandes déformations; Calcul parallèle; Large deformations; Monolithic approach; Parallel computing; 620

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APA (6th Edition):

El Haddad, F. (2015). Modélisation des problèmes de grandes déformations multi-domaines par une approche Eulérienne monolithique massivement parallèle : Modelling multi-domain large deformation problems using an Eulerian monolithic approach in a massively parallel environment. (Doctoral Dissertation). Paris, ENMP. Retrieved from http://www.theses.fr/2015ENMP0011

Chicago Manual of Style (16th Edition):

El Haddad, Fadi. “Modélisation des problèmes de grandes déformations multi-domaines par une approche Eulérienne monolithique massivement parallèle : Modelling multi-domain large deformation problems using an Eulerian monolithic approach in a massively parallel environment.” 2015. Doctoral Dissertation, Paris, ENMP. Accessed January 19, 2020. http://www.theses.fr/2015ENMP0011.

MLA Handbook (7th Edition):

El Haddad, Fadi. “Modélisation des problèmes de grandes déformations multi-domaines par une approche Eulérienne monolithique massivement parallèle : Modelling multi-domain large deformation problems using an Eulerian monolithic approach in a massively parallel environment.” 2015. Web. 19 Jan 2020.

Vancouver:

El Haddad F. Modélisation des problèmes de grandes déformations multi-domaines par une approche Eulérienne monolithique massivement parallèle : Modelling multi-domain large deformation problems using an Eulerian monolithic approach in a massively parallel environment. [Internet] [Doctoral dissertation]. Paris, ENMP; 2015. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2015ENMP0011.

Council of Science Editors:

El Haddad F. Modélisation des problèmes de grandes déformations multi-domaines par une approche Eulérienne monolithique massivement parallèle : Modelling multi-domain large deformation problems using an Eulerian monolithic approach in a massively parallel environment. [Doctoral Dissertation]. Paris, ENMP; 2015. Available from: http://www.theses.fr/2015ENMP0011

16. Coudron, Loïc. Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via.

Degree: Docteur es, Electronique, 2011, Université François-Rabelais de Tours

Ces travaux de thèse ont pour but l’évaluation et le développement de briques technologiques en silicium poreux répondant à la problématique de l’intégration monolithique 3D… (more)

Subjects/Keywords: Procédés de gravure électrochimique; Intégration monolithique; Composants passifs; Porous silicon; Anodization; Electrochemical etching; Monolithic integration

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APA (6th Edition):

Coudron, L. (2011). Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via. (Doctoral Dissertation). Université François-Rabelais de Tours. Retrieved from http://www.theses.fr/2011TOUR4028

Chicago Manual of Style (16th Edition):

Coudron, Loïc. “Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via.” 2011. Doctoral Dissertation, Université François-Rabelais de Tours. Accessed January 19, 2020. http://www.theses.fr/2011TOUR4028.

MLA Handbook (7th Edition):

Coudron, Loïc. “Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via.” 2011. Web. 19 Jan 2020.

Vancouver:

Coudron L. Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via. [Internet] [Doctoral dissertation]. Université François-Rabelais de Tours; 2011. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2011TOUR4028.

Council of Science Editors:

Coudron L. Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via. [Doctoral Dissertation]. Université François-Rabelais de Tours; 2011. Available from: http://www.theses.fr/2011TOUR4028

17. Shah, Pooja Pradeep. Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes.

Degree: Electrical Engineering (Computer Engineering), 2015, University of California – San Diego

 Particularly in advanced technology nodes, interconnects significantly affect thepower, performance, area and reliability of integrated circuits. Requirements of highintegration density, performance, complex patterning technology and… (more)

Subjects/Keywords: Electrical engineering; BEOL; Interconnect; Semiconductor; Technology; VLSI

…California, San Diego xi ABSTRACT OF THE THESIS Optimization of the BEOL Interconnect Stack for… …make it imperative to determine optimal back-end-of-line (BEOL) stack dimensions… …for high-performance IC designs. It focuses on determining optimal dimensions of the BEOL… …Chapter 1 Introduction In recent years, BEOL interconnect technology strategy for advanced VLSI… …benefits. Issues to consider while optimizing BEOL stack dimensions include the following. 1… 

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APA (6th Edition):

Shah, P. P. (2015). Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/9sf895pj

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Pooja Pradeep. “Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes.” 2015. Thesis, University of California – San Diego. Accessed January 19, 2020. http://www.escholarship.org/uc/item/9sf895pj.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Pooja Pradeep. “Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes.” 2015. Web. 19 Jan 2020.

Vancouver:

Shah PP. Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes. [Internet] [Thesis]. University of California – San Diego; 2015. [cited 2020 Jan 19]. Available from: http://www.escholarship.org/uc/item/9sf895pj.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah PP. Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes. [Thesis]. University of California – San Diego; 2015. Available from: http://www.escholarship.org/uc/item/9sf895pj

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

18. Pina-Mimbela, Ruby Melisa. Association of Polyphosphate (poly P) Kinases with Campylobacter jejuni Invasion and Survival in Human Epithelial Cells.

Degree: MS, Veterinary Preventive Medicine, 2013, The Ohio State University

 The foodborne and zoonotic bacterium Campylobacter jejuni, is one of the major causes of gastrointestinal disorders in humans worldwide. This human pathogen expresses a variety… (more)

Subjects/Keywords: Biochemistry; Cellular Biology; Microbiology; Veterinary Services; Campylobacter jejuni; Poly P kinases; invasion; survival; epithelial cells; INT-407 cells

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APA (6th Edition):

Pina-Mimbela, R. M. (2013). Association of Polyphosphate (poly P) Kinases with Campylobacter jejuni Invasion and Survival in Human Epithelial Cells. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1385978458

Chicago Manual of Style (16th Edition):

Pina-Mimbela, Ruby Melisa. “Association of Polyphosphate (poly P) Kinases with Campylobacter jejuni Invasion and Survival in Human Epithelial Cells.” 2013. Masters Thesis, The Ohio State University. Accessed January 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1385978458.

MLA Handbook (7th Edition):

Pina-Mimbela, Ruby Melisa. “Association of Polyphosphate (poly P) Kinases with Campylobacter jejuni Invasion and Survival in Human Epithelial Cells.” 2013. Web. 19 Jan 2020.

Vancouver:

Pina-Mimbela RM. Association of Polyphosphate (poly P) Kinases with Campylobacter jejuni Invasion and Survival in Human Epithelial Cells. [Internet] [Masters thesis]. The Ohio State University; 2013. [cited 2020 Jan 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1385978458.

Council of Science Editors:

Pina-Mimbela RM. Association of Polyphosphate (poly P) Kinases with Campylobacter jejuni Invasion and Survival in Human Epithelial Cells. [Masters Thesis]. The Ohio State University; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1385978458


University of Akron

19. Sheng, Li. THE INTERACTIVE HARDWARE-IN-LOOP SIMULATION SYSTEM FOR TRAFFIC CONTROL SYSTEM DEVELOPMENT.

Degree: MS, Civil Engineering, 2005, University of Akron

 With the development of modern computer technology, applications are developed to manage the transportation system intelligently and improve the efficiency of the system. Traffic controllers… (more)

Subjects/Keywords: Transportation; pNode; int; CORSIM; pLink; char; Detector; Side Street

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APA (6th Edition):

Sheng, L. (2005). THE INTERACTIVE HARDWARE-IN-LOOP SIMULATION SYSTEM FOR TRAFFIC CONTROL SYSTEM DEVELOPMENT. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1132429944

Chicago Manual of Style (16th Edition):

Sheng, Li. “THE INTERACTIVE HARDWARE-IN-LOOP SIMULATION SYSTEM FOR TRAFFIC CONTROL SYSTEM DEVELOPMENT.” 2005. Masters Thesis, University of Akron. Accessed January 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1132429944.

MLA Handbook (7th Edition):

Sheng, Li. “THE INTERACTIVE HARDWARE-IN-LOOP SIMULATION SYSTEM FOR TRAFFIC CONTROL SYSTEM DEVELOPMENT.” 2005. Web. 19 Jan 2020.

Vancouver:

Sheng L. THE INTERACTIVE HARDWARE-IN-LOOP SIMULATION SYSTEM FOR TRAFFIC CONTROL SYSTEM DEVELOPMENT. [Internet] [Masters thesis]. University of Akron; 2005. [cited 2020 Jan 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1132429944.

Council of Science Editors:

Sheng L. THE INTERACTIVE HARDWARE-IN-LOOP SIMULATION SYSTEM FOR TRAFFIC CONTROL SYSTEM DEVELOPMENT. [Masters Thesis]. University of Akron; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1132429944


Universidade Nova

20. Tomás, Sara Cristina dos Santos. Process virtualization theory (PVT) and institutional theory (INT) to explain SAAS adoption.

Degree: 2015, Universidade Nova

 Software as a service (SaaS) is a service model in which the applications are accessible from various client devices through internet. Several studies report possible… (more)

Subjects/Keywords: Process virtualization theory (PVT); Institutional theory (INT); Software as a service (SaaS); Information technology (IT) adoption

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APA (6th Edition):

Tomás, S. C. d. S. (2015). Process virtualization theory (PVT) and institutional theory (INT) to explain SAAS adoption. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/15231

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tomás, Sara Cristina dos Santos. “Process virtualization theory (PVT) and institutional theory (INT) to explain SAAS adoption.” 2015. Thesis, Universidade Nova. Accessed January 19, 2020. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/15231.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tomás, Sara Cristina dos Santos. “Process virtualization theory (PVT) and institutional theory (INT) to explain SAAS adoption.” 2015. Web. 19 Jan 2020.

Vancouver:

Tomás SCdS. Process virtualization theory (PVT) and institutional theory (INT) to explain SAAS adoption. [Internet] [Thesis]. Universidade Nova; 2015. [cited 2020 Jan 19]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/15231.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomás SCdS. Process virtualization theory (PVT) and institutional theory (INT) to explain SAAS adoption. [Thesis]. Universidade Nova; 2015. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/15231

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Raio vilela, Fernando Augusto. Structural characterization of JIP3 recruitment by Kinesin-1 : Caractérisation structurale du recrutement de JIP3 par la Kinésine-1.

Degree: Docteur es, Biochimie et biologie structurale, 2019, Paris Saclay

Le transport intracellulaire de cargos est un processus critique au sein des cellules eucaryotes, et notamment au niveau des neurones, pour contrôler différentes fonctions dont… (more)

Subjects/Keywords: Kinésine-1; Jip3; Transport intracellulaire; Biologie Structurale int; Interactions Macromoléculaires; Kinesin-1; Jip3; Intracellular transport; Integrative Structural Biology; Macromolecular Interactions

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APA (6th Edition):

Raio vilela, F. A. (2019). Structural characterization of JIP3 recruitment by Kinesin-1 : Caractérisation structurale du recrutement de JIP3 par la Kinésine-1. (Doctoral Dissertation). Paris Saclay. Retrieved from http://www.theses.fr/2019SACLS123

Chicago Manual of Style (16th Edition):

Raio vilela, Fernando Augusto. “Structural characterization of JIP3 recruitment by Kinesin-1 : Caractérisation structurale du recrutement de JIP3 par la Kinésine-1.” 2019. Doctoral Dissertation, Paris Saclay. Accessed January 19, 2020. http://www.theses.fr/2019SACLS123.

MLA Handbook (7th Edition):

Raio vilela, Fernando Augusto. “Structural characterization of JIP3 recruitment by Kinesin-1 : Caractérisation structurale du recrutement de JIP3 par la Kinésine-1.” 2019. Web. 19 Jan 2020.

Vancouver:

Raio vilela FA. Structural characterization of JIP3 recruitment by Kinesin-1 : Caractérisation structurale du recrutement de JIP3 par la Kinésine-1. [Internet] [Doctoral dissertation]. Paris Saclay; 2019. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2019SACLS123.

Council of Science Editors:

Raio vilela FA. Structural characterization of JIP3 recruitment by Kinesin-1 : Caractérisation structurale du recrutement de JIP3 par la Kinésine-1. [Doctoral Dissertation]. Paris Saclay; 2019. Available from: http://www.theses.fr/2019SACLS123

22. Monnier, Nicolas. Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems.

Degree: Docteur es, Electronique, 2018, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire

Cette thèse s’inscrit dans le développement d’imageurs térahertz en technologie intégrée CMOS avec pour volonté de rendre ces derniers fiables et robustes, de permettre de… (more)

Subjects/Keywords: Térahertz; Imagerie; Pixel; Intégration; CMOS; Monolithique; Antenne; Métasurface; Terahertz; Imaging; Pixel; Integration; CMOS; Monolithic; Antenna; Metasurface; 620

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APA (6th Edition):

Monnier, N. (2018). Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems. (Doctoral Dissertation). Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire. Retrieved from http://www.theses.fr/2018IMTA0070

Chicago Manual of Style (16th Edition):

Monnier, Nicolas. “Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems.” 2018. Doctoral Dissertation, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire. Accessed January 19, 2020. http://www.theses.fr/2018IMTA0070.

MLA Handbook (7th Edition):

Monnier, Nicolas. “Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems.” 2018. Web. 19 Jan 2020.

Vancouver:

Monnier N. Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems. [Internet] [Doctoral dissertation]. Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire; 2018. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2018IMTA0070.

Council of Science Editors:

Monnier N. Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems. [Doctoral Dissertation]. Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire; 2018. Available from: http://www.theses.fr/2018IMTA0070

23. Gaillardon, Pierre-Emmanuel. Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire.

Degree: Docteur es, Dispositifs de l'électronique intégrée, 2011, Ecully, Ecole centrale de Lyon

Durant les quatre dernières décennies, l’industrie des semi-conducteurs a connu une croissance exponentielle. En accord avec l’ITRS et à mesure de l'approche vers le nanomètre,… (more)

Subjects/Keywords: Conception Proche-Techno; PCM; 3-D monolithique; Nanofils; DG-CNFET; Crossbars; Nanoarchitectures; Benchmarking; Process-Design co-integration; Monolithic 3-D; NWFET

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APA (6th Edition):

Gaillardon, P. (2011). Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire. (Doctoral Dissertation). Ecully, Ecole centrale de Lyon. Retrieved from http://www.theses.fr/2011ECDL0027

Chicago Manual of Style (16th Edition):

Gaillardon, Pierre-Emmanuel. “Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire.” 2011. Doctoral Dissertation, Ecully, Ecole centrale de Lyon. Accessed January 19, 2020. http://www.theses.fr/2011ECDL0027.

MLA Handbook (7th Edition):

Gaillardon, Pierre-Emmanuel. “Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire.” 2011. Web. 19 Jan 2020.

Vancouver:

Gaillardon P. Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire. [Internet] [Doctoral dissertation]. Ecully, Ecole centrale de Lyon; 2011. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2011ECDL0027.

Council of Science Editors:

Gaillardon P. Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire. [Doctoral Dissertation]. Ecully, Ecole centrale de Lyon; 2011. Available from: http://www.theses.fr/2011ECDL0027

24. Capelle, Marie. Intégration monolithique de composants bipolaires et de circuits radiofréquences sur substrats mixtes silicium/silicium poreux : Monolithic integration of bipolar devices and radiofrequency circuits on porous silicon/silicon hybrid substrates.

Degree: Docteur es, Electronique, 2013, Université François-Rabelais de Tours

Le récent essor des systèmes de communication sans fil implique le développement de circuits RF performants, à fort taux d’intégration, bas coût, et adaptés à… (more)

Subjects/Keywords: Silicium poreux; Microélectronique; Intégration monolithique; Radiofréquences; Filtres; Inductances; Lignes de transmission; Porous silicon; Microelectronic; Monolithic integration; Radiofrequency; Filters; Inductors; Transmission lines

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APA (6th Edition):

Capelle, M. (2013). Intégration monolithique de composants bipolaires et de circuits radiofréquences sur substrats mixtes silicium/silicium poreux : Monolithic integration of bipolar devices and radiofrequency circuits on porous silicon/silicon hybrid substrates. (Doctoral Dissertation). Université François-Rabelais de Tours. Retrieved from http://www.theses.fr/2013TOUR4028

Chicago Manual of Style (16th Edition):

Capelle, Marie. “Intégration monolithique de composants bipolaires et de circuits radiofréquences sur substrats mixtes silicium/silicium poreux : Monolithic integration of bipolar devices and radiofrequency circuits on porous silicon/silicon hybrid substrates.” 2013. Doctoral Dissertation, Université François-Rabelais de Tours. Accessed January 19, 2020. http://www.theses.fr/2013TOUR4028.

MLA Handbook (7th Edition):

Capelle, Marie. “Intégration monolithique de composants bipolaires et de circuits radiofréquences sur substrats mixtes silicium/silicium poreux : Monolithic integration of bipolar devices and radiofrequency circuits on porous silicon/silicon hybrid substrates.” 2013. Web. 19 Jan 2020.

Vancouver:

Capelle M. Intégration monolithique de composants bipolaires et de circuits radiofréquences sur substrats mixtes silicium/silicium poreux : Monolithic integration of bipolar devices and radiofrequency circuits on porous silicon/silicon hybrid substrates. [Internet] [Doctoral dissertation]. Université François-Rabelais de Tours; 2013. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2013TOUR4028.

Council of Science Editors:

Capelle M. Intégration monolithique de composants bipolaires et de circuits radiofréquences sur substrats mixtes silicium/silicium poreux : Monolithic integration of bipolar devices and radiofrequency circuits on porous silicon/silicon hybrid substrates. [Doctoral Dissertation]. Université François-Rabelais de Tours; 2013. Available from: http://www.theses.fr/2013TOUR4028

25. Tirano, Sauveur. Intégration et caractérisation électrique d'éléments de mémorisation à commutation de résistance de type back-end à base d'oxydes métalliques. : Would it be possible to integrate Africans in the account of French national history ? : Study of ecological didactic of a History lesson in an elementary school.

Degree: Docteur es, Micro et Nanoélectronique, 2013, Aix Marseille Université

Cette thèse porte principalement sur la caractérisation électrique et la modélisation physique d'éléments mémoires émergents de type OxRRAM (Oxide Resistive Random Access Memory) intégrant soit… (more)

Subjects/Keywords: OxRRAM; Mémoire non volatile; HfO2; NiO; Caractérisation électrique; Pulvérisation cathodique réactive; Oxydation thermique; Capacité parasite; Simulation physique; BEOL; OxRRAM; Non volatile memory,; HfO2; NiO; Electrical characterization; Cathodic reactive sputtering; Thermal oxidation; Parasitic capacitance; Physical simulation; BEOL; 620.5

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APA (6th Edition):

Tirano, S. (2013). Intégration et caractérisation électrique d'éléments de mémorisation à commutation de résistance de type back-end à base d'oxydes métalliques. : Would it be possible to integrate Africans in the account of French national history ? : Study of ecological didactic of a History lesson in an elementary school. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2013AIXM4713

Chicago Manual of Style (16th Edition):

Tirano, Sauveur. “Intégration et caractérisation électrique d'éléments de mémorisation à commutation de résistance de type back-end à base d'oxydes métalliques. : Would it be possible to integrate Africans in the account of French national history ? : Study of ecological didactic of a History lesson in an elementary school.” 2013. Doctoral Dissertation, Aix Marseille Université. Accessed January 19, 2020. http://www.theses.fr/2013AIXM4713.

MLA Handbook (7th Edition):

Tirano, Sauveur. “Intégration et caractérisation électrique d'éléments de mémorisation à commutation de résistance de type back-end à base d'oxydes métalliques. : Would it be possible to integrate Africans in the account of French national history ? : Study of ecological didactic of a History lesson in an elementary school.” 2013. Web. 19 Jan 2020.

Vancouver:

Tirano S. Intégration et caractérisation électrique d'éléments de mémorisation à commutation de résistance de type back-end à base d'oxydes métalliques. : Would it be possible to integrate Africans in the account of French national history ? : Study of ecological didactic of a History lesson in an elementary school. [Internet] [Doctoral dissertation]. Aix Marseille Université 2013. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2013AIXM4713.

Council of Science Editors:

Tirano S. Intégration et caractérisation électrique d'éléments de mémorisation à commutation de résistance de type back-end à base d'oxydes métalliques. : Would it be possible to integrate Africans in the account of French national history ? : Study of ecological didactic of a History lesson in an elementary school. [Doctoral Dissertation]. Aix Marseille Université 2013. Available from: http://www.theses.fr/2013AIXM4713

26. Dasgupta, Aritra. Radiation Response in MOS Devices with High-K Gate Oxides and Metal Gates.

Degree: PhD, Electrical Engineering, 2011, Vanderbilt University

 The effects of low and medium energy x-rays on MOS capacitors with SiO2 or HfO2 gate dielectrics and Al and TaSi gate metallization have been… (more)

Subjects/Keywords: gate dielectrics; dose; metal gates; BEOL; high-k; MOS

…87 5.7. Device geometry with a single layer of back-end-of-line (BEOL) materials… …compared to the equilibrium deposited dose in a pure SiO2 for the BEOL layers ............91 5.9… …structure with 1 layer of Cu metallization and other BEOL layers… …structure with 1, 4 and 6 layers of Cu metallization and other BEOL layers.. .............….95… …6 layers of Cu metallization and other BEOL layers… 

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APA (6th Edition):

Dasgupta, A. (2011). Radiation Response in MOS Devices with High-K Gate Oxides and Metal Gates. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-08182011-095958/ ;

Chicago Manual of Style (16th Edition):

Dasgupta, Aritra. “Radiation Response in MOS Devices with High-K Gate Oxides and Metal Gates.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed January 19, 2020. http://etd.library.vanderbilt.edu//available/etd-08182011-095958/ ;.

MLA Handbook (7th Edition):

Dasgupta, Aritra. “Radiation Response in MOS Devices with High-K Gate Oxides and Metal Gates.” 2011. Web. 19 Jan 2020.

Vancouver:

Dasgupta A. Radiation Response in MOS Devices with High-K Gate Oxides and Metal Gates. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2020 Jan 19]. Available from: http://etd.library.vanderbilt.edu//available/etd-08182011-095958/ ;.

Council of Science Editors:

Dasgupta A. Radiation Response in MOS Devices with High-K Gate Oxides and Metal Gates. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu//available/etd-08182011-095958/ ;

27. El Hajjam, Khalil. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique.

Degree: PhD, Génie électrique, 2016, Université de Sherbrooke

 Résumé: Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de… (more)

Subjects/Keywords: Dépôt par couche atomique; Couches minces diélectriques high-k; Couches minces diélectriques low-k; Oxydation; Transistor à un électron; Composés de titane; Ingénierie de la jonction tunnel; Intégration BEOL; Atomic layer deposition; High-k dielectric thin films; Low-k dielectric thin films; Oxidation; Double gate single electron transistors; Ttitanium compounds; Tunnel junction engineering; BEOL integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

El Hajjam, K. (2016). Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique. (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://www.collectionscanada.gc.ca/obj/thesescanada/vol2/QSHERU/TC-QSHERU-11143_8508.pdf ; http://savoirs.usherbrooke.ca/bitstream/11143/8508/5/El_Hajjam_Khalil_PhD_2015.pdf

Chicago Manual of Style (16th Edition):

El Hajjam, Khalil. “Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique.” 2016. Doctoral Dissertation, Université de Sherbrooke. Accessed January 19, 2020. http://www.collectionscanada.gc.ca/obj/thesescanada/vol2/QSHERU/TC-QSHERU-11143_8508.pdf ; http://savoirs.usherbrooke.ca/bitstream/11143/8508/5/El_Hajjam_Khalil_PhD_2015.pdf.

MLA Handbook (7th Edition):

El Hajjam, Khalil. “Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique.” 2016. Web. 19 Jan 2020.

Vancouver:

El Hajjam K. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique. [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2016. [cited 2020 Jan 19]. Available from: http://www.collectionscanada.gc.ca/obj/thesescanada/vol2/QSHERU/TC-QSHERU-11143_8508.pdf ; http://savoirs.usherbrooke.ca/bitstream/11143/8508/5/El_Hajjam_Khalil_PhD_2015.pdf.

Council of Science Editors:

El Hajjam K. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique. [Doctoral Dissertation]. Université de Sherbrooke; 2016. Available from: http://www.collectionscanada.gc.ca/obj/thesescanada/vol2/QSHERU/TC-QSHERU-11143_8508.pdf ; http://savoirs.usherbrooke.ca/bitstream/11143/8508/5/El_Hajjam_Khalil_PhD_2015.pdf


Université de Sherbrooke

28. El Hajjam, Khalil. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique .

Degree: 2016, Université de Sherbrooke

 Résumé: Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de… (more)

Subjects/Keywords: Dépôt par couche atomique; Couches minces diélectriques high-k; Couches minces diélectriques low-k; Oxydation; Transistor à un électron; Composés de titane; Ingénierie de la jonction tunnel; Intégration BEOL; Atomic layer deposition; High-k dielectric thin films; Low-k dielectric thin films; Oxidation; Double gate single electron transistors; Ttitanium compounds; Tunnel junction engineering; BEOL integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

El Hajjam, K. (2016). Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/8508

Chicago Manual of Style (16th Edition):

El Hajjam, Khalil. “Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique .” 2016. Doctoral Dissertation, Université de Sherbrooke. Accessed January 19, 2020. http://hdl.handle.net/11143/8508.

MLA Handbook (7th Edition):

El Hajjam, Khalil. “Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique .” 2016. Web. 19 Jan 2020.

Vancouver:

El Hajjam K. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2016. [cited 2020 Jan 19]. Available from: http://hdl.handle.net/11143/8508.

Council of Science Editors:

El Hajjam K. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique . [Doctoral Dissertation]. Université de Sherbrooke; 2016. Available from: http://hdl.handle.net/11143/8508

29. Hajjam, Khalil El. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique : Tunnel barrier engineering to enhance the performances of the metallic single electron transistor.

Degree: Docteur es, Électronique, Électrotechnique, Automatique, 2015, INSA Lyon

Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal… (more)

Subjects/Keywords: Electronique; Transistor mono-Électroniques - SET; Dépôt par couches minces; Couches minces diélectriques high-K; Couches minces diélectriques low-K; Oxudation; Transistor à un électron; Composés de titane; Ingénierie de la jonction tunnel; Intégration BEOL; Electronics; Atomic layer deposition; High-K dielectric thin films; Low-K dielectric films; Double gate single electron transistors; Titanium compounds; Tunnel junction engineering; BEOL integration; 621.381 520 72

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hajjam, K. E. (2015). Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique : Tunnel barrier engineering to enhance the performances of the metallic single electron transistor. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2015ISAL0111

Chicago Manual of Style (16th Edition):

Hajjam, Khalil El. “Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique : Tunnel barrier engineering to enhance the performances of the metallic single electron transistor.” 2015. Doctoral Dissertation, INSA Lyon. Accessed January 19, 2020. http://www.theses.fr/2015ISAL0111.

MLA Handbook (7th Edition):

Hajjam, Khalil El. “Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique : Tunnel barrier engineering to enhance the performances of the metallic single electron transistor.” 2015. Web. 19 Jan 2020.

Vancouver:

Hajjam KE. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique : Tunnel barrier engineering to enhance the performances of the metallic single electron transistor. [Internet] [Doctoral dissertation]. INSA Lyon; 2015. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2015ISAL0111.

Council of Science Editors:

Hajjam KE. Ingénierie de jonctions tunnel pour améliorer les performances du transistor mono-électronique métallique : Tunnel barrier engineering to enhance the performances of the metallic single electron transistor. [Doctoral Dissertation]. INSA Lyon; 2015. Available from: http://www.theses.fr/2015ISAL0111

30. To, Duc Ngoc. Circuit de pilotage intégré pour transistor de puissance : Integrated driving circuit for power transistor.

Degree: Docteur es, Génie électrique, 2015, Grenoble Alpes

Ces travaux de thèse s’inscrivent dans le cadre d’une collaboration entre les laboratoires G2ELAB et IMEP-LAHC en lien avec le projet BQR WiSiTUDe (Grenoble-INP). Le… (more)

Subjects/Keywords: Driver intégré; Transformateur sans noyau magnétique; Driver isolé; Intégration CMOS; Intégration SOI; Intégration monolithique; Integrated driver; Coreless transformer; Isolated driver; CMOS driver; SOI driver; Monolithic integration; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

To, D. N. (2015). Circuit de pilotage intégré pour transistor de puissance : Integrated driving circuit for power transistor. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT017

Chicago Manual of Style (16th Edition):

To, Duc Ngoc. “Circuit de pilotage intégré pour transistor de puissance : Integrated driving circuit for power transistor.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed January 19, 2020. http://www.theses.fr/2015GREAT017.

MLA Handbook (7th Edition):

To, Duc Ngoc. “Circuit de pilotage intégré pour transistor de puissance : Integrated driving circuit for power transistor.” 2015. Web. 19 Jan 2020.

Vancouver:

To DN. Circuit de pilotage intégré pour transistor de puissance : Integrated driving circuit for power transistor. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2020 Jan 19]. Available from: http://www.theses.fr/2015GREAT017.

Council of Science Editors:

To DN. Circuit de pilotage intégré pour transistor de puissance : Integrated driving circuit for power transistor. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT017

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