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Brno University of Technology

1. Vlha, Matej. Odhad výkonnosti diskových polí s využitím prediktivní analytiky .

Degree: 2017, Brno University of Technology

Práca sa zaoberá problematikou diskových polí, kde je cieľom navrhnúť testovacie scenáre pre meranie výkonu diskového poľa a pomocou nástrojov prediktívnej analytiky natrénovať na nameranej sade dát model, ktorý bude predpovedať zvolený výkonnostný parameter. Pomocou realizovanej webovej aplikácie je demonštrovaná funkčnosť natrénovaného modelu a znázornený odhad výkonu diskového poľa.; Thesis focuses on disk arrays, where the goal is to design test scenarios to measure performance of disk array and use predictive analytics tools to train a model that will predict the selected performance parameter on a measured set of data. The implemented web application demonstrates the functionality of the trained model and shows estimate of the disk array performance. Advisors/Committee Members: Burget, Radim (advisor).

Subjects/Keywords: diskové pole; DiskSpd; IOps; prediktívna analytika; kNN; ANN; SVM; natrénovaný model; trénovacia sada dát; testovacia sada dát; disk array; DiskSpd; IOps; predictive analytict; kNN; ANN; SVM; trained model; training data sets; testing data sets

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vlha, M. (2017). Odhad výkonnosti diskových polí s využitím prediktivní analytiky . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/65800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vlha, Matej. “Odhad výkonnosti diskových polí s využitím prediktivní analytiky .” 2017. Thesis, Brno University of Technology. Accessed March 23, 2019. http://hdl.handle.net/11012/65800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vlha, Matej. “Odhad výkonnosti diskových polí s využitím prediktivní analytiky .” 2017. Web. 23 Mar 2019.

Vancouver:

Vlha M. Odhad výkonnosti diskových polí s využitím prediktivní analytiky . [Internet] [Thesis]. Brno University of Technology; 2017. [cited 2019 Mar 23]. Available from: http://hdl.handle.net/11012/65800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vlha M. Odhad výkonnosti diskových polí s využitím prediktivní analytiky . [Thesis]. Brno University of Technology; 2017. Available from: http://hdl.handle.net/11012/65800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Mukundan, Janani. Improving Memory And I/O Systems Through Foresight .

Degree: 2014, Cornell University

Traditionally, DRAM scheduling techniques have been optimized for performance. Only recently has there been a push for improving other optimization metrics, such as energy efficiency, power, or fairness. A multitude of scheduling algorithms have been proposed in the past few years for tackling these goals. But a major shortcoming in many of these techniques is that they are made up of inflexible, static hard-coded scheduling policies that lack the ability to learn and improve automatically with experience, or to reconfigure themselves to target a variety of such optimization metrics. Recently, Ipek et al. [32] proposed the use of reinforcement learning (RL) to design high-performance, self-optimizing memory schedulers. Reinforcement learning is a machine learning technique that learns automatically with experience, by interacting with the environment. It tries to pick the actions that maximize a desired long-term objective function. By using an online learning technique like RL, memory controllers have the capability of foresight and longterm planning, thereby enabling a non-greedy approach to scheduling. How ever, Ipek et al.'s methodology has a key limitation: it does not possess a generalizable way to target an objective function. In my thesis, we present a framework for designing a class of memory controllers that have the capability of managing multiple objective functions in a synergistic and coordinated fashion. MORSE (MultiObjective Reconfigurable Self-Optimizing Scheduler) is a systematic and general methodology to design reconfigurable DRAM schedulers following RL principles. Our framework also provides a way to reconfigure the scheduler on the field (post-silicon), whether at boot time or dynamically at run time, to accommodate changes to the optimization criteria. Beyond DRAM scheduling, we find that the storage technology landscape is rapidly undergoing many changes, primarily enabled by device scaling. In particular, DRAM is scaling in terms of density and frequency. High-density DRAM chips are becoming increasingly more common. As a result, memory systems are becoming more complex structurally. Due to this, a number of problems that were either non-existent or inconsequential in prior DRAM systems, have started surfacing. In particular, DRAM refresh overheads are on the rise. In the next part of my thesis, we investigate refresh overheads that are caused due to DRAM scaling. We propose simple scheduling techniques that help mitigate refresh stalls that occur in high density DDR4 memory systems. These techniques again involve the notion of foresight, by anticipating the patterns that lead to refresh stalls, and planning ahead of time to mitigate them. Scheduling refreshes is a real-time algorithm, and missing deadlines may lead to reliability concerns. Hence, this research initially focuses on simple prioritization techniques that do not require complex online learning to overcome refresh stalls. Over the past few years computer systems of all types have started integrating flash memory. The usage of… Advisors/Committee Members: Lipson, Hod (committeeMember), Albonesi, David H. (committeeMember).

Subjects/Keywords: DRAMs; Scheduling; Performance; Power; Machine learning; RL; DDR4 Memory; Refresh; Flash; IOPS; Endurance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukundan, J. (2014). Improving Memory And I/O Systems Through Foresight . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/36018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mukundan, Janani. “Improving Memory And I/O Systems Through Foresight .” 2014. Thesis, Cornell University. Accessed March 23, 2019. http://hdl.handle.net/1813/36018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mukundan, Janani. “Improving Memory And I/O Systems Through Foresight .” 2014. Web. 23 Mar 2019.

Vancouver:

Mukundan J. Improving Memory And I/O Systems Through Foresight . [Internet] [Thesis]. Cornell University; 2014. [cited 2019 Mar 23]. Available from: http://hdl.handle.net/1813/36018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mukundan J. Improving Memory And I/O Systems Through Foresight . [Thesis]. Cornell University; 2014. Available from: http://hdl.handle.net/1813/36018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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