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You searched for subject:( Field Programmable Gate Arrays FPGA ). Showing records 1 – 30 of 19633 total matches.

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1. Lorandel, Jordane. Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems.

Degree: Docteur es, Electronique et Télécommunications, 2015, Rennes, INSA

Les systèmes de communications sans fil n'ont cessé d'évoluer ces dernières années, poussés par de fortes demandes du marché en systèmes toujours plus autonomes et… (more)

Subjects/Keywords: FPGA; Modélisation haut-niveau; Field programmable gate arrays; 621.3

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APA (6th Edition):

Lorandel, J. (2015). Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems. (Doctoral Dissertation). Rennes, INSA. Retrieved from http://www.theses.fr/2015ISAR0036

Chicago Manual of Style (16th Edition):

Lorandel, Jordane. “Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems.” 2015. Doctoral Dissertation, Rennes, INSA. Accessed August 18, 2019. http://www.theses.fr/2015ISAR0036.

MLA Handbook (7th Edition):

Lorandel, Jordane. “Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems.” 2015. Web. 18 Aug 2019.

Vancouver:

Lorandel J. Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems. [Internet] [Doctoral dissertation]. Rennes, INSA; 2015. [cited 2019 Aug 18]. Available from: http://www.theses.fr/2015ISAR0036.

Council of Science Editors:

Lorandel J. Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems. [Doctoral Dissertation]. Rennes, INSA; 2015. Available from: http://www.theses.fr/2015ISAR0036


University of Technology, Sydney

2. Yu, Ying-Hao. FPGA based formation control of multiple ubiquitous indoor robots.

Degree: 2011, University of Technology, Sydney

 This thesis explores the feasibility of using Field-Programmable Gate Array (FPGA) technology for formation control of multiple indoor robots in an ubiquitous computing environment. It… (more)

Subjects/Keywords: FPGA.; Ubiquitous computing.; Field programmable gate arrays.; Robots.

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APA (6th Edition):

Yu, Y. (2011). FPGA based formation control of multiple ubiquitous indoor robots. (Thesis). University of Technology, Sydney. Retrieved from http://hdl.handle.net/10453/20375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Ying-Hao. “FPGA based formation control of multiple ubiquitous indoor robots.” 2011. Thesis, University of Technology, Sydney. Accessed August 18, 2019. http://hdl.handle.net/10453/20375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Ying-Hao. “FPGA based formation control of multiple ubiquitous indoor robots.” 2011. Web. 18 Aug 2019.

Vancouver:

Yu Y. FPGA based formation control of multiple ubiquitous indoor robots. [Internet] [Thesis]. University of Technology, Sydney; 2011. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10453/20375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu Y. FPGA based formation control of multiple ubiquitous indoor robots. [Thesis]. University of Technology, Sydney; 2011. Available from: http://hdl.handle.net/10453/20375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Rao, Parthasarathy Murali Baskar. Implementation of an industrial process control interface for the LSC11 system using Lattice ECP2M FPGA.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

  Reconfigurable devices are the mainstream in today’s system on chip solutions. Reconfigurable devices have the advantages of reduced cost over their equivalent custom design,… (more)

Subjects/Keywords: PCI Express (PCIe); Lattice ECP2M (ECP2M); Field Programmable Gate Arrays (FPGA)

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APA (6th Edition):

Rao, P. M. B. (2012). Implementation of an industrial process control interface for the LSC11 system using Lattice ECP2M FPGA. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rao, Parthasarathy Murali Baskar. “Implementation of an industrial process control interface for the LSC11 system using Lattice ECP2M FPGA.” 2012. Thesis, Linköping UniversityLinköping University. Accessed August 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rao, Parthasarathy Murali Baskar. “Implementation of an industrial process control interface for the LSC11 system using Lattice ECP2M FPGA.” 2012. Web. 18 Aug 2019.

Vancouver:

Rao PMB. Implementation of an industrial process control interface for the LSC11 system using Lattice ECP2M FPGA. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2019 Aug 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rao PMB. Implementation of an industrial process control interface for the LSC11 system using Lattice ECP2M FPGA. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Mavroidis, Iakovos. Novel techniques for hardware / software partitioning and emulation.

Degree: 2011, Technical University of Crete (TUC); Πολυτεχνείο Κρήτης

 Over the last several years, uniprocessor systems, in an effort to overcome the limits of deeperpipelining, instruction-level parallelism and power dissipation, evolved from one processing… (more)

Subjects/Keywords: System design; Computer-aided design; Field programmable gate arrays (FPGA)

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APA (6th Edition):

Mavroidis, I. (2011). Novel techniques for hardware / software partitioning and emulation. (Thesis). Technical University of Crete (TUC); Πολυτεχνείο Κρήτης. Retrieved from http://hdl.handle.net/10442/hedi/32016

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mavroidis, Iakovos. “Novel techniques for hardware / software partitioning and emulation.” 2011. Thesis, Technical University of Crete (TUC); Πολυτεχνείο Κρήτης. Accessed August 18, 2019. http://hdl.handle.net/10442/hedi/32016.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mavroidis, Iakovos. “Novel techniques for hardware / software partitioning and emulation.” 2011. Web. 18 Aug 2019.

Vancouver:

Mavroidis I. Novel techniques for hardware / software partitioning and emulation. [Internet] [Thesis]. Technical University of Crete (TUC); Πολυτεχνείο Κρήτης; 2011. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10442/hedi/32016.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mavroidis I. Novel techniques for hardware / software partitioning and emulation. [Thesis]. Technical University of Crete (TUC); Πολυτεχνείο Κρήτης; 2011. Available from: http://hdl.handle.net/10442/hedi/32016

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

5. Liu, Cheng. QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.

Degree: PhD, 2015, University of Hong Kong

The use of FPGAs as accelerators for compute-intensive loops has been demonstrated by numerous researchers as an effective solution to meet both the performance and… (more)

Subjects/Keywords: Field programmable gate arrays

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APA (6th Edition):

Liu, C. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Doctoral Dissertation). University of Hong Kong. Retrieved from Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764

Chicago Manual of Style (16th Edition):

Liu, Cheng. “QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.” 2015. Doctoral Dissertation, University of Hong Kong. Accessed August 18, 2019. Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764.

MLA Handbook (7th Edition):

Liu, Cheng. “QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.” 2015. Web. 18 Aug 2019.

Vancouver:

Liu C. QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. [Internet] [Doctoral dissertation]. University of Hong Kong; 2015. [cited 2019 Aug 18]. Available from: Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764.

Council of Science Editors:

Liu C. QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. [Doctoral Dissertation]. University of Hong Kong; 2015. Available from: Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764


University of Hong Kong

6. Ng, Ho-cheung. A soft processor overlay with tightly-coupled FPGA accelerator.

Degree: M. Phil., 2015, University of Hong Kong

FPGA overlays have shown the potential to improve designers’ productivity through balancing flexibility and ease of configuration of the underlying fabric while maintaining considerable overall… (more)

Subjects/Keywords: Field programmable gate arrays

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APA (6th Edition):

Ng, H. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Masters Thesis). University of Hong Kong. Retrieved from Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791

Chicago Manual of Style (16th Edition):

Ng, Ho-cheung. “A soft processor overlay with tightly-coupled FPGA accelerator.” 2015. Masters Thesis, University of Hong Kong. Accessed August 18, 2019. Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791.

MLA Handbook (7th Edition):

Ng, Ho-cheung. “A soft processor overlay with tightly-coupled FPGA accelerator.” 2015. Web. 18 Aug 2019.

Vancouver:

Ng H. A soft processor overlay with tightly-coupled FPGA accelerator. [Internet] [Masters thesis]. University of Hong Kong; 2015. [cited 2019 Aug 18]. Available from: Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791.

Council of Science Editors:

Ng H. A soft processor overlay with tightly-coupled FPGA accelerator. [Masters Thesis]. University of Hong Kong; 2015. Available from: Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791


University of Hong Kong

7. 林郁.; Lin, Yu, Colin. ArchSyn: an energy-efficient FPGA high-level synthesizer.

Degree: PhD, 2012, University of Hong Kong

 Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive… (more)

Subjects/Keywords: Field programmable gate arrays.

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APA (6th Edition):

林郁.; Lin, Yu, C. (2012). ArchSyn: an energy-efficient FPGA high-level synthesizer. (Doctoral Dissertation). University of Hong Kong. Retrieved from Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525

Chicago Manual of Style (16th Edition):

林郁.; Lin, Yu, Colin. “ArchSyn: an energy-efficient FPGA high-level synthesizer.” 2012. Doctoral Dissertation, University of Hong Kong. Accessed August 18, 2019. Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525.

MLA Handbook (7th Edition):

林郁.; Lin, Yu, Colin. “ArchSyn: an energy-efficient FPGA high-level synthesizer.” 2012. Web. 18 Aug 2019.

Vancouver:

林郁.; Lin, Yu C. ArchSyn: an energy-efficient FPGA high-level synthesizer. [Internet] [Doctoral dissertation]. University of Hong Kong; 2012. [cited 2019 Aug 18]. Available from: Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525.

Council of Science Editors:

林郁.; Lin, Yu C. ArchSyn: an energy-efficient FPGA high-level synthesizer. [Doctoral Dissertation]. University of Hong Kong; 2012. Available from: Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525


Oregon State University

8. Zhao, Yichen. Design and FPGA implementation of digital transmission over severe ISI channels.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how… (more)

Subjects/Keywords: ISI; Field programmable gate arrays

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APA (6th Edition):

Zhao, Y. (2013). Design and FPGA implementation of digital transmission over severe ISI channels. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39400

Chicago Manual of Style (16th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Masters Thesis, Oregon State University. Accessed August 18, 2019. http://hdl.handle.net/1957/39400.

MLA Handbook (7th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Web. 18 Aug 2019.

Vancouver:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/1957/39400.

Council of Science Editors:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39400


Nelson Mandela Metropolitan University

9. Potgieter, Juan-Pierre. Single event upset testing of flash based field programmable gate arrays.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2015, Nelson Mandela Metropolitan University

 In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities;… (more)

Subjects/Keywords: Field programmable gate arrays

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APA (6th Edition):

Potgieter, J. (2015). Single event upset testing of flash based field programmable gate arrays. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Thesis, Nelson Mandela Metropolitan University. Accessed August 18, 2019. http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Web. 18 Aug 2019.

Vancouver:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2015. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Thesis]. Nelson Mandela Metropolitan University; 2015. Available from: http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Baylor University

10. Trower, John W. Accelerating path planning algorithms with high level synthesis tools and FPGAs.

Degree: Electrical and Computer Engineering., 2013, Baylor University

 Accelerating path planning algorithms with field programmable gate arrays (FPGA) allows the designer to achieve significant performance increases over using a traditional central processing unit… (more)

Subjects/Keywords: Path planning algorithms.; Field programmable gate arrays.; FPGA.; High level synthesis tools.; Converting algorithms.

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APA (6th Edition):

Trower, J. W. (2013). Accelerating path planning algorithms with high level synthesis tools and FPGAs. (Thesis). Baylor University. Retrieved from http://hdl.handle.net/2104/8600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trower, John W. “Accelerating path planning algorithms with high level synthesis tools and FPGAs. ” 2013. Thesis, Baylor University. Accessed August 18, 2019. http://hdl.handle.net/2104/8600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trower, John W. “Accelerating path planning algorithms with high level synthesis tools and FPGAs. ” 2013. Web. 18 Aug 2019.

Vancouver:

Trower JW. Accelerating path planning algorithms with high level synthesis tools and FPGAs. [Internet] [Thesis]. Baylor University; 2013. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/2104/8600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trower JW. Accelerating path planning algorithms with high level synthesis tools and FPGAs. [Thesis]. Baylor University; 2013. Available from: http://hdl.handle.net/2104/8600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Melbourne

11. CHEN, SIMIN. Real-time signal processing for coherent optical OFDM system.

Degree: 2011, University of Melbourne

 The principle of Orthogonal Frequency-Division Multiplexing (OFDM) modulation has been proposed for several decades. OFDM technology has moved out of laboratories into practice in modern… (more)

Subjects/Keywords: Orthogonal Frequency-Division Multiplexing; OFDM; coherent communications; Field-Programmable Gate Arrays; FPGA

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APA (6th Edition):

CHEN, S. (2011). Real-time signal processing for coherent optical OFDM system. (Doctoral Dissertation). University of Melbourne. Retrieved from http://hdl.handle.net/11343/36109

Chicago Manual of Style (16th Edition):

CHEN, SIMIN. “Real-time signal processing for coherent optical OFDM system.” 2011. Doctoral Dissertation, University of Melbourne. Accessed August 18, 2019. http://hdl.handle.net/11343/36109.

MLA Handbook (7th Edition):

CHEN, SIMIN. “Real-time signal processing for coherent optical OFDM system.” 2011. Web. 18 Aug 2019.

Vancouver:

CHEN S. Real-time signal processing for coherent optical OFDM system. [Internet] [Doctoral dissertation]. University of Melbourne; 2011. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/11343/36109.

Council of Science Editors:

CHEN S. Real-time signal processing for coherent optical OFDM system. [Doctoral Dissertation]. University of Melbourne; 2011. Available from: http://hdl.handle.net/11343/36109

12. Reis, Bruno Ricardo Lito. Development of a low cost RF Lab .

Degree: 2017, Universidade de Aveiro

 Com o aumento dos serviços de rede móvel disponíveis é necessária uma utilização mais eficiente dos recursos disponíveis. Para conseguir isso, são necessárias ferramentas de… (more)

Subjects/Keywords: Engenharia eletrónica e telecomunicações; Radiofrequência; Amplificadores de potência; FPGA (Field programmable gate arrays)

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APA (6th Edition):

Reis, B. R. L. (2017). Development of a low cost RF Lab . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/23836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reis, Bruno Ricardo Lito. “Development of a low cost RF Lab .” 2017. Thesis, Universidade de Aveiro. Accessed August 18, 2019. http://hdl.handle.net/10773/23836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reis, Bruno Ricardo Lito. “Development of a low cost RF Lab .” 2017. Web. 18 Aug 2019.

Vancouver:

Reis BRL. Development of a low cost RF Lab . [Internet] [Thesis]. Universidade de Aveiro; 2017. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10773/23836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reis BRL. Development of a low cost RF Lab . [Thesis]. Universidade de Aveiro; 2017. Available from: http://hdl.handle.net/10773/23836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Sotiriades, Euripides. Reconfigurable architecture structures for the BLAST DNA sequencing algorithm.

Degree: 2011, Technical University of Crete (TUC); Πολυτεχνείο Κρήτης

 Computational Molecular Biology or Bioinformatics is an emerging area for Electronic and Computer Engineering. Bioinformatics research results are expected to have a great impact on… (more)

Subjects/Keywords: Bioinformatics; Molecular biology; Data processing; Nucleotide sequence; Field programmable gate arrays (FPGA)

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APA (6th Edition):

Sotiriades, E. (2011). Reconfigurable architecture structures for the BLAST DNA sequencing algorithm. (Thesis). Technical University of Crete (TUC); Πολυτεχνείο Κρήτης. Retrieved from http://hdl.handle.net/10442/hedi/32018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sotiriades, Euripides. “Reconfigurable architecture structures for the BLAST DNA sequencing algorithm.” 2011. Thesis, Technical University of Crete (TUC); Πολυτεχνείο Κρήτης. Accessed August 18, 2019. http://hdl.handle.net/10442/hedi/32018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sotiriades, Euripides. “Reconfigurable architecture structures for the BLAST DNA sequencing algorithm.” 2011. Web. 18 Aug 2019.

Vancouver:

Sotiriades E. Reconfigurable architecture structures for the BLAST DNA sequencing algorithm. [Internet] [Thesis]. Technical University of Crete (TUC); Πολυτεχνείο Κρήτης; 2011. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10442/hedi/32018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sotiriades E. Reconfigurable architecture structures for the BLAST DNA sequencing algorithm. [Thesis]. Technical University of Crete (TUC); Πολυτεχνείο Κρήτης; 2011. Available from: http://hdl.handle.net/10442/hedi/32018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

14. Luu, Jason. A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs.

Degree: 2010, University of Toronto

The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement… (more)

Subjects/Keywords: FPGA; CAD; Packing; Clustering; Field-Programmable Gate Arrays; Computer-Aided Design; Architecture; 0544

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APA (6th Edition):

Luu, J. (2010). A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/24601

Chicago Manual of Style (16th Edition):

Luu, Jason. “A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs.” 2010. Masters Thesis, University of Toronto. Accessed August 18, 2019. http://hdl.handle.net/1807/24601.

MLA Handbook (7th Edition):

Luu, Jason. “A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs.” 2010. Web. 18 Aug 2019.

Vancouver:

Luu J. A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs. [Internet] [Masters thesis]. University of Toronto; 2010. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/1807/24601.

Council of Science Editors:

Luu J. A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs. [Masters Thesis]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/24601


University of Hong Kong

15. 蔡育明; Choi, Yuk-ming. A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster.

Degree: M. Phil., 2013, University of Hong Kong

The era of big data has led to problems of unprecedented scale and complexity that are challenging the computing capability of conventional computer systems. One… (more)

Subjects/Keywords: Field programmable gate arrays; High performance computing

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APA (6th Edition):

蔡育明; Choi, Y. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Masters Thesis). University of Hong Kong. Retrieved from Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679

Chicago Manual of Style (16th Edition):

蔡育明; Choi, Yuk-ming. “A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster.” 2013. Masters Thesis, University of Hong Kong. Accessed August 18, 2019. Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679.

MLA Handbook (7th Edition):

蔡育明; Choi, Yuk-ming. “A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster.” 2013. Web. 18 Aug 2019.

Vancouver:

蔡育明; Choi Y. A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. [Internet] [Masters thesis]. University of Hong Kong; 2013. [cited 2019 Aug 18]. Available from: Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679.

Council of Science Editors:

蔡育明; Choi Y. A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. [Masters Thesis]. University of Hong Kong; 2013. Available from: Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679


Ryerson University

16. Mutukuda, Omesh. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.

Degree: 2010, Ryerson University

Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown… (more)

Subjects/Keywords: Field programmable gate arrays; Integrated circuits

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APA (6th Edition):

Mutukuda, O. (2010). Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Thesis, Ryerson University. Accessed August 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Web. 18 Aug 2019.

Vancouver:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Internet] [Thesis]. Ryerson University; 2010. [cited 2019 Aug 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Patel, Tanvika M. Implementation of a software defined radio on FPGAs using system generator.

Degree: 2010, University of Tennessee – Chattanooga

 The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array.… (more)

Subjects/Keywords: Field programmable gate arrays; Software radio

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patel, T. M. (2010). Implementation of a software defined radio on FPGAs using system generator. (Masters Thesis). University of Tennessee – Chattanooga. Retrieved from https://scholar.utc.edu/theses/359

Chicago Manual of Style (16th Edition):

Patel, Tanvika M. “Implementation of a software defined radio on FPGAs using system generator.” 2010. Masters Thesis, University of Tennessee – Chattanooga. Accessed August 18, 2019. https://scholar.utc.edu/theses/359.

MLA Handbook (7th Edition):

Patel, Tanvika M. “Implementation of a software defined radio on FPGAs using system generator.” 2010. Web. 18 Aug 2019.

Vancouver:

Patel TM. Implementation of a software defined radio on FPGAs using system generator. [Internet] [Masters thesis]. University of Tennessee – Chattanooga; 2010. [cited 2019 Aug 18]. Available from: https://scholar.utc.edu/theses/359.

Council of Science Editors:

Patel TM. Implementation of a software defined radio on FPGAs using system generator. [Masters Thesis]. University of Tennessee – Chattanooga; 2010. Available from: https://scholar.utc.edu/theses/359

18. Purani, Abhilash M. An evaluation of low cost fpga-based software defined radios for education and research.

Degree: 2010, University of Tennessee – Chattanooga

 The purpose of this study is to evaluate a low-cost Software Defined Radio (SDR) platform for educational and research purposes. An evaluation of existing SDR… (more)

Subjects/Keywords: Field programmable gate arrays; Software radio

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APA (6th Edition):

Purani, A. M. (2010). An evaluation of low cost fpga-based software defined radios for education and research. (Masters Thesis). University of Tennessee – Chattanooga. Retrieved from https://scholar.utc.edu/theses/369

Chicago Manual of Style (16th Edition):

Purani, Abhilash M. “An evaluation of low cost fpga-based software defined radios for education and research.” 2010. Masters Thesis, University of Tennessee – Chattanooga. Accessed August 18, 2019. https://scholar.utc.edu/theses/369.

MLA Handbook (7th Edition):

Purani, Abhilash M. “An evaluation of low cost fpga-based software defined radios for education and research.” 2010. Web. 18 Aug 2019.

Vancouver:

Purani AM. An evaluation of low cost fpga-based software defined radios for education and research. [Internet] [Masters thesis]. University of Tennessee – Chattanooga; 2010. [cited 2019 Aug 18]. Available from: https://scholar.utc.edu/theses/369.

Council of Science Editors:

Purani AM. An evaluation of low cost fpga-based software defined radios for education and research. [Masters Thesis]. University of Tennessee – Chattanooga; 2010. Available from: https://scholar.utc.edu/theses/369


Montana State University

19. Buerkle, Todd Michael. Ionizing radiation detector for environmental awareness in FPGA-based flight computers.

Degree: College of Engineering, 2012, Montana State University

 Ionizing radiation has a detrimental effect on digital electronics that operate in extraterrestrial environments. When electronics are struck by these high energy particles, the effect… (more)

Subjects/Keywords: Ionizing radiation.; Field programmable gate arrays.

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APA (6th Edition):

Buerkle, T. M. (2012). Ionizing radiation detector for environmental awareness in FPGA-based flight computers. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Buerkle, Todd Michael. “Ionizing radiation detector for environmental awareness in FPGA-based flight computers.” 2012. Thesis, Montana State University. Accessed August 18, 2019. https://scholarworks.montana.edu/xmlui/handle/1/1007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Buerkle, Todd Michael. “Ionizing radiation detector for environmental awareness in FPGA-based flight computers.” 2012. Web. 18 Aug 2019.

Vancouver:

Buerkle TM. Ionizing radiation detector for environmental awareness in FPGA-based flight computers. [Internet] [Thesis]. Montana State University; 2012. [cited 2019 Aug 18]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Buerkle TM. Ionizing radiation detector for environmental awareness in FPGA-based flight computers. [Thesis]. Montana State University; 2012. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

20. Casebeer, Christopher Ness. A system to eavesdrop on marmosets.

Degree: College of Engineering, 2015, Montana State University

 This masters thesis describes developing a custom digital recording system to record the vocalizations and behavior of marmosets, which are small primates native to the… (more)

Subjects/Keywords: Field programmable gate arrays.; Animal behavior.; Monkeys.

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APA (6th Edition):

Casebeer, C. N. (2015). A system to eavesdrop on marmosets. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/12731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Casebeer, Christopher Ness. “A system to eavesdrop on marmosets.” 2015. Thesis, Montana State University. Accessed August 18, 2019. https://scholarworks.montana.edu/xmlui/handle/1/12731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Casebeer, Christopher Ness. “A system to eavesdrop on marmosets.” 2015. Web. 18 Aug 2019.

Vancouver:

Casebeer CN. A system to eavesdrop on marmosets. [Internet] [Thesis]. Montana State University; 2015. [cited 2019 Aug 18]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Casebeer CN. A system to eavesdrop on marmosets. [Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

21. Weber, Raymond Joseph. Reconfigurable hardware accelerators for high performance radiation tolerant computers.

Degree: College of Engineering, 2014, Montana State University

 Computers play an important role in spaceflight and with ever more complex mission goals and sensors, current devices are not sufficient to meet the requirements… (more)

Subjects/Keywords: Field programmable gate arrays.; Radiation tolerance.

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APA (6th Edition):

Weber, R. J. (2014). Reconfigurable hardware accelerators for high performance radiation tolerant computers. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/8695

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Weber, Raymond Joseph. “Reconfigurable hardware accelerators for high performance radiation tolerant computers.” 2014. Thesis, Montana State University. Accessed August 18, 2019. https://scholarworks.montana.edu/xmlui/handle/1/8695.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Weber, Raymond Joseph. “Reconfigurable hardware accelerators for high performance radiation tolerant computers.” 2014. Web. 18 Aug 2019.

Vancouver:

Weber RJ. Reconfigurable hardware accelerators for high performance radiation tolerant computers. [Internet] [Thesis]. Montana State University; 2014. [cited 2019 Aug 18]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/8695.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weber RJ. Reconfigurable hardware accelerators for high performance radiation tolerant computers. [Thesis]. Montana State University; 2014. Available from: https://scholarworks.montana.edu/xmlui/handle/1/8695

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

22. Turner, David Lee Douglas. Implementation of a radiation-tolerant computer based on a LEON3 architecture.

Degree: College of Engineering, 2015, Montana State University

 It is desired to create an inexpensive, open-source, radiation-tolerant computer for space applications using commercial, off-the-shelf parts and a proven space-grade processor. Building upon previous… (more)

Subjects/Keywords: Field programmable gate arrays.; Radiation.; Computer software.

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APA (6th Edition):

Turner, D. L. D. (2015). Implementation of a radiation-tolerant computer based on a LEON3 architecture. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/10163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Turner, David Lee Douglas. “Implementation of a radiation-tolerant computer based on a LEON3 architecture.” 2015. Thesis, Montana State University. Accessed August 18, 2019. https://scholarworks.montana.edu/xmlui/handle/1/10163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Turner, David Lee Douglas. “Implementation of a radiation-tolerant computer based on a LEON3 architecture.” 2015. Web. 18 Aug 2019.

Vancouver:

Turner DLD. Implementation of a radiation-tolerant computer based on a LEON3 architecture. [Internet] [Thesis]. Montana State University; 2015. [cited 2019 Aug 18]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/10163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Turner DLD. Implementation of a radiation-tolerant computer based on a LEON3 architecture. [Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/10163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

23. Hyder, Nafiul. Minimizing the layout area of 2-input look up tables.

Degree: 2017, Ryerson University

 This work investigates the minimum layout area of multiplexers, a fundamental building block of Field-Programmable Gate Arrays (FPGAs). In particular, we investigate the minimum layout… (more)

Subjects/Keywords: Field programmable gate arrays  – Computer-aided design.; Field programmable gate arrays  – Design and construction.; Multiplexing.

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APA (6th Edition):

Hyder, N. (2017). Minimizing the layout area of 2-input look up tables. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hyder, Nafiul. “Minimizing the layout area of 2-input look up tables.” 2017. Thesis, Ryerson University. Accessed August 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hyder, Nafiul. “Minimizing the layout area of 2-input look up tables.” 2017. Web. 18 Aug 2019.

Vancouver:

Hyder N. Minimizing the layout area of 2-input look up tables. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Aug 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hyder N. Minimizing the layout area of 2-input look up tables. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

24. Zafar, Muhammad Umair. Measuring the dynamic energy efficiency of FPGAs over processors.

Degree: 2016, Ryerson University

 This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive… (more)

Subjects/Keywords: Field programmable gate arrays  – Energy consumption  – Measurement; Field programmable gate arrays  – Energy consumption  – Mathematical models

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APA (6th Edition):

Zafar, M. U. (2016). Measuring the dynamic energy efficiency of FPGAs over processors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zafar, Muhammad Umair. “Measuring the dynamic energy efficiency of FPGAs over processors.” 2016. Thesis, Ryerson University. Accessed August 18, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A5816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zafar, Muhammad Umair. “Measuring the dynamic energy efficiency of FPGAs over processors.” 2016. Web. 18 Aug 2019.

Vancouver:

Zafar MU. Measuring the dynamic energy efficiency of FPGAs over processors. [Internet] [Thesis]. Ryerson University; 2016. [cited 2019 Aug 18]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zafar MU. Measuring the dynamic energy efficiency of FPGAs over processors. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

25. Santos, Leonardo Pereira. Cost-effective dynamic repair for FPGAs in real-time systems.

Degree: 2016, Universidade do Rio Grande do Sul

Field-Programmable Gate Arrays (FPGAs) are widely used in digital systems due to characteristics such as flexibility, low cost and high density. These characteristics are due… (more)

Subjects/Keywords: Field-programmable gate arrays (FPGA); Microeletrônica; Sistemas : Tempo real; Scrubbing; Fault diagnosis; Fault tolerance; Real-time

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APA (6th Edition):

Santos, L. P. (2016). Cost-effective dynamic repair for FPGAs in real-time systems. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/138206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, Leonardo Pereira. “Cost-effective dynamic repair for FPGAs in real-time systems.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed August 18, 2019. http://hdl.handle.net/10183/138206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, Leonardo Pereira. “Cost-effective dynamic repair for FPGAs in real-time systems.” 2016. Web. 18 Aug 2019.

Vancouver:

Santos LP. Cost-effective dynamic repair for FPGAs in real-time systems. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10183/138206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos LP. Cost-effective dynamic repair for FPGAs in real-time systems. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/138206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Nalluri, Purnachand. A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding .

Degree: 2016, Universidade de Aveiro

 Video coding has been used in applications like video surveillance, video conferencing, video streaming, video broadcasting and video storage. In a typical video coding standard,… (more)

Subjects/Keywords: Engenharia electrotécnica; Vídeo digital; Codificação de imagem; Compressão de imagem; Movimento - Estimação; Algoritmos; Arquitectura de computadores; FPGA (Field programmable gate arrays)

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APA (6th Edition):

Nalluri, P. (2016). A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/15442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nalluri, Purnachand. “A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding .” 2016. Thesis, Universidade de Aveiro. Accessed August 18, 2019. http://hdl.handle.net/10773/15442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nalluri, Purnachand. “A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding .” 2016. Web. 18 Aug 2019.

Vancouver:

Nalluri P. A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding . [Internet] [Thesis]. Universidade de Aveiro; 2016. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10773/15442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nalluri P. A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding . [Thesis]. Universidade de Aveiro; 2016. Available from: http://hdl.handle.net/10773/15442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Santos, Tiago Vallejo dos. Sudoku em FPGA .

Degree: 2011, Universidade de Aveiro

 Este trabalho, desenvolvido no âmbito dos sistemas reconfiguráveis, tem como objetivo a implementação de um solucionador de puzzles Sudoku, quer em software quer em hardware,… (more)

Subjects/Keywords: Engenharia electrónica; Puzzles; Resolução de problemas: processamento de dados; Dispositivos lógicos programáveis; FPGA (Field programmable gate arrays)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santos, T. V. d. (2011). Sudoku em FPGA . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/8946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, Tiago Vallejo dos. “Sudoku em FPGA .” 2011. Thesis, Universidade de Aveiro. Accessed August 18, 2019. http://hdl.handle.net/10773/8946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, Tiago Vallejo dos. “Sudoku em FPGA .” 2011. Web. 18 Aug 2019.

Vancouver:

Santos TVd. Sudoku em FPGA . [Internet] [Thesis]. Universidade de Aveiro; 2011. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10773/8946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos TVd. Sudoku em FPGA . [Thesis]. Universidade de Aveiro; 2011. Available from: http://hdl.handle.net/10773/8946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

28. Landy, Aaron M. Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route.

Degree: MS, Electrical and Computer Engineering, 2013, University of Florida

Field-programmable gate arrays (FPGAs) have been widely shown to have significant performance and power advantages compared to microprocessors and graphics-processing units (GPUs), but remain a… (more)

Subjects/Keywords: Architectural design; Boxes; Coarse grained; Comparators; Computer technology; Field programmable gate arrays; Multiplexers; Shift registers; Topology; Tradeoffs; fpga  – reconfigurable  – routing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Landy, A. M. (2013). Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route. (Masters Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0045513

Chicago Manual of Style (16th Edition):

Landy, Aaron M. “Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route.” 2013. Masters Thesis, University of Florida. Accessed August 18, 2019. http://ufdc.ufl.edu/UFE0045513.

MLA Handbook (7th Edition):

Landy, Aaron M. “Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route.” 2013. Web. 18 Aug 2019.

Vancouver:

Landy AM. Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route. [Internet] [Masters thesis]. University of Florida; 2013. [cited 2019 Aug 18]. Available from: http://ufdc.ufl.edu/UFE0045513.

Council of Science Editors:

Landy AM. Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route. [Masters Thesis]. University of Florida; 2013. Available from: http://ufdc.ufl.edu/UFE0045513

29. Serra, Carlos David Alexandre. Análise e implementação de ordenação de dados em FPGA .

Degree: 2010, Universidade de Aveiro

 Desde os primórdios da computação que os algoritmos de ordenação têm sido investigados. Estes podem ser baseados em diferentes tipos de estruturas de dados. A… (more)

Subjects/Keywords: Engenharia electrónica; Circuitos integrados; Dispositivos lógicos programáveis; Algoritmos de computador; Microprocessadores; Arquitectura de computadores; FPGA (Field programmable gate arrays)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Serra, C. D. A. (2010). Análise e implementação de ordenação de dados em FPGA . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/4484

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Serra, Carlos David Alexandre. “Análise e implementação de ordenação de dados em FPGA .” 2010. Thesis, Universidade de Aveiro. Accessed August 18, 2019. http://hdl.handle.net/10773/4484.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Serra, Carlos David Alexandre. “Análise e implementação de ordenação de dados em FPGA .” 2010. Web. 18 Aug 2019.

Vancouver:

Serra CDA. Análise e implementação de ordenação de dados em FPGA . [Internet] [Thesis]. Universidade de Aveiro; 2010. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10773/4484.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Serra CDA. Análise e implementação de ordenação de dados em FPGA . [Thesis]. Universidade de Aveiro; 2010. Available from: http://hdl.handle.net/10773/4484

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Oliveira, Ramiro Manuel Silva. Análise e comparação de métodos soft/hard em sistemas reconfiguráveis .

Degree: 2010, Universidade de Aveiro

 O avançar da tecnologia na área dos sistemas digitais, que se traduziu num aumento significativo da velocidade e numa diminuição dos consumos e das dimensões,… (more)

Subjects/Keywords: Engenharia electrónica; Dispositivos lógicos programáveis; Sistemas embebidos; Microprocessadores; Microcontroladores; Arquitectura de computadores; FPGA (Field programmable gate arrays)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, R. M. S. (2010). Análise e comparação de métodos soft/hard em sistemas reconfiguráveis . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/3709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Ramiro Manuel Silva. “Análise e comparação de métodos soft/hard em sistemas reconfiguráveis .” 2010. Thesis, Universidade de Aveiro. Accessed August 18, 2019. http://hdl.handle.net/10773/3709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Ramiro Manuel Silva. “Análise e comparação de métodos soft/hard em sistemas reconfiguráveis .” 2010. Web. 18 Aug 2019.

Vancouver:

Oliveira RMS. Análise e comparação de métodos soft/hard em sistemas reconfiguráveis . [Internet] [Thesis]. Universidade de Aveiro; 2010. [cited 2019 Aug 18]. Available from: http://hdl.handle.net/10773/3709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira RMS. Análise e comparação de métodos soft/hard em sistemas reconfiguráveis . [Thesis]. Universidade de Aveiro; 2010. Available from: http://hdl.handle.net/10773/3709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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