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You searched for subject:( DDR4 Memory). Showing records 1 – 2 of 2 total matches.

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1. Mukundan, Janani. Improving Memory And I/O Systems Through Foresight .

Degree: 2014, Cornell University

Traditionally, DRAM scheduling techniques have been optimized for performance. Only recently has there been a push for improving other optimization metrics, such as energy efficiency, power, or fairness. A multitude of scheduling algorithms have been proposed in the past few years for tackling these goals. But a major shortcoming in many of these techniques is that they are made up of inflexible, static hard-coded scheduling policies that lack the ability to learn and improve automatically with experience, or to reconfigure themselves to target a variety of such optimization metrics. Recently, Ipek et al. [32] proposed the use of reinforcement learning (RL) to design high-performance, self-optimizing memory schedulers. Reinforcement learning is a machine learning technique that learns automatically with experience, by interacting with the environment. It tries to pick the actions that maximize a desired long-term objective function. By using an online learning technique like RL, memory controllers have the capability of foresight and longterm planning, thereby enabling a non-greedy approach to scheduling. How ever, Ipek et al.'s methodology has a key limitation: it does not possess a generalizable way to target an objective function. In my thesis, we present a framework for designing a class of memory controllers that have the capability of managing multiple objective functions in a synergistic and coordinated fashion. MORSE (MultiObjective Reconfigurable Self-Optimizing Scheduler) is a systematic and general methodology to design reconfigurable DRAM schedulers following RL principles. Our framework also provides a way to reconfigure the scheduler on the field (post-silicon), whether at boot time or dynamically at run time, to accommodate changes to the optimization criteria. Beyond DRAM scheduling, we find that the storage technology landscape is rapidly undergoing many changes, primarily enabled by device scaling. In particular, DRAM is scaling in terms of density and frequency. High-density DRAM chips are becoming increasingly more common. As a result, memory systems are becoming more complex structurally. Due to this, a number of problems that were either non-existent or inconsequential in prior DRAM systems, have started surfacing. In particular, DRAM refresh overheads are on the rise. In the next part of my thesis, we investigate refresh overheads that are caused due to DRAM scaling. We propose simple scheduling techniques that help mitigate refresh stalls that occur in high density DDR4 memory systems. These techniques again involve the notion of foresight, by anticipating the patterns that lead to refresh stalls, and planning ahead of time to mitigate them. Scheduling refreshes is a real-time algorithm, and missing deadlines may lead to reliability concerns. Hence, this research initially focuses on simple prioritization techniques that do not require complex online learning to overcome refresh stalls. Over the past few years computer systems of all types have started integrating flash memory. The usage of… Advisors/Committee Members: Lipson, Hod (committeeMember), Albonesi, David H. (committeeMember).

Subjects/Keywords: DRAMs; Scheduling; Performance; Power; Machine learning; RL; DDR4 Memory; Refresh; Flash; IOPS; Endurance

…3 Understanding and Mitigating Refresh Overheads in High Density DDR4 Memory 3.1… …1.1.1 Memory scheduling for diverse optimization functions . . 1.1.2 Refresh in High Density… …MORSE: Improving Scheduling in Memory Systems 2.1 Introduction… …2.3 A General Framework For Self-Optimizing Memory Schedulers 2.3.1 Design… …3.8 3.9 3.2.1 JEDEC DDR4 DRAM Specification . . . . . . . . . . . . . . 3.2.2 DDR4 DRAM… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukundan, J. (2014). Improving Memory And I/O Systems Through Foresight . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/36018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mukundan, Janani. “Improving Memory And I/O Systems Through Foresight .” 2014. Thesis, Cornell University. Accessed March 20, 2019. http://hdl.handle.net/1813/36018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mukundan, Janani. “Improving Memory And I/O Systems Through Foresight .” 2014. Web. 20 Mar 2019.

Vancouver:

Mukundan J. Improving Memory And I/O Systems Through Foresight . [Internet] [Thesis]. Cornell University; 2014. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1813/36018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mukundan J. Improving Memory And I/O Systems Through Foresight . [Thesis]. Cornell University; 2014. Available from: http://hdl.handle.net/1813/36018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Krishnapillai, Yogen. Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems.

Degree: 2015, University of Waterloo

In this thesis, we present a rank-switching open-row DRAM controller for mixed critical real time systems. This memory controller is optimized for multi-requestor and multi-rank memory systems. The key to improved performance is an innovative rank-switching mechanism which hides the latency of write to read transitions in DRAM devices without requiring unpredictable request reordering. We further employ open-row policy to take advantage of the data caching mechanism (row buffering) in each device. We choose the bank privatization scheme where each requestor is assigned its own private bank or set of banks. This private bank mapping guarantees that each requestor has its own row buffers and cannot be interfered by other requestors. The proposed memory controller design allows maximum of thirty two requestors at a time targeting either two or four ranks. This controller provides complete timing isolation between critical and non-critical applications and allows for compositional timing analysis over number of requestors and memory ranks in the system. We designed both the front end logic for the command generation and back end logic for the DRAM timing constraint check and arbitration utilizing the rank switching techniques. The complete design is implemented and synthesized using Verilog RTL and finally, we evaluated performance using various benchmarks. Our proposed memory controller offers significantly lower worst case latency bounds for critical real-time applications and supports average throughput for non-critical real-time applications compared to existing real time memory controllers in the literature.

Subjects/Keywords: Rank Switching DDR3 Memory Controller; Rank hopping Memory Controller; Bank Privatization; DDR4 Memory Controller; Real Time Memory Controller; Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems; multi port memory controller; worst-case execution time (WCET)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Krishnapillai, Y. (2015). Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/9088

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Krishnapillai, Yogen. “Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems.” 2015. Thesis, University of Waterloo. Accessed March 20, 2019. http://hdl.handle.net/10012/9088.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Krishnapillai, Yogen. “Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems.” 2015. Web. 20 Mar 2019.

Vancouver:

Krishnapillai Y. Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems. [Internet] [Thesis]. University of Waterloo; 2015. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/10012/9088.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Krishnapillai Y. Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems. [Thesis]. University of Waterloo; 2015. Available from: http://hdl.handle.net/10012/9088

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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