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You searched for subject:( ADC). Showing records 1 – 30 of 506 total matches.

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Oregon State University

1. Muhlestein, Jason, Russell. Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques.

Degree: PhD, 2017, Oregon State University

 The internet-of-things is a growing market segment which is based on an array of portable communication devices with high power efficiency. Advanced semiconductor technology can… (more)

Subjects/Keywords: ADC

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APA (6th Edition):

Muhlestein, Jason, R. (2017). Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/61673

Chicago Manual of Style (16th Edition):

Muhlestein, Jason, Russell. “Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques.” 2017. Doctoral Dissertation, Oregon State University. Accessed October 01, 2020. http://hdl.handle.net/1957/61673.

MLA Handbook (7th Edition):

Muhlestein, Jason, Russell. “Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques.” 2017. Web. 01 Oct 2020.

Vancouver:

Muhlestein, Jason R. Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques. [Internet] [Doctoral dissertation]. Oregon State University; 2017. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1957/61673.

Council of Science Editors:

Muhlestein, Jason R. Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques. [Doctoral Dissertation]. Oregon State University; 2017. Available from: http://hdl.handle.net/1957/61673


Texas A&M University

2. Cai, Shengchang. Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications.

Degree: PhD, Electrical Engineering, 2018, Texas A&M University

 Serial input/output (I/O) data rates are increasing in order to support the explosion in network traffic driven by big data applications such as the Internet… (more)

Subjects/Keywords: Highspeed ADC; ADC-based receiver

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APA (6th Edition):

Cai, S. (2018). Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173607

Chicago Manual of Style (16th Edition):

Cai, Shengchang. “Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications.” 2018. Doctoral Dissertation, Texas A&M University. Accessed October 01, 2020. http://hdl.handle.net/1969.1/173607.

MLA Handbook (7th Edition):

Cai, Shengchang. “Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications.” 2018. Web. 01 Oct 2020.

Vancouver:

Cai S. Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1969.1/173607.

Council of Science Editors:

Cai S. Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173607


University of Texas – Austin

3. Gulati, Paridhi. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.

Degree: MSin Engineering, Electrical and Computer Engineering, 2016, University of Texas – Austin

 A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the… (more)

Subjects/Keywords: Pipelined ADC; SAR ADC

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APA (6th Edition):

Gulati, P. (2016). A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65964

Chicago Manual of Style (16th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Masters Thesis, University of Texas – Austin. Accessed October 01, 2020. http://hdl.handle.net/2152/65964.

MLA Handbook (7th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Web. 01 Oct 2020.

Vancouver:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/2152/65964.

Council of Science Editors:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/65964


Dalhousie University

4. Ceekala, Mithun. STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2013, Dalhousie University

 This thesis presents a new architecture of stochastic Analog-to-Digital converter (ADC). A standard Stochastic ADC uses comparator random offset as the trip point while all… (more)

Subjects/Keywords: stochastic ADC

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APA (6th Edition):

Ceekala, M. (2013). STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/21911

Chicago Manual of Style (16th Edition):

Ceekala, Mithun. “STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS.” 2013. Masters Thesis, Dalhousie University. Accessed October 01, 2020. http://hdl.handle.net/10222/21911.

MLA Handbook (7th Edition):

Ceekala, Mithun. “STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS.” 2013. Web. 01 Oct 2020.

Vancouver:

Ceekala M. STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS. [Internet] [Masters thesis]. Dalhousie University; 2013. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10222/21911.

Council of Science Editors:

Ceekala M. STOCHASTIC ADC WITH RANDOM U-QUADRATIC DISTRIBUTED REFERENCE VOLTAGES TO UNIFORMLY DISTRIBUTE COMPARATORS TRIP POINTS. [Masters Thesis]. Dalhousie University; 2013. Available from: http://hdl.handle.net/10222/21911


NSYSU

5. Fan, Gang-Jin. A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison.

Degree: Master, Electrical Engineering, 2005, NSYSU

 A 3.3V 8-bit 250MSample/sec synchronous comparison current-mode analog to digital converter is described in this thesis. The high bits and low bits are realized by… (more)

Subjects/Keywords: ADC

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APA (6th Edition):

Fan, G. (2005). A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fan, Gang-Jin. “A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison.” 2005. Thesis, NSYSU. Accessed October 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fan, Gang-Jin. “A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison.” 2005. Web. 01 Oct 2020.

Vancouver:

Fan G. A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison. [Internet] [Thesis]. NSYSU; 2005. [cited 2020 Oct 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fan G. A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison. [Thesis]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719105-153559

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

6. Jamalizavareh, Shiva. Jitter Suppression Techniques for High Speed Communication Systems.

Degree: PhD, Electrical Engineering, 2019, University of Minnesota

 The drive towards fast and robust communication has resulted in an increased focus on high frequency analog and digital transceivers. One of the major challenges… (more)

Subjects/Keywords: ADC; Jitter

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APA (6th Edition):

Jamalizavareh, S. (2019). Jitter Suppression Techniques for High Speed Communication Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/211765

Chicago Manual of Style (16th Edition):

Jamalizavareh, Shiva. “Jitter Suppression Techniques for High Speed Communication Systems.” 2019. Doctoral Dissertation, University of Minnesota. Accessed October 01, 2020. http://hdl.handle.net/11299/211765.

MLA Handbook (7th Edition):

Jamalizavareh, Shiva. “Jitter Suppression Techniques for High Speed Communication Systems.” 2019. Web. 01 Oct 2020.

Vancouver:

Jamalizavareh S. Jitter Suppression Techniques for High Speed Communication Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11299/211765.

Council of Science Editors:

Jamalizavareh S. Jitter Suppression Techniques for High Speed Communication Systems. [Doctoral Dissertation]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/211765


Linköping University

7. Radhakrishnan, Venkataraman. Design of a low power analog to digital converter in a 130nmCMOS technology.

Degree: Electronics System, 2011, Linköping University

  Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the… (more)

Subjects/Keywords: pipeline ADC; fully differential; CLS ADC

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APA (6th Edition):

Radhakrishnan, V. (2011). Design of a low power analog to digital converter in a 130nmCMOS technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Radhakrishnan, Venkataraman. “Design of a low power analog to digital converter in a 130nmCMOS technology.” 2011. Thesis, Linköping University. Accessed October 01, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Radhakrishnan, Venkataraman. “Design of a low power analog to digital converter in a 130nmCMOS technology.” 2011. Web. 01 Oct 2020.

Vancouver:

Radhakrishnan V. Design of a low power analog to digital converter in a 130nmCMOS technology. [Internet] [Thesis]. Linköping University; 2011. [cited 2020 Oct 01]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Radhakrishnan V. Design of a low power analog to digital converter in a 130nmCMOS technology. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Crasso, Anthony. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.

Degree: MS, 2013, Worcester Polytechnic Institute

 In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized… (more)

Subjects/Keywords: Calibration; Flash; ADC

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APA (6th Edition):

Crasso, A. (2013). Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Crasso, Anthony. “Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.” 2013. Thesis, Worcester Polytechnic Institute. Accessed October 01, 2020. etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Crasso, Anthony. “Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.” 2013. Web. 01 Oct 2020.

Vancouver:

Crasso A. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. [Internet] [Thesis]. Worcester Polytechnic Institute; 2013. [cited 2020 Oct 01]. Available from: etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Crasso A. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. [Thesis]. Worcester Polytechnic Institute; 2013. Available from: etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

9. Gianelli, Christopher David. One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Florida

 This work considers the problem of estimating the parameters of a noisy signal which has been quantized to one-bit via a time-varying thresholding operation. This… (more)

Subjects/Keywords: adc  – engineering  – estimation

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APA (6th Edition):

Gianelli, C. D. (2019). One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation. (Doctoral Dissertation). University of Florida. Retrieved from https://ufdc.ufl.edu/UFE0055945

Chicago Manual of Style (16th Edition):

Gianelli, Christopher David. “One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation.” 2019. Doctoral Dissertation, University of Florida. Accessed October 01, 2020. https://ufdc.ufl.edu/UFE0055945.

MLA Handbook (7th Edition):

Gianelli, Christopher David. “One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation.” 2019. Web. 01 Oct 2020.

Vancouver:

Gianelli CD. One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation. [Internet] [Doctoral dissertation]. University of Florida; 2019. [cited 2020 Oct 01]. Available from: https://ufdc.ufl.edu/UFE0055945.

Council of Science Editors:

Gianelli CD. One-Bit Compressive Sampling with Time-Varying Thresholds the Cramer-Rao Bound, Maximum Likelihood, and Sparse Estimation. [Doctoral Dissertation]. University of Florida; 2019. Available from: https://ufdc.ufl.edu/UFE0055945


Delft University of Technology

10. Das, Aurojyoti (author). Multichannel LC ADC: to Record Atrial Electrograms.

Degree: 2019, Delft University of Technology

Biosignals such as electoencephalogram (EEG), electrocorticogram (ECoG), atrial electrogram (AEG) etc. are being recorded from multiple channels simultaneously to improve the spatial resolution of the… (more)

Subjects/Keywords: Biosignals; atrial fibrillation; ADC; level crossing ADC; multichannel ADC

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APA (6th Edition):

Das, A. (. (2019). Multichannel LC ADC: to Record Atrial Electrograms. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ca77d0f7-0ea7-4782-a42a-c878c5204956

Chicago Manual of Style (16th Edition):

Das, Aurojyoti (author). “Multichannel LC ADC: to Record Atrial Electrograms.” 2019. Masters Thesis, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:ca77d0f7-0ea7-4782-a42a-c878c5204956.

MLA Handbook (7th Edition):

Das, Aurojyoti (author). “Multichannel LC ADC: to Record Atrial Electrograms.” 2019. Web. 01 Oct 2020.

Vancouver:

Das A(. Multichannel LC ADC: to Record Atrial Electrograms. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:ca77d0f7-0ea7-4782-a42a-c878c5204956.

Council of Science Editors:

Das A(. Multichannel LC ADC: to Record Atrial Electrograms. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:ca77d0f7-0ea7-4782-a42a-c878c5204956

11. Thangamani, Manivannan. The design of an all-digital VCO-based ADC in a 65nm CMOS technology.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  This thesis explores the study and design of an all-digital VCO-based ADC in a 65 nm CMOS technology. As the CMOS process enters the… (more)

Subjects/Keywords: VCO-ADC; VCO-bsaed ADC; Time-based quantizer; all-digital ADC; VCO; FDC

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APA (6th Edition):

Thangamani, M. (2014). The design of an all-digital VCO-based ADC in a 65nm CMOS technology. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Thangamani, Manivannan. “The design of an all-digital VCO-based ADC in a 65nm CMOS technology.” 2014. Thesis, Linköping UniversityLinköping University. Accessed October 01, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Thangamani, Manivannan. “The design of an all-digital VCO-based ADC in a 65nm CMOS technology.” 2014. Web. 01 Oct 2020.

Vancouver:

Thangamani M. The design of an all-digital VCO-based ADC in a 65nm CMOS technology. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2020 Oct 01]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Thangamani M. The design of an all-digital VCO-based ADC in a 65nm CMOS technology. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-112928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

12. Tatu, Cristian Ionut (author). An Error Feedback Noise Shaping SAR ADC.

Degree: 2019, Delft University of Technology

Analog-to-digital converters are important blocks in any electronic system which act as a bridge between analog signals and digital processors. The conventional SAR ADC employs… (more)

Subjects/Keywords: Noise Shaping SAR ADC; SAR ADC; capacitive DAC; switching scheme; CMOS; energy efficient; ADC

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APA (6th Edition):

Tatu, C. I. (. (2019). An Error Feedback Noise Shaping SAR ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2ffea978-0a5c-4474-8460-7bdf9046866a

Chicago Manual of Style (16th Edition):

Tatu, Cristian Ionut (author). “An Error Feedback Noise Shaping SAR ADC.” 2019. Masters Thesis, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:2ffea978-0a5c-4474-8460-7bdf9046866a.

MLA Handbook (7th Edition):

Tatu, Cristian Ionut (author). “An Error Feedback Noise Shaping SAR ADC.” 2019. Web. 01 Oct 2020.

Vancouver:

Tatu CI(. An Error Feedback Noise Shaping SAR ADC. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:2ffea978-0a5c-4474-8460-7bdf9046866a.

Council of Science Editors:

Tatu CI(. An Error Feedback Noise Shaping SAR ADC. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:2ffea978-0a5c-4474-8460-7bdf9046866a


University of Houston

13. Amaka, Ogechukwu. Impact of Automated Dispensing Cabinet Optimization on the Incidence of Medication Stockouts.

Degree: MS, Pharmacy Leadership & Administration, 2020, University of Houston

 PURPOSE: Assess the change in the incidence of medication stockouts and median stockout duration, and to determine the amount of drug wastage before and after… (more)

Subjects/Keywords: automated dispensing cabinet; ADC; stockout

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APA (6th Edition):

Amaka, O. (2020). Impact of Automated Dispensing Cabinet Optimization on the Incidence of Medication Stockouts. (Masters Thesis). University of Houston. Retrieved from http://hdl.handle.net/10657/6981

Chicago Manual of Style (16th Edition):

Amaka, Ogechukwu. “Impact of Automated Dispensing Cabinet Optimization on the Incidence of Medication Stockouts.” 2020. Masters Thesis, University of Houston. Accessed October 01, 2020. http://hdl.handle.net/10657/6981.

MLA Handbook (7th Edition):

Amaka, Ogechukwu. “Impact of Automated Dispensing Cabinet Optimization on the Incidence of Medication Stockouts.” 2020. Web. 01 Oct 2020.

Vancouver:

Amaka O. Impact of Automated Dispensing Cabinet Optimization on the Incidence of Medication Stockouts. [Internet] [Masters thesis]. University of Houston; 2020. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10657/6981.

Council of Science Editors:

Amaka O. Impact of Automated Dispensing Cabinet Optimization on the Incidence of Medication Stockouts. [Masters Thesis]. University of Houston; 2020. Available from: http://hdl.handle.net/10657/6981


The Ohio State University

14. Ravikumar, Dinesh. Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB.

Degree: MS, Electrical and Computer Engineering, 2016, The Ohio State University

 High Speed Analog to Digital Converters (ADCs) are being widely used in digital communication, digital oscilloscopes and fast data acquisition systems since they provide the… (more)

Subjects/Keywords: Electrical Engineering; ADC Modeling

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APA (6th Edition):

Ravikumar, D. (2016). Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228

Chicago Manual of Style (16th Edition):

Ravikumar, Dinesh. “Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB.” 2016. Masters Thesis, The Ohio State University. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228.

MLA Handbook (7th Edition):

Ravikumar, Dinesh. “Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB.” 2016. Web. 01 Oct 2020.

Vancouver:

Ravikumar D. Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB. [Internet] [Masters thesis]. The Ohio State University; 2016. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228.

Council of Science Editors:

Ravikumar D. Modeling of Ideal and Error Characteristics of a Multi – Stage,Time Interleaved Sub – Ranging Analog to Digital Converter usingMATLAB. [Masters Thesis]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228


Oregon State University

15. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC(more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed October 01, 2020. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 01 Oct 2020.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


University of Texas – Austin

16. Bayoumy, Mostafa Elsayed. A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash… (more)

Subjects/Keywords: Pipeline ADC; 1.5-bit stage

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APA (6th Edition):

Bayoumy, M. E. (2013). A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24010

Chicago Manual of Style (16th Edition):

Bayoumy, Mostafa Elsayed. “A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage.” 2013. Masters Thesis, University of Texas – Austin. Accessed October 01, 2020. http://hdl.handle.net/2152/24010.

MLA Handbook (7th Edition):

Bayoumy, Mostafa Elsayed. “A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage.” 2013. Web. 01 Oct 2020.

Vancouver:

Bayoumy ME. A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/2152/24010.

Council of Science Editors:

Bayoumy ME. A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24010

17. Hallström, Claes. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor… (more)

Subjects/Keywords: adc; sar; digital calibration

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APA (6th Edition):

Hallström, C. (2013). Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hallström, Claes. “Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.” 2013. Thesis, Linköping UniversityLinköping University. Accessed October 01, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hallström, Claes. “Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC.” 2013. Web. 01 Oct 2020.

Vancouver:

Hallström C. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Oct 01]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hallström C. Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97400

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

18. Hu, W. (author). A 9-bit 33MHz Hybrid SAR Single-slope ADC.

Degree: 2015, Delft University of Technology

In this work a 9-bit, 33MHz hybrid SAR single-slope ADC for element-level digitization in 2D ultrasound transducer arrays is presented. This hybrid architecture consists of… (more)

Subjects/Keywords: ADC; Hybrid SAR single-slope

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APA (6th Edition):

Hu, W. (. (2015). A 9-bit 33MHz Hybrid SAR Single-slope ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842

Chicago Manual of Style (16th Edition):

Hu, W (author). “A 9-bit 33MHz Hybrid SAR Single-slope ADC.” 2015. Masters Thesis, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842.

MLA Handbook (7th Edition):

Hu, W (author). “A 9-bit 33MHz Hybrid SAR Single-slope ADC.” 2015. Web. 01 Oct 2020.

Vancouver:

Hu W(. A 9-bit 33MHz Hybrid SAR Single-slope ADC. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842.

Council of Science Editors:

Hu W(. A 9-bit 33MHz Hybrid SAR Single-slope ADC. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:d9773876-5527-473a-a2d0-64cad121a842


Delft University of Technology

19. Shi, Yixin (author). A Low-Power Area-Efficient SAR-Assisted Hybrid ADC for Ultrasound Imaging.

Degree: 2017, Delft University of Technology

This thesis presents a Low-Power Area-Ecient SAR-Assisted Hybrid ADC for ultra- sound imaging systems. This ADC combines a 5-bit SAR ADC per channel with a… (more)

Subjects/Keywords: Hybrid ADC; SAR; ultrasound imaging

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APA (6th Edition):

Shi, Y. (. (2017). A Low-Power Area-Efficient SAR-Assisted Hybrid ADC for Ultrasound Imaging. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:b38b134c-88a8-4fe8-a706-68abb0a715cc

Chicago Manual of Style (16th Edition):

Shi, Yixin (author). “A Low-Power Area-Efficient SAR-Assisted Hybrid ADC for Ultrasound Imaging.” 2017. Masters Thesis, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:b38b134c-88a8-4fe8-a706-68abb0a715cc.

MLA Handbook (7th Edition):

Shi, Yixin (author). “A Low-Power Area-Efficient SAR-Assisted Hybrid ADC for Ultrasound Imaging.” 2017. Web. 01 Oct 2020.

Vancouver:

Shi Y(. A Low-Power Area-Efficient SAR-Assisted Hybrid ADC for Ultrasound Imaging. [Internet] [Masters thesis]. Delft University of Technology; 2017. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:b38b134c-88a8-4fe8-a706-68abb0a715cc.

Council of Science Editors:

Shi Y(. A Low-Power Area-Efficient SAR-Assisted Hybrid ADC for Ultrasound Imaging. [Masters Thesis]. Delft University of Technology; 2017. Available from: http://resolver.tudelft.nl/uuid:b38b134c-88a8-4fe8-a706-68abb0a715cc


Delft University of Technology

20. Zhan, Xin (author). A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC.

Degree: 2018, Delft University of Technology

 This thesis presents the design and implementation of a low power 3rd-order loop filter and a low power, compact, high-speed inverter-based amplifier designed in 28nm… (more)

Subjects/Keywords: Sigma Delta; ADC; loop filter

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APA (6th Edition):

Zhan, X. (. (2018). A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652

Chicago Manual of Style (16th Edition):

Zhan, Xin (author). “A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC.” 2018. Masters Thesis, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652.

MLA Handbook (7th Edition):

Zhan, Xin (author). “A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC.” 2018. Web. 01 Oct 2020.

Vancouver:

Zhan X(. A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652.

Council of Science Editors:

Zhan X(. A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652


California State University – Sacramento

21. Thouta, Santosh Kumar. Mono to stereo synthesizer implementation on FPGA.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 The main objective of this project is to design a synthesizer that can convert mono audio signal into stereo audio signal. This synthesizer proves to… (more)

Subjects/Keywords: DSP; ADC; Digital filter

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APA (6th Edition):

Thouta, S. K. (2011). Mono to stereo synthesizer implementation on FPGA. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/991

Chicago Manual of Style (16th Edition):

Thouta, Santosh Kumar. “Mono to stereo synthesizer implementation on FPGA.” 2011. Masters Thesis, California State University – Sacramento. Accessed October 01, 2020. http://hdl.handle.net/10211.9/991.

MLA Handbook (7th Edition):

Thouta, Santosh Kumar. “Mono to stereo synthesizer implementation on FPGA.” 2011. Web. 01 Oct 2020.

Vancouver:

Thouta SK. Mono to stereo synthesizer implementation on FPGA. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10211.9/991.

Council of Science Editors:

Thouta SK. Mono to stereo synthesizer implementation on FPGA. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/991


The Ohio State University

22. Ng, Sheung Yan. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.

Degree: PhD, Electrical and Computer Engineering, 2009, The Ohio State University

  This dissertation focuses on the circuit design techniques for an asynchronous sigma delta Analog to Digital Converter (ADC). The key advantage of this ADC(more)

Subjects/Keywords: Electrical Engineering; asynchronous sigma delta ADC; synchronous sigma delta ADC

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APA (6th Edition):

Ng, S. Y. (2009). A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906

Chicago Manual of Style (16th Edition):

Ng, Sheung Yan. “A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.” 2009. Doctoral Dissertation, The Ohio State University. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

MLA Handbook (7th Edition):

Ng, Sheung Yan. “A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.” 2009. Web. 01 Oct 2020.

Vancouver:

Ng SY. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. [Internet] [Doctoral dissertation]. The Ohio State University; 2009. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

Council of Science Editors:

Ng SY. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. [Doctoral Dissertation]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906


Wright State University

23. Wang, Mingzhen. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.

Degree: PhD, Engineering PhD, 2007, Wright State University

 Wang, Mingzhen, Ph.D, Engineering Ph.D Program, Department of Electrical Engineering, Wright State University, 2007. High-Speed Low-Voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip With… (more)

Subjects/Keywords: tmp_output; ADC; flash ADC; CLK; CMOS; Outputs; comparator

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APA (6th Edition):

Wang, M. (2007). High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482

Chicago Manual of Style (16th Edition):

Wang, Mingzhen. “High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.” 2007. Doctoral Dissertation, Wright State University. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

MLA Handbook (7th Edition):

Wang, Mingzhen. “High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.” 2007. Web. 01 Oct 2020.

Vancouver:

Wang M. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. [Internet] [Doctoral dissertation]. Wright State University; 2007. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

Council of Science Editors:

Wang M. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. [Doctoral Dissertation]. Wright State University; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482


NSYSU

24. Huang, Hui-wen. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage… (more)

Subjects/Keywords: Dynamic Comparator; Bootstrapped Switch; Successive Approximation ADC; Binary Search ADC

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APA (6th Edition):

Huang, H. (2015). A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed October 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 01 Oct 2020.

Vancouver:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Oct 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

25. Castro Scorsi, Rafael. A data interface for ultra high speed ADC integrated circuits.

Degree: MSin Engineering, Electrical and Computer Engineering, 2011, University of Texas – Austin

 Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in… (more)

Subjects/Keywords: High speed ADC; 10 gigabit ethernet; ADC interface

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APA (6th Edition):

Castro Scorsi, R. (2011). A data interface for ultra high speed ADC integrated circuits. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/22769

Chicago Manual of Style (16th Edition):

Castro Scorsi, Rafael. “A data interface for ultra high speed ADC integrated circuits.” 2011. Masters Thesis, University of Texas – Austin. Accessed October 01, 2020. http://hdl.handle.net/2152/22769.

MLA Handbook (7th Edition):

Castro Scorsi, Rafael. “A data interface for ultra high speed ADC integrated circuits.” 2011. Web. 01 Oct 2020.

Vancouver:

Castro Scorsi R. A data interface for ultra high speed ADC integrated circuits. [Internet] [Masters thesis]. University of Texas – Austin; 2011. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/2152/22769.

Council of Science Editors:

Castro Scorsi R. A data interface for ultra high speed ADC integrated circuits. [Masters Thesis]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/22769


Duke University

26. Aleksanyan, Arnak. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .

Degree: 2011, Duke University

  Many medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto… (more)

Subjects/Keywords: Electrical Engineering; delta-sigma adc; low power sensor; programmable adc; rfid

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APA (6th Edition):

Aleksanyan, A. (2011). Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/3956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aleksanyan, Arnak. “Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .” 2011. Thesis, Duke University. Accessed October 01, 2020. http://hdl.handle.net/10161/3956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aleksanyan, Arnak. “Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .” 2011. Web. 01 Oct 2020.

Vancouver:

Aleksanyan A. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . [Internet] [Thesis]. Duke University; 2011. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10161/3956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aleksanyan A. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . [Thesis]. Duke University; 2011. Available from: http://hdl.handle.net/10161/3956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

27. Lim, Yong. Energy Efficient Pipeline ADCs Using Ring Amplifiers.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the… (more)

Subjects/Keywords: Ring Amplifier; Analog to Digital Converter; Pipeline ADC; Switched Capacitor; Energy Efficient ADC; Low Power ADC; Electrical Engineering; Engineering

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APA (6th Edition):

Lim, Y. (2017). Energy Efficient Pipeline ADCs Using Ring Amplifiers. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138759

Chicago Manual of Style (16th Edition):

Lim, Yong. “Energy Efficient Pipeline ADCs Using Ring Amplifiers.” 2017. Doctoral Dissertation, University of Michigan. Accessed October 01, 2020. http://hdl.handle.net/2027.42/138759.

MLA Handbook (7th Edition):

Lim, Yong. “Energy Efficient Pipeline ADCs Using Ring Amplifiers.” 2017. Web. 01 Oct 2020.

Vancouver:

Lim Y. Energy Efficient Pipeline ADCs Using Ring Amplifiers. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/2027.42/138759.

Council of Science Editors:

Lim Y. Energy Efficient Pipeline ADCs Using Ring Amplifiers. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138759


NSYSU

28. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed October 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 01 Oct 2020.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Oct 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

29. Larocque, Matthew. ADC and T2 response to radiotherapy in a human tumour xenograft model.

Degree: PhD, Department of Physics, 2010, University of Alberta

 A 9.4 T magnetic resonance imaging (MRI) system was used to evaluate the response of a human tumour xenograft model to radiation therapy. The apparent… (more)

Subjects/Keywords: tumour response; radiotherapy; T2; ADC; xenograft

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Larocque, M. (2010). ADC and T2 response to radiotherapy in a human tumour xenograft model. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/8c97kq49n

Chicago Manual of Style (16th Edition):

Larocque, Matthew. “ADC and T2 response to radiotherapy in a human tumour xenograft model.” 2010. Doctoral Dissertation, University of Alberta. Accessed October 01, 2020. https://era.library.ualberta.ca/files/8c97kq49n.

MLA Handbook (7th Edition):

Larocque, Matthew. “ADC and T2 response to radiotherapy in a human tumour xenograft model.” 2010. Web. 01 Oct 2020.

Vancouver:

Larocque M. ADC and T2 response to radiotherapy in a human tumour xenograft model. [Internet] [Doctoral dissertation]. University of Alberta; 2010. [cited 2020 Oct 01]. Available from: https://era.library.ualberta.ca/files/8c97kq49n.

Council of Science Editors:

Larocque M. ADC and T2 response to radiotherapy in a human tumour xenograft model. [Doctoral Dissertation]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/8c97kq49n


Oregon State University

30. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 01, 2020. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 01 Oct 2020.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709

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