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You searched for subject:( 3D monolithic integration). Showing records 1 – 30 of 18035 total matches.

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Princeton University

1. Bhattacharya, Debajit. Exploring the system hierarchy from devices to on-chip communication .

Degree: PhD, 2016, Princeton University

 FinFETs have replaced planar CMOS at and beyond the 22 nm node because of their superior short-channel behavior. Despite their significant advantages in electrostatics, FinFETs… (more)

Subjects/Keywords: 3D Monolithic integration; Capacitance extraction; FinFET; Network on chip; SRAM; TCAD

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APA (6th Edition):

Bhattacharya, D. (2016). Exploring the system hierarchy from devices to on-chip communication . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01cc08hj107

Chicago Manual of Style (16th Edition):

Bhattacharya, Debajit. “Exploring the system hierarchy from devices to on-chip communication .” 2016. Doctoral Dissertation, Princeton University. Accessed January 29, 2020. http://arks.princeton.edu/ark:/88435/dsp01cc08hj107.

MLA Handbook (7th Edition):

Bhattacharya, Debajit. “Exploring the system hierarchy from devices to on-chip communication .” 2016. Web. 29 Jan 2020.

Vancouver:

Bhattacharya D. Exploring the system hierarchy from devices to on-chip communication . [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2020 Jan 29]. Available from: http://arks.princeton.edu/ark:/88435/dsp01cc08hj107.

Council of Science Editors:

Bhattacharya D. Exploring the system hierarchy from devices to on-chip communication . [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp01cc08hj107


Princeton University

2. Yu, Ye. Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing .

Degree: PhD, 2019, Princeton University

 More transistors are integrated within the same footprint area as the technology node shrinks to deliver higher performance. However, this is accompanied by higher power… (more)

Subjects/Keywords: Deep learning; FinFET; Heterogeneous architecture; Monolithic 3D integration; Neural network

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APA (6th Edition):

Yu, Y. (2019). Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01r781wj908

Chicago Manual of Style (16th Edition):

Yu, Ye. “Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing .” 2019. Doctoral Dissertation, Princeton University. Accessed January 29, 2020. http://arks.princeton.edu/ark:/88435/dsp01r781wj908.

MLA Handbook (7th Edition):

Yu, Ye. “Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing .” 2019. Web. 29 Jan 2020.

Vancouver:

Yu Y. Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing . [Internet] [Doctoral dissertation]. Princeton University; 2019. [cited 2020 Jan 29]. Available from: http://arks.princeton.edu/ark:/88435/dsp01r781wj908.

Council of Science Editors:

Yu Y. Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing . [Doctoral Dissertation]. Princeton University; 2019. Available from: http://arks.princeton.edu/ark:/88435/dsp01r781wj908

3. Ayres de sousa, Alexandre. Intégration monolithique en 3D : étude du potentiel en termes de consommation, performance et surface pour le nœud technologique 14nm et au-delà : 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Grenoble Alpes

L'intégration 3DVLSI, également connue sous le nom d'intégration monolithique ou séquentielle, est présentée et évaluée dans cette thèse comme une alternative à la réduction du… (more)

Subjects/Keywords: Intégration monolithique en 3D; Cps; Variabilité du circuit 3D; Modèle Statistique Unifié pour la 3D; Recommandations pour le Design 3D; Simulations 3D avec SPICE; 3D Monolithic Integration; Ppa; 3D circuit variability; 3D Unified Statistical Model; 3D Design Guidelines; 3D SPICE simulations; 620

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APA (6th Edition):

Ayres de sousa, A. (2017). Intégration monolithique en 3D : étude du potentiel en termes de consommation, performance et surface pour le nœud technologique 14nm et au-delà : 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT065

Chicago Manual of Style (16th Edition):

Ayres de sousa, Alexandre. “Intégration monolithique en 3D : étude du potentiel en termes de consommation, performance et surface pour le nœud technologique 14nm et au-delà : 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed January 29, 2020. http://www.theses.fr/2017GREAT065.

MLA Handbook (7th Edition):

Ayres de sousa, Alexandre. “Intégration monolithique en 3D : étude du potentiel en termes de consommation, performance et surface pour le nœud technologique 14nm et au-delà : 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond.” 2017. Web. 29 Jan 2020.

Vancouver:

Ayres de sousa A. Intégration monolithique en 3D : étude du potentiel en termes de consommation, performance et surface pour le nœud technologique 14nm et au-delà : 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2017GREAT065.

Council of Science Editors:

Ayres de sousa A. Intégration monolithique en 3D : étude du potentiel en termes de consommation, performance et surface pour le nœud technologique 14nm et au-delà : 3D Monolithic Integration : performance, Power and Area Evaluation for 14nm and beyond. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT065


Université de Sherbrooke

4. Lee Sang, Bruno. Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS .

Degree: 2016, Université de Sherbrooke

 Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais… (more)

Subjects/Keywords: Transistor monoélectronique (SET); CMOS; Intégration 3D monolithique; BEOL; Gravure plasma; Électrolithographie; Nanodamascène; Nanofabrication; Single electron transistor (SET); 3D monolithic integration; Plasma etching; Electrolithography; Nanodamascene

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APA (6th Edition):

Lee Sang, B. (2016). Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/8955

Chicago Manual of Style (16th Edition):

Lee Sang, Bruno. “Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS .” 2016. Doctoral Dissertation, Université de Sherbrooke. Accessed January 29, 2020. http://hdl.handle.net/11143/8955.

MLA Handbook (7th Edition):

Lee Sang, Bruno. “Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS .” 2016. Web. 29 Jan 2020.

Vancouver:

Lee Sang B. Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/11143/8955.

Council of Science Editors:

Lee Sang B. Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS . [Doctoral Dissertation]. Université de Sherbrooke; 2016. Available from: http://hdl.handle.net/11143/8955


Université de Grenoble

5. Turkyilmaz, Ogun. Emerging 3D technologies for efficient implementation of FPGAs : Implémentation de FPGA en utilisant des technologies 3D émergentes.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Université de Grenoble

La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison… (more)

Subjects/Keywords: FPGA; Monolithic integration; Logique; Mémoire résistive; FPGA; Monolithic integration; Logic; Resistive memory; 620

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APA (6th Edition):

Turkyilmaz, O. (2014). Emerging 3D technologies for efficient implementation of FPGAs : Implémentation de FPGA en utilisant des technologies 3D émergentes. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT091

Chicago Manual of Style (16th Edition):

Turkyilmaz, Ogun. “Emerging 3D technologies for efficient implementation of FPGAs : Implémentation de FPGA en utilisant des technologies 3D émergentes.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed January 29, 2020. http://www.theses.fr/2014GRENT091.

MLA Handbook (7th Edition):

Turkyilmaz, Ogun. “Emerging 3D technologies for efficient implementation of FPGAs : Implémentation de FPGA en utilisant des technologies 3D émergentes.” 2014. Web. 29 Jan 2020.

Vancouver:

Turkyilmaz O. Emerging 3D technologies for efficient implementation of FPGAs : Implémentation de FPGA en utilisant des technologies 3D émergentes. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2014GRENT091.

Council of Science Editors:

Turkyilmaz O. Emerging 3D technologies for efficient implementation of FPGAs : Implémentation de FPGA en utilisant des technologies 3D émergentes. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT091


Université de Sherbrooke

6. Labalette, Marina. Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS .

Degree: 2018, Université de Sherbrooke

 Les dispositifs mémoires résistives, notamment ceux à base d’oxyde de commutation OxRRAM, se placent parmi les dispositifs mémoires émergentes les plus attractifs pour remplacer les… (more)

Subjects/Keywords: Filière CMOS; Mémoires résistives OxRRAM; Dispositifs CRS; Intégration monolithique BEOL; Caractérisations en mode QS et pulsé; Architecture mémoire haute densité; Configuration 1T1R; Oxide based resistive memories OxRRAM; CRS dispositive; CMOS BEOL; 3D monolithic integration; DC and pulsed electrical characterization; High density of integration; 1T1R configuration

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APA (6th Edition):

Labalette, M. (2018). Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/12267

Chicago Manual of Style (16th Edition):

Labalette, Marina. “Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS .” 2018. Doctoral Dissertation, Université de Sherbrooke. Accessed January 29, 2020. http://hdl.handle.net/11143/12267.

MLA Handbook (7th Edition):

Labalette, Marina. “Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS .” 2018. Web. 29 Jan 2020.

Vancouver:

Labalette M. Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2018. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/11143/12267.

Council of Science Editors:

Labalette M. Intégration 3D de mémoires résistives complémentaires dans le back-end-of-line du CMOS . [Doctoral Dissertation]. Université de Sherbrooke; 2018. Available from: http://hdl.handle.net/11143/12267


University College Cork

7. Duggan, Shane P. Regrowth-free monolithic vertical integration of passive and active waveguides.

Degree: 2019, University College Cork

 Data usage continues to rise exponentially with user demand, and the bandwidth of optical communications is reaching its limit. Spectrally efficient advanced modulation formats are… (more)

Subjects/Keywords: Monolithic integration; Regrowth-free integration; Photonic integration; Lasers; Waveguides; Photonic integrated circuits; Optoelectronics

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APA (6th Edition):

Duggan, S. P. (2019). Regrowth-free monolithic vertical integration of passive and active waveguides. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/7973

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Duggan, Shane P. “Regrowth-free monolithic vertical integration of passive and active waveguides.” 2019. Thesis, University College Cork. Accessed January 29, 2020. http://hdl.handle.net/10468/7973.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Duggan, Shane P. “Regrowth-free monolithic vertical integration of passive and active waveguides.” 2019. Web. 29 Jan 2020.

Vancouver:

Duggan SP. Regrowth-free monolithic vertical integration of passive and active waveguides. [Internet] [Thesis]. University College Cork; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10468/7973.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Duggan SP. Regrowth-free monolithic vertical integration of passive and active waveguides. [Thesis]. University College Cork; 2019. Available from: http://hdl.handle.net/10468/7973

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

8. Arbabi, Amir. Selective mode coupling in microring resonators for single mode semiconductor lasers.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 Single mode semiconductor laser diodes have many applications in optical communications, metrology and sensing. Edge-emitting single mode lasers commonly use distributed feedback structures, or narrowband… (more)

Subjects/Keywords: On-chip mirrors; Semiconductor lasers; Micro-resonators; Monolithic integration

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APA (6th Edition):

Arbabi, A. (2013). Selective mode coupling in microring resonators for single mode semiconductor lasers. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/45565

Chicago Manual of Style (16th Edition):

Arbabi, Amir. “Selective mode coupling in microring resonators for single mode semiconductor lasers.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 29, 2020. http://hdl.handle.net/2142/45565.

MLA Handbook (7th Edition):

Arbabi, Amir. “Selective mode coupling in microring resonators for single mode semiconductor lasers.” 2013. Web. 29 Jan 2020.

Vancouver:

Arbabi A. Selective mode coupling in microring resonators for single mode semiconductor lasers. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2142/45565.

Council of Science Editors:

Arbabi A. Selective mode coupling in microring resonators for single mode semiconductor lasers. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/45565


Université de Sherbrooke

9. Ayadi, Yosri. 3D integration of single electron transistors in the Back-End-Of-Line of 28 nm CMOS technology for the development of ultra-low power sensors .

Degree: 2017, Université de Sherbrooke

 La forte demande et le besoin d’intégration hétérogène de nouvelles fonctionnalités dans les systèmes mobiles et autonomes, tels que les mémoires, capteurs, et interfaces de… (more)

Subjects/Keywords: Single electron transistors; 3D monolithic integration; FET-based gas sensors; Gas sensing; Hydrogen detection; MW-CNT networks; Ultra-low power; FDSOI; Double gate-SET; Double gate-FET; Sensing layer texturing; Transistors monoélectroniques; Intégration 3D monolithique; Capteur de gaz à base de FET; Capteur de gaz; Détection du dihydrogène; Texturation de surface de la couche sensible; Réseaux de MW-CNTs; Ultra-basse consommation

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APA (6th Edition):

Ayadi, Y. (2017). 3D integration of single electron transistors in the Back-End-Of-Line of 28 nm CMOS technology for the development of ultra-low power sensors . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/10122

Chicago Manual of Style (16th Edition):

Ayadi, Yosri. “3D integration of single electron transistors in the Back-End-Of-Line of 28 nm CMOS technology for the development of ultra-low power sensors .” 2017. Doctoral Dissertation, Université de Sherbrooke. Accessed January 29, 2020. http://hdl.handle.net/11143/10122.

MLA Handbook (7th Edition):

Ayadi, Yosri. “3D integration of single electron transistors in the Back-End-Of-Line of 28 nm CMOS technology for the development of ultra-low power sensors .” 2017. Web. 29 Jan 2020.

Vancouver:

Ayadi Y. 3D integration of single electron transistors in the Back-End-Of-Line of 28 nm CMOS technology for the development of ultra-low power sensors . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2017. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/11143/10122.

Council of Science Editors:

Ayadi Y. 3D integration of single electron transistors in the Back-End-Of-Line of 28 nm CMOS technology for the development of ultra-low power sensors . [Doctoral Dissertation]. Université de Sherbrooke; 2017. Available from: http://hdl.handle.net/11143/10122

10. Ayadi, Yosri. 3D integration of single electron transistors in the back-end-of-line of 28 nm CMOS technology for the development of ultra-low power sensors : Intégration 3D de dispositifs SETs dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation.

Degree: Docteur es, Electronique, électrotechnique, automatique, 2016, Lyon; Université de Sherbrooke (Québec, Canada)

Les systèmes mobiles intelligents sont déjà dotés de plusieurs composants de type capteur comme les accéléromètres, les thermomètres et les détecteurs infrarouge. Cependant, jusqu’à aujourd’hui… (more)

Subjects/Keywords: Electronique; Capteur; Transistor mono-Électroniques - SET; Intégration 3D monolithique; Capteur de gaz à base de FET; Capteur de gaz; Détection de dihydrogène; Ultra-Basse consommation; Texturation de surface de la couche sensible; Réseaux de MW-CNTs; Electronics; Sensors; SET - Single Electron Transistor; 3D monolithic integration; FET-Based gas sensor; Hydrogen detection; Sensing layer texturing; MW-CNT networks; 621.370 72

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APA (6th Edition):

Ayadi, Y. (2016). 3D integration of single electron transistors in the back-end-of-line of 28 nm CMOS technology for the development of ultra-low power sensors : Intégration 3D de dispositifs SETs dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation. (Doctoral Dissertation). Lyon; Université de Sherbrooke (Québec, Canada). Retrieved from http://www.theses.fr/2016LYSEI155

Chicago Manual of Style (16th Edition):

Ayadi, Yosri. “3D integration of single electron transistors in the back-end-of-line of 28 nm CMOS technology for the development of ultra-low power sensors : Intégration 3D de dispositifs SETs dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation.” 2016. Doctoral Dissertation, Lyon; Université de Sherbrooke (Québec, Canada). Accessed January 29, 2020. http://www.theses.fr/2016LYSEI155.

MLA Handbook (7th Edition):

Ayadi, Yosri. “3D integration of single electron transistors in the back-end-of-line of 28 nm CMOS technology for the development of ultra-low power sensors : Intégration 3D de dispositifs SETs dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation.” 2016. Web. 29 Jan 2020.

Vancouver:

Ayadi Y. 3D integration of single electron transistors in the back-end-of-line of 28 nm CMOS technology for the development of ultra-low power sensors : Intégration 3D de dispositifs SETs dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation. [Internet] [Doctoral dissertation]. Lyon; Université de Sherbrooke (Québec, Canada); 2016. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2016LYSEI155.

Council of Science Editors:

Ayadi Y. 3D integration of single electron transistors in the back-end-of-line of 28 nm CMOS technology for the development of ultra-low power sensors : Intégration 3D de dispositifs SETs dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation. [Doctoral Dissertation]. Lyon; Université de Sherbrooke (Québec, Canada); 2016. Available from: http://www.theses.fr/2016LYSEI155

11. Piccolboni, Giuseppe. Etude et intégration de mémoires résistives 3D pour application haute densité : Study and integration of 3D resistive memories for high density application.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2016, Grenoble Alpes

 Le but de cette thèse était de caractériser et d’aider au développement des premières mémoires résistives verticales (VRRAM) fabriquées au LETI. Parmi les mémoires émergentes,… (more)

Subjects/Keywords: Memoires; Resistives; Integration; 3d; Memories; Resistive; Integration; 3d; 620

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APA (6th Edition):

Piccolboni, G. (2016). Etude et intégration de mémoires résistives 3D pour application haute densité : Study and integration of 3D resistive memories for high density application. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2016GREAT062

Chicago Manual of Style (16th Edition):

Piccolboni, Giuseppe. “Etude et intégration de mémoires résistives 3D pour application haute densité : Study and integration of 3D resistive memories for high density application.” 2016. Doctoral Dissertation, Grenoble Alpes. Accessed January 29, 2020. http://www.theses.fr/2016GREAT062.

MLA Handbook (7th Edition):

Piccolboni, Giuseppe. “Etude et intégration de mémoires résistives 3D pour application haute densité : Study and integration of 3D resistive memories for high density application.” 2016. Web. 29 Jan 2020.

Vancouver:

Piccolboni G. Etude et intégration de mémoires résistives 3D pour application haute densité : Study and integration of 3D resistive memories for high density application. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2016. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2016GREAT062.

Council of Science Editors:

Piccolboni G. Etude et intégration de mémoires résistives 3D pour application haute densité : Study and integration of 3D resistive memories for high density application. [Doctoral Dissertation]. Grenoble Alpes; 2016. Available from: http://www.theses.fr/2016GREAT062

12. Sarhan, Hossam. Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Grenoble Alpes

L'impact des interconnections d'un circuit intégré sur les performances et la consommation est de plus en plus important à partir du nœud CMOS 28 nm… (more)

Subjects/Keywords: 3D IC; Monolithique 3D; Méthodologie de conception; 3D haute densité; Architecture; Évaluation des technologies; 3D IC; Monolithic 3D; Design methodology; High density 3D; Architecture; Technololgy assessment; 620

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APA (6th Edition):

Sarhan, H. (2015). Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT134

Chicago Manual of Style (16th Edition):

Sarhan, Hossam. “Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed January 29, 2020. http://www.theses.fr/2015GREAT134.

MLA Handbook (7th Edition):

Sarhan, Hossam. “Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité.” 2015. Web. 29 Jan 2020.

Vancouver:

Sarhan H. Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2015GREAT134.

Council of Science Editors:

Sarhan H. Design methodology and technology assessment for high-desnity 3D technologies : Méthodologie de conception et de l'évaluation des technologies 3D haute densité. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT134


University of Illinois – Urbana-Champaign

13. Gopi Reddy, Bhargava Reddy. Energy efficient core designs for upcoming process technologies.

Degree: PhD, Computer Science, 2019, University of Illinois – Urbana-Champaign

 Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are… (more)

Subjects/Keywords: Energy efficient architecture; TFET; Monolithic 3D; ScalCore; HetCore; Microarchitecture; Processor; CPU; Low Voltage

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APA (6th Edition):

Gopi Reddy, B. R. (2019). Energy efficient core designs for upcoming process technologies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104832

Chicago Manual of Style (16th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 29, 2020. http://hdl.handle.net/2142/104832.

MLA Handbook (7th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Web. 29 Jan 2020.

Vancouver:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2142/104832.

Council of Science Editors:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104832


Duke University

14. Koneru, Abhishek. Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits .

Degree: 2019, Duke University

  Three-dimensional (3D) integration is a promising way to sustain Moore's Law beyond device- and interconnect-scaling limits. 3D technologies enable the integration of heterogeneous fabrication… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Design-for-Testability; Fault Modeling; Monolithic 3D; Optimization; Power Delivery; Testing

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APA (6th Edition):

Koneru, A. (2019). Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/18664

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Koneru, Abhishek. “Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits .” 2019. Thesis, Duke University. Accessed January 29, 2020. http://hdl.handle.net/10161/18664.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Koneru, Abhishek. “Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits .” 2019. Web. 29 Jan 2020.

Vancouver:

Koneru A. Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits . [Internet] [Thesis]. Duke University; 2019. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10161/18664.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Koneru A. Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits . [Thesis]. Duke University; 2019. Available from: http://hdl.handle.net/10161/18664

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Yang, Ping-Lin. Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security.

Degree: 2017, University of California – eScholarship, University of California

 With the continuous demands on integrating more functions and devices on a single chip, the technology has been evolving along the scaling path for decades.… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Engineering; 3D IC; Dynamic Reconfigurable Computing; Hardware Security; Monolithic 3D; Physical Design; VeSFET

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APA (6th Edition):

Yang, P. (2017). Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/5s9833kz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Ping-Lin. “Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security.” 2017. Thesis, University of California – eScholarship, University of California. Accessed January 29, 2020. http://www.escholarship.org/uc/item/5s9833kz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Ping-Lin. “Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security.” 2017. Web. 29 Jan 2020.

Vancouver:

Yang P. Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security. [Internet] [Thesis]. University of California – eScholarship, University of California; 2017. [cited 2020 Jan 29]. Available from: http://www.escholarship.org/uc/item/5s9833kz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang P. Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security. [Thesis]. University of California – eScholarship, University of California; 2017. Available from: http://www.escholarship.org/uc/item/5s9833kz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Kiihamäki, Jyrki. Fabrication of SOI Micromechanical Devices.

Degree: 2005, VTT Technical Research Centre of Finland

This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single… (more)

Subjects/Keywords: silicon-on-insulator; SOI; micromechanics; MEMS; microfabrication; HARMST; DRIE; etching; vacuum cavities; resonators; monolithic integration

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APA (6th Edition):

Kiihamäki, J. (2005). Fabrication of SOI Micromechanical Devices. (Thesis). VTT Technical Research Centre of Finland. Retrieved from http://lib.tkk.fi/Diss/2005/isbn9513864367/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kiihamäki, Jyrki. “Fabrication of SOI Micromechanical Devices.” 2005. Thesis, VTT Technical Research Centre of Finland. Accessed January 29, 2020. http://lib.tkk.fi/Diss/2005/isbn9513864367/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kiihamäki, Jyrki. “Fabrication of SOI Micromechanical Devices.” 2005. Web. 29 Jan 2020.

Vancouver:

Kiihamäki J. Fabrication of SOI Micromechanical Devices. [Internet] [Thesis]. VTT Technical Research Centre of Finland; 2005. [cited 2020 Jan 29]. Available from: http://lib.tkk.fi/Diss/2005/isbn9513864367/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kiihamäki J. Fabrication of SOI Micromechanical Devices. [Thesis]. VTT Technical Research Centre of Finland; 2005. Available from: http://lib.tkk.fi/Diss/2005/isbn9513864367/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Santa Cruz

17. Risbud, Dilip M. Design And Fabrication Of A Monolithically Integrated Thermal Self-Protection Circuit With A High Voltage GaN-on-Si Power Hemt.

Degree: Electrical Engineering, 2016, University of California – Santa Cruz

 AbstractDilip M. RisbudDESIGN AND FABRICATION OF A MONOLITHICALLY INTEGRATEDTHERMAL SELF-PROTECTION CIRCUIT WITH A HIGH VOLTAGEGaN-on-Si POWER HEMTIn recent years, significant progress has been made in… (more)

Subjects/Keywords: Electrical engineering; Physics; Materials Science; GaN-on-Silicon; GaN power HEMT; Monolithic integration; Schottky

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APA (6th Edition):

Risbud, D. M. (2016). Design And Fabrication Of A Monolithically Integrated Thermal Self-Protection Circuit With A High Voltage GaN-on-Si Power Hemt. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/5sz2q2q1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Risbud, Dilip M. “Design And Fabrication Of A Monolithically Integrated Thermal Self-Protection Circuit With A High Voltage GaN-on-Si Power Hemt.” 2016. Thesis, University of California – Santa Cruz. Accessed January 29, 2020. http://www.escholarship.org/uc/item/5sz2q2q1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Risbud, Dilip M. “Design And Fabrication Of A Monolithically Integrated Thermal Self-Protection Circuit With A High Voltage GaN-on-Si Power Hemt.” 2016. Web. 29 Jan 2020.

Vancouver:

Risbud DM. Design And Fabrication Of A Monolithically Integrated Thermal Self-Protection Circuit With A High Voltage GaN-on-Si Power Hemt. [Internet] [Thesis]. University of California – Santa Cruz; 2016. [cited 2020 Jan 29]. Available from: http://www.escholarship.org/uc/item/5sz2q2q1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Risbud DM. Design And Fabrication Of A Monolithically Integrated Thermal Self-Protection Circuit With A High Voltage GaN-on-Si Power Hemt. [Thesis]. University of California – Santa Cruz; 2016. Available from: http://www.escholarship.org/uc/item/5sz2q2q1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

18. Chen, Paul Cheng Po. Integration of Photodetectors and Optical Receiver .

Degree: 2008, Cornell University

 As computing systems and communication networks grow more complex, so is the need for higher bandwidth data links. Optical interconnect promises to offer lowercost, high-bandwidth… (more)

Subjects/Keywords: Optical Receiver; Monolithic; CMOS Integration; Phototransistor

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APA (6th Edition):

Chen, P. C. P. (2008). Integration of Photodetectors and Optical Receiver . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/11623

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Paul Cheng Po. “Integration of Photodetectors and Optical Receiver .” 2008. Thesis, Cornell University. Accessed January 29, 2020. http://hdl.handle.net/1813/11623.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Paul Cheng Po. “Integration of Photodetectors and Optical Receiver .” 2008. Web. 29 Jan 2020.

Vancouver:

Chen PCP. Integration of Photodetectors and Optical Receiver . [Internet] [Thesis]. Cornell University; 2008. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1813/11623.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen PCP. Integration of Photodetectors and Optical Receiver . [Thesis]. Cornell University; 2008. Available from: http://hdl.handle.net/1813/11623

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

19. Kim, Hyunseok. III-V semiconductor nanowire lasers on silicon.

Degree: Electrical Engineering, 2018, UCLA

 Chip-scale integrated light sources are a crucial component in a broad range of photonics applications. III-V semiconductor nanowire emitters have gained attention as a fascinating… (more)

Subjects/Keywords: Electrical engineering; Optics; Nanotechnology; Monolithic integration; Nanowire laser; Optical interconnects; Photonic crystal; Silicon photonics

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APA (6th Edition):

Kim, H. (2018). III-V semiconductor nanowire lasers on silicon. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/2sv8m0b7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hyunseok. “III-V semiconductor nanowire lasers on silicon.” 2018. Thesis, UCLA. Accessed January 29, 2020. http://www.escholarship.org/uc/item/2sv8m0b7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hyunseok. “III-V semiconductor nanowire lasers on silicon.” 2018. Web. 29 Jan 2020.

Vancouver:

Kim H. III-V semiconductor nanowire lasers on silicon. [Internet] [Thesis]. UCLA; 2018. [cited 2020 Jan 29]. Available from: http://www.escholarship.org/uc/item/2sv8m0b7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim H. III-V semiconductor nanowire lasers on silicon. [Thesis]. UCLA; 2018. Available from: http://www.escholarship.org/uc/item/2sv8m0b7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Coudron, Loïc. Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via.

Degree: Docteur es, Electronique, 2011, Université François-Rabelais de Tours

Ces travaux de thèse ont pour but l’évaluation et le développement de briques technologiques en silicium poreux répondant à la problématique de l’intégration monolithique 3D(more)

Subjects/Keywords: Procédés de gravure électrochimique; Intégration monolithique; Composants passifs; Porous silicon; Anodization; Electrochemical etching; Monolithic integration

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APA (6th Edition):

Coudron, L. (2011). Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via. (Doctoral Dissertation). Université François-Rabelais de Tours. Retrieved from http://www.theses.fr/2011TOUR4028

Chicago Manual of Style (16th Edition):

Coudron, Loïc. “Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via.” 2011. Doctoral Dissertation, Université François-Rabelais de Tours. Accessed January 29, 2020. http://www.theses.fr/2011TOUR4028.

MLA Handbook (7th Edition):

Coudron, Loïc. “Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via.” 2011. Web. 29 Jan 2020.

Vancouver:

Coudron L. Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via. [Internet] [Doctoral dissertation]. Université François-Rabelais de Tours; 2011. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2011TOUR4028.

Council of Science Editors:

Coudron L. Etude des procédés de gravure électrochimique du silicium pour l'intégration monolithique de composants passifs sur silicium poreux et la réalisation de chemins d'interconnexion : Study of silicon electrochemical etching process for monolithic integration of passive components on porous silicon and for the realization of through silicon via. [Doctoral Dissertation]. Université François-Rabelais de Tours; 2011. Available from: http://www.theses.fr/2011TOUR4028


University of Michigan

21. Wu, Fan. Implantable Neural Probes for Electrical Recording and Optical Stimulation of Cellular Level Neural Circuitry in Behaving Animals.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 In order to advance the understanding of brain function, it is critical to monitor how neural circuits work together and perform computational processing. For the… (more)

Subjects/Keywords: Neural probe; Optogenetics; Silk coating; Semiconductor LED; Monolithic integration; Electrical Engineering; Engineering

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APA (6th Edition):

Wu, F. (2015). Implantable Neural Probes for Electrical Recording and Optical Stimulation of Cellular Level Neural Circuitry in Behaving Animals. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/111604

Chicago Manual of Style (16th Edition):

Wu, Fan. “Implantable Neural Probes for Electrical Recording and Optical Stimulation of Cellular Level Neural Circuitry in Behaving Animals.” 2015. Doctoral Dissertation, University of Michigan. Accessed January 29, 2020. http://hdl.handle.net/2027.42/111604.

MLA Handbook (7th Edition):

Wu, Fan. “Implantable Neural Probes for Electrical Recording and Optical Stimulation of Cellular Level Neural Circuitry in Behaving Animals.” 2015. Web. 29 Jan 2020.

Vancouver:

Wu F. Implantable Neural Probes for Electrical Recording and Optical Stimulation of Cellular Level Neural Circuitry in Behaving Animals. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2027.42/111604.

Council of Science Editors:

Wu F. Implantable Neural Probes for Electrical Recording and Optical Stimulation of Cellular Level Neural Circuitry in Behaving Animals. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/111604


NSYSU

22. Huang, Tzu-Ming. SoC Integration and Verification of a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 While consumer demand for electronic equipment and more mature systems integration capabilities, it makes the system complexity of chip design increasing significantly. Also accompany an… (more)

Subjects/Keywords: Verification; Bus Bridge; SoC; 3D Graphics; Integration

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APA (6th Edition):

Huang, T. (2011). SoC Integration and Verification of a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Tzu-Ming. “SoC Integration and Verification of a 3D Graphics SoC.” 2011. Thesis, NSYSU. Accessed January 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Tzu-Ming. “SoC Integration and Verification of a 3D Graphics SoC.” 2011. Web. 29 Jan 2020.

Vancouver:

Huang T. SoC Integration and Verification of a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Jan 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang T. SoC Integration and Verification of a 3D Graphics SoC. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Grenoble

23. Bertheau, Julien. Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs : Study and characterization of intermetallics interconnections as CuSn for 3D stacking components application.

Degree: Docteur es, Matériaux, mécanique, génie civil, électrochimie, 2014, Université de Grenoble

Les objectifs technologiques de l'industrie de la microélectronique sont largement dictés par la loi de Moore qui vise une réduction permanente de la taille des… (more)

Subjects/Keywords: Interconnexion; Intermetallique; Integration 3D; Pillier de cuivre; Interconnection; Intermetallic; 3D integration; Copper pillars; 620

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APA (6th Edition):

Bertheau, J. (2014). Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs : Study and characterization of intermetallics interconnections as CuSn for 3D stacking components application. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENI043

Chicago Manual of Style (16th Edition):

Bertheau, Julien. “Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs : Study and characterization of intermetallics interconnections as CuSn for 3D stacking components application.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed January 29, 2020. http://www.theses.fr/2014GRENI043.

MLA Handbook (7th Edition):

Bertheau, Julien. “Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs : Study and characterization of intermetallics interconnections as CuSn for 3D stacking components application.” 2014. Web. 29 Jan 2020.

Vancouver:

Bertheau J. Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs : Study and characterization of intermetallics interconnections as CuSn for 3D stacking components application. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2014GRENI043.

Council of Science Editors:

Bertheau J. Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs : Study and characterization of intermetallics interconnections as CuSn for 3D stacking components application. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENI043

24. Labalette, Marina. Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line.

Degree: Docteur es, Electronique, électrotechnique et automatique, 2018, Lyon; Université de Sherbrooke (Québec, Canada)

La gestion, la manipulation et le stockage de données sont aujourd’hui de réels challenges. Pour supporter cette réalité, le besoin de technologies mémoires plus efficaces,… (more)

Subjects/Keywords: Electronique; Microélectronique; Mémoires en microélectronique; Filière CMOS; Mémoires résistives OxRRAM; Mémoires resistives complémentaires - CRS; Intégration monolithique BEOL - back end of line; Caractérisation électrique en mode quasi statique - QS; Caractérisation électrique en mode pulsé; Architecture de mémoire haute densité; Configuration 1T1R; Procédé nanodamascène; Electronics; Microelectronics; Memory on Silicon; Oxide based resistive memories OxRRAM; Complementary resistive switching devices - CRS; Cmos beol; 3D monolithic integration; DC and pulsed electrical characterization; High density integration; 1T1R configuration; 621.397 072

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APA (6th Edition):

Labalette, M. (2018). Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line. (Doctoral Dissertation). Lyon; Université de Sherbrooke (Québec, Canada). Retrieved from http://www.theses.fr/2018LYSEI037

Chicago Manual of Style (16th Edition):

Labalette, Marina. “Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line.” 2018. Doctoral Dissertation, Lyon; Université de Sherbrooke (Québec, Canada). Accessed January 29, 2020. http://www.theses.fr/2018LYSEI037.

MLA Handbook (7th Edition):

Labalette, Marina. “Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line.” 2018. Web. 29 Jan 2020.

Vancouver:

Labalette M. Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line. [Internet] [Doctoral dissertation]. Lyon; Université de Sherbrooke (Québec, Canada); 2018. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2018LYSEI037.

Council of Science Editors:

Labalette M. Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS : 3D integration of complementary resistive switching devices in CMOS back end of line. [Doctoral Dissertation]. Lyon; Université de Sherbrooke (Québec, Canada); 2018. Available from: http://www.theses.fr/2018LYSEI037


Virginia Tech

25. Ralston, Parrish Elaine. Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.

Degree: PhD, Electrical Engineering, 2013, Virginia Tech

 Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in… (more)

Subjects/Keywords: liquid metal; electronics packaging; flip chip; 3D integration; MMIC integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ralston, P. E. (2013). Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50641

Chicago Manual of Style (16th Edition):

Ralston, Parrish Elaine. “Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.” 2013. Doctoral Dissertation, Virginia Tech. Accessed January 29, 2020. http://hdl.handle.net/10919/50641.

MLA Handbook (7th Edition):

Ralston, Parrish Elaine. “Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.” 2013. Web. 29 Jan 2020.

Vancouver:

Ralston PE. Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10919/50641.

Council of Science Editors:

Ralston PE. Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/50641

26. TEO HONG HAI. 3-Dimenstional microstructural fabrication of foturanTM glass with femtosecond laser irradiation.

Degree: 2009, National University of Singapore

Subjects/Keywords: 3D; Multi-level; Monolithic; Microstructural fabrication; Foturan; Femtosecond laser

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APA (6th Edition):

HAI, T. H. (2009). 3-Dimenstional microstructural fabrication of foturanTM glass with femtosecond laser irradiation. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/17728

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HAI, TEO HONG. “3-Dimenstional microstructural fabrication of foturanTM glass with femtosecond laser irradiation.” 2009. Thesis, National University of Singapore. Accessed January 29, 2020. http://scholarbank.nus.edu.sg/handle/10635/17728.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HAI, TEO HONG. “3-Dimenstional microstructural fabrication of foturanTM glass with femtosecond laser irradiation.” 2009. Web. 29 Jan 2020.

Vancouver:

HAI TH. 3-Dimenstional microstructural fabrication of foturanTM glass with femtosecond laser irradiation. [Internet] [Thesis]. National University of Singapore; 2009. [cited 2020 Jan 29]. Available from: http://scholarbank.nus.edu.sg/handle/10635/17728.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HAI TH. 3-Dimenstional microstructural fabrication of foturanTM glass with femtosecond laser irradiation. [Thesis]. National University of Singapore; 2009. Available from: http://scholarbank.nus.edu.sg/handle/10635/17728

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

27. Zhou, Ying. Carbon Nanotube Synthesis on Cmos Substrate Via Localized Resistive Heating.

Degree: MS, Electrical and Computer Engineering, 2009, University of Florida

 Since their discovery, the unique properties of carbon nanotubes (CNTs) have drawn great attention, and a lot of applications have been demonstrated, such as CNT-based… (more)

Subjects/Keywords: Carbon nanotubes; Electric potential; Electrodes; Heaters; Heating; High temperature; Nanotubes; Sensors; Silicon; Temperature distribution; cmos, integration, monolithic, nanotube

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, Y. (2009). Carbon Nanotube Synthesis on Cmos Substrate Via Localized Resistive Heating. (Masters Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0025057

Chicago Manual of Style (16th Edition):

Zhou, Ying. “Carbon Nanotube Synthesis on Cmos Substrate Via Localized Resistive Heating.” 2009. Masters Thesis, University of Florida. Accessed January 29, 2020. http://ufdc.ufl.edu/UFE0025057.

MLA Handbook (7th Edition):

Zhou, Ying. “Carbon Nanotube Synthesis on Cmos Substrate Via Localized Resistive Heating.” 2009. Web. 29 Jan 2020.

Vancouver:

Zhou Y. Carbon Nanotube Synthesis on Cmos Substrate Via Localized Resistive Heating. [Internet] [Masters thesis]. University of Florida; 2009. [cited 2020 Jan 29]. Available from: http://ufdc.ufl.edu/UFE0025057.

Council of Science Editors:

Zhou Y. Carbon Nanotube Synthesis on Cmos Substrate Via Localized Resistive Heating. [Masters Thesis]. University of Florida; 2009. Available from: http://ufdc.ufl.edu/UFE0025057

28. Monnier, Nicolas. Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems.

Degree: Docteur es, Electronique, 2018, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire

Cette thèse s’inscrit dans le développement d’imageurs térahertz en technologie intégrée CMOS avec pour volonté de rendre ces derniers fiables et robustes, de permettre de… (more)

Subjects/Keywords: Térahertz; Imagerie; Pixel; Intégration; CMOS; Monolithique; Antenne; Métasurface; Terahertz; Imaging; Pixel; Integration; CMOS; Monolithic; Antenna; Metasurface; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Monnier, N. (2018). Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems. (Doctoral Dissertation). Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire. Retrieved from http://www.theses.fr/2018IMTA0070

Chicago Manual of Style (16th Edition):

Monnier, Nicolas. “Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems.” 2018. Doctoral Dissertation, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire. Accessed January 29, 2020. http://www.theses.fr/2018IMTA0070.

MLA Handbook (7th Edition):

Monnier, Nicolas. “Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems.” 2018. Web. 29 Jan 2020.

Vancouver:

Monnier N. Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems. [Internet] [Doctoral dissertation]. Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire; 2018. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2018IMTA0070.

Council of Science Editors:

Monnier N. Amélioration du traitement amont de pixels térahertz, monolithiquement intégrés en technologie CMOS, pour des systèmes d'imagerie en temps réel : Improvements on front-end terahertz pixels, monolithically integrated in CMOS technology, for real time imaging systems. [Doctoral Dissertation]. Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire; 2018. Available from: http://www.theses.fr/2018IMTA0070


Virginia Tech

29. Deng, Haifei. Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response.

Degree: PhD, Electrical and Computer Engineering, 2005, Virginia Tech

 With the electronic equipments becoming more and more complicated, the requirements for the power management are more and more strict. Efficient performance, high functionality, small… (more)

Subjects/Keywords: high frequency; switching regulator; fast transient response; Monolithic integration

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APA (6th Edition):

Deng, H. (2005). Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/26226

Chicago Manual of Style (16th Edition):

Deng, Haifei. “Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response.” 2005. Doctoral Dissertation, Virginia Tech. Accessed January 29, 2020. http://hdl.handle.net/10919/26226.

MLA Handbook (7th Edition):

Deng, Haifei. “Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response.” 2005. Web. 29 Jan 2020.

Vancouver:

Deng H. Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response. [Internet] [Doctoral dissertation]. Virginia Tech; 2005. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10919/26226.

Council of Science Editors:

Deng H. Modeling and Design of a Monolithic High Frequency Synchronous Buck with Fast Transient Response. [Doctoral Dissertation]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/26226

30. Gaillardon, Pierre-Emmanuel. Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire.

Degree: Docteur es, Dispositifs de l'électronique intégrée, 2011, Ecully, Ecole centrale de Lyon

Durant les quatre dernières décennies, l’industrie des semi-conducteurs a connu une croissance exponentielle. En accord avec l’ITRS et à mesure de l'approche vers le nanomètre,… (more)

Subjects/Keywords: Conception Proche-Techno; PCM; 3-D monolithique; Nanofils; DG-CNFET; Crossbars; Nanoarchitectures; Benchmarking; Process-Design co-integration; Monolithic 3-D; NWFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gaillardon, P. (2011). Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire. (Doctoral Dissertation). Ecully, Ecole centrale de Lyon. Retrieved from http://www.theses.fr/2011ECDL0027

Chicago Manual of Style (16th Edition):

Gaillardon, Pierre-Emmanuel. “Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire.” 2011. Doctoral Dissertation, Ecully, Ecole centrale de Lyon. Accessed January 29, 2020. http://www.theses.fr/2011ECDL0027.

MLA Handbook (7th Edition):

Gaillardon, Pierre-Emmanuel. “Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire.” 2011. Web. 29 Jan 2020.

Vancouver:

Gaillardon P. Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire. [Internet] [Doctoral dissertation]. Ecully, Ecole centrale de Lyon; 2011. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2011ECDL0027.

Council of Science Editors:

Gaillardon P. Reconfigurable Logic Architectures based on Disruptive Technologies : Architectures logiques reconfigurables utilisant les propriétés de l'électronique moléculaire. [Doctoral Dissertation]. Ecully, Ecole centrale de Lyon; 2011. Available from: http://www.theses.fr/2011ECDL0027

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