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You searched for subject:( master slave flip flop divider ). Showing records 1 – 30 of 3134 total matches.

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California State University – Sacramento

1. Yerranagula, Monica. A programmable frequency divider for an all digital phase-locked loop in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 A phase-locked loop is needed on nearly every integrated circuit to align the phase and frequency of the clock created by the on-chip oscillator to… (more)

Subjects/Keywords: Toggle flip-flop; 2-input multiplexer; 4-input multiplexer; Programmable frequency divider; CMOS frequency divider

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APA (6th Edition):

Yerranagula, M. (2017). A programmable frequency divider for an all digital phase-locked loop in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/182875

Chicago Manual of Style (16th Edition):

Yerranagula, Monica. “A programmable frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2017. Masters Thesis, California State University – Sacramento. Accessed September 25, 2020. http://hdl.handle.net/10211.3/182875.

MLA Handbook (7th Edition):

Yerranagula, Monica. “A programmable frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2017. Web. 25 Sep 2020.

Vancouver:

Yerranagula M. A programmable frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10211.3/182875.

Council of Science Editors:

Yerranagula M. A programmable frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/182875


Queens University

2. Carr, John. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .

Degree: Electrical and Computer Engineering, 2009, Queens University

 This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use… (more)

Subjects/Keywords: phase-locked loop ; frequency multiplier ; CMOS ; integrated circuit ; voltage controlled oscillator ; injection locked frequency divider ; phase detector ; phase noise ; Accumulation MOS varactor ; monolithic integration ; static phase offset ; common mode rejection ; 26 GHz ; master-slave flip-flop divider ; direct injection ; differential ; phase plane

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APA (6th Edition):

Carr, J. (2009). A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Thesis, Queens University. Accessed September 25, 2020. http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Web. 25 Sep 2020.

Vancouver:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Internet] [Thesis]. Queens University; 2009. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Thesis]. Queens University; 2009. Available from: http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Uznanski, Slawosz. Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Decision making for the conservation of atlantic salmon populations (Salmo salar L.).

Degree: Docteur es, Micro et nanoélectronique, 2011, Aix-Marseille 1

L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire… (more)

Subjects/Keywords: Evénements Singulier; Aléa logiques; Rhbd; Cmos; Sram; Flip-Flop; SEE; SER; SEU; RHBD; Monte-Carlo; CMOS technology; SRAM; Flip-Flop

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APA (6th Edition):

Uznanski, S. (2011). Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Decision making for the conservation of atlantic salmon populations (Salmo salar L.). (Doctoral Dissertation). Aix-Marseille 1. Retrieved from http://www.theses.fr/2011AIX10222

Chicago Manual of Style (16th Edition):

Uznanski, Slawosz. “Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Decision making for the conservation of atlantic salmon populations (Salmo salar L.).” 2011. Doctoral Dissertation, Aix-Marseille 1. Accessed September 25, 2020. http://www.theses.fr/2011AIX10222.

MLA Handbook (7th Edition):

Uznanski, Slawosz. “Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Decision making for the conservation of atlantic salmon populations (Salmo salar L.).” 2011. Web. 25 Sep 2020.

Vancouver:

Uznanski S. Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Decision making for the conservation of atlantic salmon populations (Salmo salar L.). [Internet] [Doctoral dissertation]. Aix-Marseille 1; 2011. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2011AIX10222.

Council of Science Editors:

Uznanski S. Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Decision making for the conservation of atlantic salmon populations (Salmo salar L.). [Doctoral Dissertation]. Aix-Marseille 1; 2011. Available from: http://www.theses.fr/2011AIX10222


Vanderbilt University

4. Wang, Xiaowen. A clock-gated, double edge-triggered flip-flop implemented with transmission gates.

Degree: MS, Electrical Engineering, 2011, Vanderbilt University

 Power is a critical issue in digital system design, especially with the emphasis on the portability of electronic devices. However, decreasing power does not necessarily… (more)

Subjects/Keywords: Lowpower; Flip-Flop; Double edge-triggered; Clock-gating

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APA (6th Edition):

Wang, X. (2011). A clock-gated, double edge-triggered flip-flop implemented with transmission gates. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11592

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Xiaowen. “A clock-gated, double edge-triggered flip-flop implemented with transmission gates.” 2011. Thesis, Vanderbilt University. Accessed September 25, 2020. http://hdl.handle.net/1803/11592.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Xiaowen. “A clock-gated, double edge-triggered flip-flop implemented with transmission gates.” 2011. Web. 25 Sep 2020.

Vancouver:

Wang X. A clock-gated, double edge-triggered flip-flop implemented with transmission gates. [Internet] [Thesis]. Vanderbilt University; 2011. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1803/11592.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang X. A clock-gated, double edge-triggered flip-flop implemented with transmission gates. [Thesis]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/11592

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

5. Gaspard, Nelson Joseph III. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop(more)

Subjects/Keywords: single event upset; CMOS; flip-flop; soft error

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APA (6th Edition):

Gaspard, N. J. I. (2017). Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10824

Chicago Manual of Style (16th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed September 25, 2020. http://hdl.handle.net/1803/10824.

MLA Handbook (7th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Web. 25 Sep 2020.

Vancouver:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1803/10824.

Council of Science Editors:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/10824


Vanderbilt University

6. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

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APA (6th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11784

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Thesis, Vanderbilt University. Accessed September 25, 2020. http://hdl.handle.net/1803/11784.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 25 Sep 2020.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Thesis]. Vanderbilt University; 2015. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1803/11784.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Thesis]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/11784

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

7. Poe, Grant Douglas. A RADIATION-TOLERANT D FLIP-FLOP DESIGNED FOR LOW-VOLTAGE APPLICATIONS.

Degree: MS, Electrical Engineering, 2019, Vanderbilt University

 A radiation-hardened by design (RHBD) D flip-flop is presented that demonstrates a tolerance to radiation induced single-event upsets while maintaining desirable electrical performance characteristics over… (more)

Subjects/Keywords: D Flip-Flop; Single-Event Upset; Radiation Hardened By Design

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APA (6th Edition):

Poe, G. D. (2019). A RADIATION-TOLERANT D FLIP-FLOP DESIGNED FOR LOW-VOLTAGE APPLICATIONS. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13230

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Poe, Grant Douglas. “A RADIATION-TOLERANT D FLIP-FLOP DESIGNED FOR LOW-VOLTAGE APPLICATIONS.” 2019. Thesis, Vanderbilt University. Accessed September 25, 2020. http://hdl.handle.net/1803/13230.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Poe, Grant Douglas. “A RADIATION-TOLERANT D FLIP-FLOP DESIGNED FOR LOW-VOLTAGE APPLICATIONS.” 2019. Web. 25 Sep 2020.

Vancouver:

Poe GD. A RADIATION-TOLERANT D FLIP-FLOP DESIGNED FOR LOW-VOLTAGE APPLICATIONS. [Internet] [Thesis]. Vanderbilt University; 2019. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1803/13230.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Poe GD. A RADIATION-TOLERANT D FLIP-FLOP DESIGNED FOR LOW-VOLTAGE APPLICATIONS. [Thesis]. Vanderbilt University; 2019. Available from: http://hdl.handle.net/1803/13230

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

8. Fontaine, Robert Alexander. Investigation of 10-bit SAR ADC using flip-flip bypass circuit.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by… (more)

Subjects/Keywords: SAR; Successive Approximation Register; ADC; Flip-flop bypass

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APA (6th Edition):

Fontaine, R. A. (2013). Investigation of 10-bit SAR ADC using flip-flip bypass circuit. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24011

Chicago Manual of Style (16th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Masters Thesis, University of Texas – Austin. Accessed September 25, 2020. http://hdl.handle.net/2152/24011.

MLA Handbook (7th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Web. 25 Sep 2020.

Vancouver:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/2152/24011.

Council of Science Editors:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24011


University of Notre Dame

9. Christopher C. Forbes. Supramolecular Chemistry of Amide Containing Molecules</h1>.

Degree: Chemistry and Biochemistry, 2005, University of Notre Dame

  Amide-based synthetic molecules have been prepared and examined in four separate research projects which investigate conformational isomerization, anion binding, phospholipid translocation and rotaxane formation.… (more)

Subjects/Keywords: squaraine; Rotaxane; phospholipid flip flop

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APA (6th Edition):

Forbes, C. C. (2005). Supramolecular Chemistry of Amide Containing Molecules</h1>. (Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/6q182j64r5m

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Forbes, Christopher C.. “Supramolecular Chemistry of Amide Containing Molecules</h1>.” 2005. Thesis, University of Notre Dame. Accessed September 25, 2020. https://curate.nd.edu/show/6q182j64r5m.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Forbes, Christopher C.. “Supramolecular Chemistry of Amide Containing Molecules</h1>.” 2005. Web. 25 Sep 2020.

Vancouver:

Forbes CC. Supramolecular Chemistry of Amide Containing Molecules</h1>. [Internet] [Thesis]. University of Notre Dame; 2005. [cited 2020 Sep 25]. Available from: https://curate.nd.edu/show/6q182j64r5m.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Forbes CC. Supramolecular Chemistry of Amide Containing Molecules</h1>. [Thesis]. University of Notre Dame; 2005. Available from: https://curate.nd.edu/show/6q182j64r5m

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oregon

10. Lindsay, Theodore. Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans.

Degree: 2012, University of Oregon

 One central question of neuroscience asks how a neural system can generate the diversity of complex behaviors needed to meet the range of possible demands… (more)

Subjects/Keywords: Brownian; C. elegans; Circuit; Command neurons; Flip-flop; Optogenetics

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APA (6th Edition):

Lindsay, T. (2012). Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans. (Thesis). University of Oregon. Retrieved from http://hdl.handle.net/1794/12560

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lindsay, Theodore. “Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans.” 2012. Thesis, University of Oregon. Accessed September 25, 2020. http://hdl.handle.net/1794/12560.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lindsay, Theodore. “Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans.” 2012. Web. 25 Sep 2020.

Vancouver:

Lindsay T. Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans. [Internet] [Thesis]. University of Oregon; 2012. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1794/12560.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lindsay T. Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans. [Thesis]. University of Oregon; 2012. Available from: http://hdl.handle.net/1794/12560

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

11. Maheshwari, Yugal Kishore. A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops.

Degree: 2020, University of Waterloo

 Recently, several flip-flops have been proposed to increase their speed while reducing their power and energy consumption. Flip-flop power is dependent on data activity and… (more)

Subjects/Keywords: flip-flop; low-power; low-energy; data-activity; data-storage

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APA (6th Edition):

Maheshwari, Y. K. (2020). A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/16220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Maheshwari, Yugal Kishore. “A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops.” 2020. Thesis, University of Waterloo. Accessed September 25, 2020. http://hdl.handle.net/10012/16220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Maheshwari, Yugal Kishore. “A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops.” 2020. Web. 25 Sep 2020.

Vancouver:

Maheshwari YK. A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops. [Internet] [Thesis]. University of Waterloo; 2020. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10012/16220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Maheshwari YK. A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops. [Thesis]. University of Waterloo; 2020. Available from: http://hdl.handle.net/10012/16220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Swiecicki, Jean-Marie. Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides.

Degree: Docteur es, Chimie, 2014, Université Pierre et Marie Curie – Paris VI

Les peptides pénétrants (CPP) se caractérisent par deux propriétés : ils pénètrent dans l'espace intracellulaire et favorisent l'internalisation de cargaisons moléculaires auxquelles ils sont associés.… (more)

Subjects/Keywords: Peptide pénétrant; Lipopeptide; Vésicule; Phospholipide; Flip-Flop; Extinction de fluorescence; Cell penetrating peptides; Phospholipids; 540

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APA (6th Edition):

Swiecicki, J. (2014). Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066474

Chicago Manual of Style (16th Edition):

Swiecicki, Jean-Marie. “Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed September 25, 2020. http://www.theses.fr/2014PA066474.

MLA Handbook (7th Edition):

Swiecicki, Jean-Marie. “Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides.” 2014. Web. 25 Sep 2020.

Vancouver:

Swiecicki J. Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2014PA066474.

Council of Science Editors:

Swiecicki J. Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066474


University of California – Irvine

13. Elsharkasy, Wael Mahmoud. Low Power Reliable Design using Pulsed Latch Circuits.

Degree: Electrical and Computer Engineering, 2017, University of California – Irvine

 System-on-Chip (SoC) faced lots of challenges over the past decade. With nowadays applications centered around Internet-of-Everything (IoE), these challenges are expected to be more critical.… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Flip-Flop; Low Power; Pulsed Latch; Register File; Reliability; Sequential Element

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APA (6th Edition):

Elsharkasy, W. M. (2017). Low Power Reliable Design using Pulsed Latch Circuits. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/5ss2z430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Elsharkasy, Wael Mahmoud. “Low Power Reliable Design using Pulsed Latch Circuits.” 2017. Thesis, University of California – Irvine. Accessed September 25, 2020. http://www.escholarship.org/uc/item/5ss2z430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Elsharkasy, Wael Mahmoud. “Low Power Reliable Design using Pulsed Latch Circuits.” 2017. Web. 25 Sep 2020.

Vancouver:

Elsharkasy WM. Low Power Reliable Design using Pulsed Latch Circuits. [Internet] [Thesis]. University of California – Irvine; 2017. [cited 2020 Sep 25]. Available from: http://www.escholarship.org/uc/item/5ss2z430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Elsharkasy WM. Low Power Reliable Design using Pulsed Latch Circuits. [Thesis]. University of California – Irvine; 2017. Available from: http://www.escholarship.org/uc/item/5ss2z430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Bernard, Sébastien. Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Grenoble; Université catholique de Louvain (1970-....)

Avec l'explosion du marché des applications portables et le paradigme de l'Internet des objets, la demande pour les circuits à très haute efficacité énergétique ne… (more)

Subjects/Keywords: Bascule; Numérique; FDSOI; Énergétique; Efficacité; Flip-flop; Digital; FDSOI; Energy; Efficiency; 620

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APA (6th Edition):

Bernard, S. (2014). Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits. (Doctoral Dissertation). Grenoble; Université catholique de Louvain (1970-....). Retrieved from http://www.theses.fr/2014GRENT071

Chicago Manual of Style (16th Edition):

Bernard, Sébastien. “Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits.” 2014. Doctoral Dissertation, Grenoble; Université catholique de Louvain (1970-....). Accessed September 25, 2020. http://www.theses.fr/2014GRENT071.

MLA Handbook (7th Edition):

Bernard, Sébastien. “Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits.” 2014. Web. 25 Sep 2020.

Vancouver:

Bernard S. Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits. [Internet] [Doctoral dissertation]. Grenoble; Université catholique de Louvain (1970-....); 2014. [cited 2020 Sep 25]. Available from: http://www.theses.fr/2014GRENT071.

Council of Science Editors:

Bernard S. Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits. [Doctoral Dissertation]. Grenoble; Université catholique de Louvain (1970-....); 2014. Available from: http://www.theses.fr/2014GRENT071


Vanderbilt University

15. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

 Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

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APA (6th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Thesis, Vanderbilt University. Accessed September 25, 2020. http://hdl.handle.net/1803/12068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 25 Sep 2020.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Thesis]. Vanderbilt University; 2014. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1803/12068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Thesis]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/12068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

16. Zhang, Hangfang. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses… (more)

Subjects/Keywords: Single Event; Threshold Voltage; FinFET; Design Parameter; Temperature; Angular Incidence; Flip-Flop; Well Structure

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APA (6th Edition):

Zhang, H. (2018). Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12055

Chicago Manual of Style (16th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed September 25, 2020. http://hdl.handle.net/1803/12055.

MLA Handbook (7th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Web. 25 Sep 2020.

Vancouver:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/1803/12055.

Council of Science Editors:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/12055

17. Wang, Haibin. STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS.

Degree: 2015, University of Saskatchewan

 Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy… (more)

Subjects/Keywords: Single event effects; Charge sharing; nano technology; flip-flop; Radiation Hardening By Design

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APA (6th Edition):

Wang, H. (2015). STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/ETD-2015-08-2101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Haibin. “STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS.” 2015. Thesis, University of Saskatchewan. Accessed September 25, 2020. http://hdl.handle.net/10388/ETD-2015-08-2101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Haibin. “STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS.” 2015. Web. 25 Sep 2020.

Vancouver:

Wang H. STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS. [Internet] [Thesis]. University of Saskatchewan; 2015. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10388/ETD-2015-08-2101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang H. STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS. [Thesis]. University of Saskatchewan; 2015. Available from: http://hdl.handle.net/10388/ETD-2015-08-2101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Lourenço, João Pedro de Almeida. Transmissão de áudio através de TDM.

Degree: 2016, Instituto Politécnico do Porto

Na actualidade, pretende-se que as tecnologias apresentem, entre outras características, uma maior eficiência, autonomia e rapidez. Desta forma, este projecto insere-se no âmbito destas exigências… (more)

Subjects/Keywords: TDM; Microfone; Áudio; PIC; Transmissão; Cabo; Microphone; Audio; Transmission; Cable; DAC; EUSART; Flip-flop; Telecomunicações

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APA (6th Edition):

Lourenço, J. P. d. A. (2016). Transmissão de áudio através de TDM. (Thesis). Instituto Politécnico do Porto. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/10999

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lourenço, João Pedro de Almeida. “Transmissão de áudio através de TDM.” 2016. Thesis, Instituto Politécnico do Porto. Accessed September 25, 2020. https://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/10999.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lourenço, João Pedro de Almeida. “Transmissão de áudio através de TDM.” 2016. Web. 25 Sep 2020.

Vancouver:

Lourenço JPdA. Transmissão de áudio através de TDM. [Internet] [Thesis]. Instituto Politécnico do Porto; 2016. [cited 2020 Sep 25]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/10999.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lourenço JPdA. Transmissão de áudio através de TDM. [Thesis]. Instituto Politécnico do Porto; 2016. Available from: https://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/10999

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universiteit Utrecht

19. Halter, D. Transport and Translocation of Glucosylceramide.

Degree: 2007, Universiteit Utrecht

 Glycosphingolipids (GSL) are important determinants of the functional organization of cellular membranes. They are controlled by the spatial organization of their metabolism and by specificity… (more)

Subjects/Keywords: Scheikunde; glucosylceramide; glycosphingolipid; GLTP; V-ATPase; ABC transporter; flip-flop; transmembrane translocation; transport

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Halter, D. (2007). Transport and Translocation of Glucosylceramide. (Doctoral Dissertation). Universiteit Utrecht. Retrieved from http://dspace.library.uu.nl:8080/handle/1874/22788

Chicago Manual of Style (16th Edition):

Halter, D. “Transport and Translocation of Glucosylceramide.” 2007. Doctoral Dissertation, Universiteit Utrecht. Accessed September 25, 2020. http://dspace.library.uu.nl:8080/handle/1874/22788.

MLA Handbook (7th Edition):

Halter, D. “Transport and Translocation of Glucosylceramide.” 2007. Web. 25 Sep 2020.

Vancouver:

Halter D. Transport and Translocation of Glucosylceramide. [Internet] [Doctoral dissertation]. Universiteit Utrecht; 2007. [cited 2020 Sep 25]. Available from: http://dspace.library.uu.nl:8080/handle/1874/22788.

Council of Science Editors:

Halter D. Transport and Translocation of Glucosylceramide. [Doctoral Dissertation]. Universiteit Utrecht; 2007. Available from: http://dspace.library.uu.nl:8080/handle/1874/22788

20. Sjökvist, Niclas. Realizing a 32-bit Normally-Off Microprocessor With State Retention Flip Flops Using Crystalline Oxide Semiconductor Technology.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  Power consumption is one of the most important design factors in modern electronic design. With a large market increase in portable battery-operated devices and… (more)

Subjects/Keywords: Normally Off; Low Power; Microprocessor; Nonvolatile; Power Gating; State Retention; Flip Flop; CAAC; IGZO

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APA (6th Edition):

Sjökvist, N. (2013). Realizing a 32-bit Normally-Off Microprocessor With State Retention Flip Flops Using Crystalline Oxide Semiconductor Technology. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sjökvist, Niclas. “Realizing a 32-bit Normally-Off Microprocessor With State Retention Flip Flops Using Crystalline Oxide Semiconductor Technology.” 2013. Thesis, Linköping UniversityLinköping University. Accessed September 25, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sjökvist, Niclas. “Realizing a 32-bit Normally-Off Microprocessor With State Retention Flip Flops Using Crystalline Oxide Semiconductor Technology.” 2013. Web. 25 Sep 2020.

Vancouver:

Sjökvist N. Realizing a 32-bit Normally-Off Microprocessor With State Retention Flip Flops Using Crystalline Oxide Semiconductor Technology. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2020 Sep 25]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sjökvist N. Realizing a 32-bit Normally-Off Microprocessor With State Retention Flip Flops Using Crystalline Oxide Semiconductor Technology. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Notre Dame

21. Kristy Marie DiVittorio. Phospholipid Flip-Flop and Molecular Transport Across Biomembranes</h1>.

Degree: Chemistry and Biochemistry, 2007, University of Notre Dame

  This dissertation describes the ability of four classes of synthetic small molecules to promote the transport of anions across biomembranes without disturbing membrane integrity.… (more)

Subjects/Keywords: scramblase; translocation; Flip-flop; biomembranes; phospholipid

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APA (6th Edition):

DiVittorio, K. M. (2007). Phospholipid Flip-Flop and Molecular Transport Across Biomembranes</h1>. (Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/4x51hh65q0p

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DiVittorio, Kristy Marie. “Phospholipid Flip-Flop and Molecular Transport Across Biomembranes</h1>.” 2007. Thesis, University of Notre Dame. Accessed September 25, 2020. https://curate.nd.edu/show/4x51hh65q0p.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DiVittorio, Kristy Marie. “Phospholipid Flip-Flop and Molecular Transport Across Biomembranes</h1>.” 2007. Web. 25 Sep 2020.

Vancouver:

DiVittorio KM. Phospholipid Flip-Flop and Molecular Transport Across Biomembranes</h1>. [Internet] [Thesis]. University of Notre Dame; 2007. [cited 2020 Sep 25]. Available from: https://curate.nd.edu/show/4x51hh65q0p.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DiVittorio KM. Phospholipid Flip-Flop and Molecular Transport Across Biomembranes</h1>. [Thesis]. University of Notre Dame; 2007. Available from: https://curate.nd.edu/show/4x51hh65q0p

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

22. Choubey, Amit. Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations.

Degree: PhD, Physics, 2014, University of Southern California

 Biological cell membranes provide mechanical stability to cells and understanding their structure, dynamics and mechanics are important biophysics problems. Experiments coupled with computational methods such… (more)

Subjects/Keywords: molecular dynamics; DPPC bilayer; nanobubble collapse; shock; poration; cholesterol flip-flop; siRNA

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APA (6th Edition):

Choubey, A. (2014). Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5839

Chicago Manual of Style (16th Edition):

Choubey, Amit. “Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations.” 2014. Doctoral Dissertation, University of Southern California. Accessed September 25, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5839.

MLA Handbook (7th Edition):

Choubey, Amit. “Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations.” 2014. Web. 25 Sep 2020.

Vancouver:

Choubey A. Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations. [Internet] [Doctoral dissertation]. University of Southern California; 2014. [cited 2020 Sep 25]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5839.

Council of Science Editors:

Choubey A. Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations. [Doctoral Dissertation]. University of Southern California; 2014. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5839

23. Consoli, Elio. Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions.

Degree: 2012, Università degli Studi di Catania

 Clocked storage elements are among the most important elements in the design of digital systems, such as microprocessors, since they allow to synchronize and regulate… (more)

Subjects/Keywords: Area 09 - Ingegneria industriale e dell'informazione; Clocked Storage Elements, Clocking, VLSI, Nanometer CMOS, Low Power, High Speed, Energy-Efficient Design, Energy-Delay Tradeoff, Flip-Flops Comparison, Clock Domains, Master-Slave, Pulsed Latches

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APA (6th Edition):

Consoli, E. (2012). Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions. (Thesis). Università degli Studi di Catania. Retrieved from http://hdl.handle.net/10761/1075

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Consoli, Elio. “Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions.” 2012. Thesis, Università degli Studi di Catania. Accessed September 25, 2020. http://hdl.handle.net/10761/1075.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Consoli, Elio. “Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions.” 2012. Web. 25 Sep 2020.

Vancouver:

Consoli E. Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions. [Internet] [Thesis]. Università degli Studi di Catania; 2012. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10761/1075.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Consoli E. Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions. [Thesis]. Università degli Studi di Catania; 2012. Available from: http://hdl.handle.net/10761/1075

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Catholique de Louvain

24. Bernard, Sébastien. Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits.

Degree: 2014, Université Catholique de Louvain

The explosion market of the mobile application and the paradigm of the Internet of Things lead to a huge demand for energy-efficient systems. To overcome… (more)

Subjects/Keywords: CMOS Digital Circuits; Standard-Cell Design; FDSOI; UWVR; Pulsed Flip-Flop; Low-Voltage; Delay Generator; Register file

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APA (6th Edition):

Bernard, S. (2014). Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/153437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bernard, Sébastien. “Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits.” 2014. Thesis, Université Catholique de Louvain. Accessed September 25, 2020. http://hdl.handle.net/2078.1/153437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bernard, Sébastien. “Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits.” 2014. Web. 25 Sep 2020.

Vancouver:

Bernard S. Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits. [Internet] [Thesis]. Université Catholique de Louvain; 2014. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/2078.1/153437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bernard S. Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits. [Thesis]. Université Catholique de Louvain; 2014. Available from: http://hdl.handle.net/2078.1/153437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Tampere University

25. Nieminen, Tuomo. Molecular Mechanisms of Selected Disease-Linked Proteins Studied Through Atomistic Molecular Dynamics Simulations .

Degree: 2019, Tampere University

 Kalvoproteiinit ovat aminohappoketjuista muodostuvia monimutkaisia komplekseja, joilla on tärkeä rooli solujen ylläpidossa. Jotta proteiini pystyisi toteuttamaan tehtävänsä kalvossa, sen muodostaman aminohappoketjun täytyy ensin laskostua oikeanlaiseen… (more)

Subjects/Keywords: biologinen fysiikka; proteiini; myeliini; skramblaasi; flip-flop; molekyylidynamiikka; mallinnus; simulaatio; biological physics; protein; myelin; scramblase; molecular dynamics; modelling; simulations

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APA (6th Edition):

Nieminen, T. (2019). Molecular Mechanisms of Selected Disease-Linked Proteins Studied Through Atomistic Molecular Dynamics Simulations . (Doctoral Dissertation). Tampere University. Retrieved from https://trepo.tuni.fi/handle/10024/117549

Chicago Manual of Style (16th Edition):

Nieminen, Tuomo. “Molecular Mechanisms of Selected Disease-Linked Proteins Studied Through Atomistic Molecular Dynamics Simulations .” 2019. Doctoral Dissertation, Tampere University. Accessed September 25, 2020. https://trepo.tuni.fi/handle/10024/117549.

MLA Handbook (7th Edition):

Nieminen, Tuomo. “Molecular Mechanisms of Selected Disease-Linked Proteins Studied Through Atomistic Molecular Dynamics Simulations .” 2019. Web. 25 Sep 2020.

Vancouver:

Nieminen T. Molecular Mechanisms of Selected Disease-Linked Proteins Studied Through Atomistic Molecular Dynamics Simulations . [Internet] [Doctoral dissertation]. Tampere University; 2019. [cited 2020 Sep 25]. Available from: https://trepo.tuni.fi/handle/10024/117549.

Council of Science Editors:

Nieminen T. Molecular Mechanisms of Selected Disease-Linked Proteins Studied Through Atomistic Molecular Dynamics Simulations . [Doctoral Dissertation]. Tampere University; 2019. Available from: https://trepo.tuni.fi/handle/10024/117549


Rochester Institute of Technology

26. Pearson, Robert. PMOS digital structures.

Degree: 1986, Rochester Institute of Technology

  A majority of new integrated circuit designs are being fabricated in CMOS technology which uses both pMOSFETs and nMOSFETS. The nMOSFETS have been well… (more)

Subjects/Keywords: Fabrication; Flip-flop; Integrated circuit; pMOS; pMOSFET; RS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pearson, R. (1986). PMOS digital structures. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/4088

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pearson, Robert. “PMOS digital structures.” 1986. Thesis, Rochester Institute of Technology. Accessed September 25, 2020. https://scholarworks.rit.edu/theses/4088.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pearson, Robert. “PMOS digital structures.” 1986. Web. 25 Sep 2020.

Vancouver:

Pearson R. PMOS digital structures. [Internet] [Thesis]. Rochester Institute of Technology; 1986. [cited 2020 Sep 25]. Available from: https://scholarworks.rit.edu/theses/4088.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pearson R. PMOS digital structures. [Thesis]. Rochester Institute of Technology; 1986. Available from: https://scholarworks.rit.edu/theses/4088

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

27. Gujja, Aditya. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.

Degree: Electrical Engineering, 2015, Arizona State University

 An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced… (more)

Subjects/Keywords: Electrical engineering; Flip-Flop; multiple node charge collection; single event transient; single event upset; temporal hardening; triple mode redundancy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gujja, A. (2015). Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/36471

Chicago Manual of Style (16th Edition):

Gujja, Aditya. “Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.” 2015. Masters Thesis, Arizona State University. Accessed September 25, 2020. http://repository.asu.edu/items/36471.

MLA Handbook (7th Edition):

Gujja, Aditya. “Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.” 2015. Web. 25 Sep 2020.

Vancouver:

Gujja A. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. [Internet] [Masters thesis]. Arizona State University; 2015. [cited 2020 Sep 25]. Available from: http://repository.asu.edu/items/36471.

Council of Science Editors:

Gujja A. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. [Masters Thesis]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/36471


California State University – Sacramento

28. Penmetsa, Sruthi. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2016, California State University – Sacramento

 A phase-locked loop (PLL) is an important mixed-signal circuit that is used on almost every integrated circuit. A frequency divider is needed in the PLL… (more)

Subjects/Keywords: CML; CML Buffer; Current-mode logic; All-digital phase-locked loop; Design of CML toggle flip-flop; CML to CMOS converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Penmetsa, S. (2016). A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/182788

Chicago Manual of Style (16th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Masters Thesis, California State University – Sacramento. Accessed September 25, 2020. http://hdl.handle.net/10211.3/182788.

MLA Handbook (7th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Web. 25 Sep 2020.

Vancouver:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2016. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/10211.3/182788.

Council of Science Editors:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2016. Available from: http://hdl.handle.net/10211.3/182788


Brno University of Technology

29. Ribka, Jan. Decentralizované řízení jeřábu pomocí PLC SIMATIC: Decentralized Control of a Portal Crane by Means of PLC SIMATIC.

Degree: 2019, Brno University of Technology

 This master’s thesis deals with a total concept of decentralized control system for process control by means of PLC SIMATIC. This concept is demonstrated on… (more)

Subjects/Keywords: Decentralizovaný systém; komunikace master-slave; PROFIBUS DP; portálový jeřáb; Decentralized system; master-slave communication; PROFIBUS DP; portal crane

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ribka, J. (2019). Decentralizované řízení jeřábu pomocí PLC SIMATIC: Decentralized Control of a Portal Crane by Means of PLC SIMATIC. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2654

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ribka, Jan. “Decentralizované řízení jeřábu pomocí PLC SIMATIC: Decentralized Control of a Portal Crane by Means of PLC SIMATIC.” 2019. Thesis, Brno University of Technology. Accessed September 25, 2020. http://hdl.handle.net/11012/2654.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ribka, Jan. “Decentralizované řízení jeřábu pomocí PLC SIMATIC: Decentralized Control of a Portal Crane by Means of PLC SIMATIC.” 2019. Web. 25 Sep 2020.

Vancouver:

Ribka J. Decentralizované řízení jeřábu pomocí PLC SIMATIC: Decentralized Control of a Portal Crane by Means of PLC SIMATIC. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/11012/2654.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ribka J. Decentralizované řízení jeřábu pomocí PLC SIMATIC: Decentralized Control of a Portal Crane by Means of PLC SIMATIC. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/2654

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

30. Studený, Radim. Simulátor komunikace protokolů SCADA: Simulator of SCADA protocols.

Degree: 2018, Brno University of Technology

This work describes DNP3, IEC-60870, IEC-61850 communication protocols and their implementing in SCADA systems. It further describes communication of these protocols between RaspberryPi as a slave device and Personal Computer as a master device. Advisors/Committee Members: Blažek, Petr (advisor), Fujdiak, Radek (referee).

Subjects/Keywords: SCADA; DNP3; IEC-60870; IEC-61850; RaspberryPi; Master; Slave; SCADA; DNP3; IEC-60870; IEC-61850; RaspberryPi; Master; Slave

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Studený, R. (2018). Simulátor komunikace protokolů SCADA: Simulator of SCADA protocols. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/80894

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Studený, Radim. “Simulátor komunikace protokolů SCADA: Simulator of SCADA protocols.” 2018. Thesis, Brno University of Technology. Accessed September 25, 2020. http://hdl.handle.net/11012/80894.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Studený, Radim. “Simulátor komunikace protokolů SCADA: Simulator of SCADA protocols.” 2018. Web. 25 Sep 2020.

Vancouver:

Studený R. Simulátor komunikace protokolů SCADA: Simulator of SCADA protocols. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2020 Sep 25]. Available from: http://hdl.handle.net/11012/80894.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Studený R. Simulátor komunikace protokolů SCADA: Simulator of SCADA protocols. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/80894

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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