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Brno University of Technology

1. Janyš, Martin. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.

Degree: 2020, Brno University of Technology

The work introduces the reader to the possibilities of design and creation of nite state machines with focus on representation using VHDL. The main topic is the application that implements the VHDL code generator based on graphic description which can be create. The key application areas are described. In particular, their use and implementation that implements the actual transformation of the state diagram into VHDL. Advisors/Committee Members: Šimek, Václav (advisor), Košař, Vlastimil (referee).

Subjects/Keywords: konečný automat; FSM; VHDL; generátor konečných automatů; sekvenční logika; stavový diagram; graf přechodu; nite state machine; FSM; VHDL; generator of nite machine; sequential logic; state diagram; transition diagram

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janyš, M. (2020). Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/189704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2020. Thesis, Brno University of Technology. Accessed August 11, 2020. http://hdl.handle.net/11012/189704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2020. Web. 11 Aug 2020.

Vancouver:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 11]. Available from: http://hdl.handle.net/11012/189704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/189704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.