Static Analysis to improve RTL Verification.
Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech
Integrated circuits have traveled a long way from being a general purpose microprocessor to an application specific circuit. It has become an integral part of the modern era of technology that we live in. As the applications and their complexities are increasing rapidly every day, so are the sizes of these circuits. With the increase in the design size, the associated testing effort to verify these designs is also increased. The goal of this thesis is to leverage some of the static analysis techniques to reduce the effort of testing and verification at the register transfer level. Studying a design at register transfer level gives exposure to the relational information for the design which is inaccessible at the structural level.
In this thesis, we present a way to generate a Data Dependency Graph and a Control Flow Graph out of a register transfer level description of a circuit description. Next, the generated graphs are used to perform relation mining to improve the test generation process in terms of speed, branch coverage and number of test vectors generated. The generated control flow graph gives valuable information about the flow of information through the circuit design. We are using this information to create a framework to improve the branch reachability analysis mainly in terms of the speed. We show the efficiency of our methods by running them through a suite of ITC�[BULLET]99 benchmark circuits.
Advisors/Committee Members: Hsiao, Michael S. (committeechair), Abbott, Amos L (committee member), Zeng, Haibo (committee member).
Subjects/Keywords: Static Analysis; ATPG; Verification; Reachability Analysis
to Zotero / EndNote / Reference
APA (6th Edition):
Agrawal, A. (2017). Static Analysis to improve RTL Verification. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/75293
Chicago Manual of Style (16th Edition):
Agrawal, Akash. “Static Analysis to improve RTL Verification.” 2017. Masters Thesis, Virginia Tech. Accessed November 17, 2017.
MLA Handbook (7th Edition):
Agrawal, Akash. “Static Analysis to improve RTL Verification.” 2017. Web. 17 Nov 2017.
Agrawal A. Static Analysis to improve RTL Verification. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2017 Nov 17].
Available from: http://hdl.handle.net/10919/75293.
Council of Science Editors:
Agrawal A. Static Analysis to improve RTL Verification. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/75293