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California State University – Sacramento

1. Penmetsa, Sruthi. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2016, California State University – Sacramento

A phase-locked loop (PLL) is an important mixed-signal circuit that is used on almost every integrated circuit. A frequency divider is needed in the PLL loop to allow the use of a low frequency reference clock that is typically provided by a highly accurate off-chip crystal oscillator. This project is focused on the design of a current-mode logic (CML) frequency divider in 0.18um CMOS for an all digital phase-locked loop. Current-mode logic is used for the first few stages of the overall frequency divider, where the frequency of operation is too high for standard CMOS logic to operate properly. For this project, a CML frequency divider was designed in 0.18um CMOS and simulations were performed to verify performance for typical as well as worst case conditions. Advisors/Committee Members: Heedley, Perry.

Subjects/Keywords: CML; CML Buffer; Current-mode logic; All-digital phase-locked loop; Design of CML toggle flip-flop; CML to CMOS converter

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APA (6th Edition):

Penmetsa, S. (2016). A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/182788

Chicago Manual of Style (16th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Masters Thesis, California State University – Sacramento. Accessed April 28, 2017. http://hdl.handle.net/10211.3/182788.

MLA Handbook (7th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Web. 28 Apr 2017.

Vancouver:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2016. [cited 2017 Apr 28]. Available from: http://hdl.handle.net/10211.3/182788.

Council of Science Editors:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2016. Available from: http://hdl.handle.net/10211.3/182788

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