Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"Virginia Tech" +contributor:("Zeng, Haibo"). Showing records 1 – 30 of 35 total matches.

[1] [2]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

▼ Search Limiters


Virginia Tech

1. Drescher, Michael Stuart. A Flattened Hierarchical Scheduler for Real-Time Virtual Machines.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The recent trend of migrating legacy computer systems to a virtualized, cloud-based environment has expanded to real-time systems. Unfortunately, modern hypervisors have no mechanism in… (more)

Subjects/Keywords: Linux; KVM; Scheduling; Virtualization; Real-Time

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Drescher, M. S. (2015). A Flattened Hierarchical Scheduler for Real-Time Virtual Machines. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78125

Chicago Manual of Style (16th Edition):

Drescher, Michael Stuart. “A Flattened Hierarchical Scheduler for Real-Time Virtual Machines.” 2015. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/78125.

MLA Handbook (7th Edition):

Drescher, Michael Stuart. “A Flattened Hierarchical Scheduler for Real-Time Virtual Machines.” 2015. Web. 21 Aug 2019.

Vancouver:

Drescher MS. A Flattened Hierarchical Scheduler for Real-Time Virtual Machines. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/78125.

Council of Science Editors:

Drescher MS. A Flattened Hierarchical Scheduler for Real-Time Virtual Machines. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/78125

2. Mehrab, A K M Fazla. Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Cloud computing providers run data centers which are composed of thousands of server machines. Servers are robust, scalable, and thus capable of executing many jobs… (more)

Subjects/Keywords: Operating Systems; Unikernels; Virtualization; Heterogeneous Systems

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Sample image

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mehrab, A. K. M. F. (2018). Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86485

Chicago Manual of Style (16th Edition):

Mehrab, A K M Fazla. “Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/86485.

MLA Handbook (7th Edition):

Mehrab, A K M Fazla. “Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques.” 2018. Web. 21 Aug 2019.

Vancouver:

Mehrab AKMF. Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/86485.

Council of Science Editors:

Mehrab AKMF. Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/86485


Virginia Tech

3. Raghuraman, Shashank. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.

Degree: MS, Electrical and Computer Engineering, 2019, Virginia Tech

 With significant research effort being directed towards designing lightweight cryptographic primitives, logical metrics such as gate count are extensively used in estimating their hardware quality.… (more)

Subjects/Keywords: Logic synthesis; Cryptographic hardware; Circuit minimization; Leon-3; System-on-Chip; Authenticated encryption hardware

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raghuraman, S. (2019). Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/91462

Chicago Manual of Style (16th Edition):

Raghuraman, Shashank. “Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.” 2019. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/91462.

MLA Handbook (7th Edition):

Raghuraman, Shashank. “Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.” 2019. Web. 21 Aug 2019.

Vancouver:

Raghuraman S. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/91462.

Council of Science Editors:

Raghuraman S. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/91462


Virginia Tech

4. Shi, Zhun. Rapid Prototyping of an FPGA-Based Video Processing System.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones… (more)

Subjects/Keywords: FPGA; Computer Vision; Video Processing; Rapid Prototyping; High-Level Synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, Z. (2016). Rapid Prototyping of an FPGA-Based Video Processing System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71389

Chicago Manual of Style (16th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/71389.

MLA Handbook (7th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Web. 21 Aug 2019.

Vancouver:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/71389.

Council of Science Editors:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71389


Virginia Tech

5. Marcellino, Brendan Adrian. Partitioning Strategies to Enhance Symbolic Execution.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Software testing is a fundamental part of the software development process. However, testing is still costly and consumes about half of the development cost. The… (more)

Subjects/Keywords: Symbolic Execution; Software Testing; Static Analysis; Partitioning Strategies

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marcellino, B. A. (2015). Partitioning Strategies to Enhance Symbolic Execution. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/74883

Chicago Manual of Style (16th Edition):

Marcellino, Brendan Adrian. “Partitioning Strategies to Enhance Symbolic Execution.” 2015. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/74883.

MLA Handbook (7th Edition):

Marcellino, Brendan Adrian. “Partitioning Strategies to Enhance Symbolic Execution.” 2015. Web. 21 Aug 2019.

Vancouver:

Marcellino BA. Partitioning Strategies to Enhance Symbolic Execution. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/74883.

Council of Science Editors:

Marcellino BA. Partitioning Strategies to Enhance Symbolic Execution. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/74883


Virginia Tech

6. Agrawal, Akash. Static Analysis to improve RTL Verification.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Integrated circuits have traveled a long way from being a general purpose microprocessor to an application specific circuit. It has become an integral part of… (more)

Subjects/Keywords: Static Analysis; ATPG; Verification; Reachability Analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agrawal, A. (2017). Static Analysis to improve RTL Verification. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/75293

Chicago Manual of Style (16th Edition):

Agrawal, Akash. “Static Analysis to improve RTL Verification.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/75293.

MLA Handbook (7th Edition):

Agrawal, Akash. “Static Analysis to improve RTL Verification.” 2017. Web. 21 Aug 2019.

Vancouver:

Agrawal A. Static Analysis to improve RTL Verification. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/75293.

Council of Science Editors:

Agrawal A. Static Analysis to improve RTL Verification. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/75293


Virginia Tech

7. Gondhalekar, Nahush Ramesh. Reinforcement Learning with Gaussian Processes for Unmanned Aerial Vehicle Navigation.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 We study the problem of Reinforcement Learning (RL) for Unmanned Aerial Vehicle (UAV) navigation with the smallest number of real world samples possible. This work… (more)

Subjects/Keywords: Reinforcement Learning; Gaussian Processes; Unmanned Aerial Vehicle Navigation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gondhalekar, N. R. (2017). Reinforcement Learning with Gaussian Processes for Unmanned Aerial Vehicle Navigation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78667

Chicago Manual of Style (16th Edition):

Gondhalekar, Nahush Ramesh. “Reinforcement Learning with Gaussian Processes for Unmanned Aerial Vehicle Navigation.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/78667.

MLA Handbook (7th Edition):

Gondhalekar, Nahush Ramesh. “Reinforcement Learning with Gaussian Processes for Unmanned Aerial Vehicle Navigation.” 2017. Web. 21 Aug 2019.

Vancouver:

Gondhalekar NR. Reinforcement Learning with Gaussian Processes for Unmanned Aerial Vehicle Navigation. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/78667.

Council of Science Editors:

Gondhalekar NR. Reinforcement Learning with Gaussian Processes for Unmanned Aerial Vehicle Navigation. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78667


Virginia Tech

8. Roy, Tonmoy. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 In the first half of this thesis, a novel approach for k-induction bounded model checking using signal domain constraints and property partitioning for proving unreachability… (more)

Subjects/Keywords: RTL Verification; Reachability; k-Induction; Bounded Model Checking; Test Vector Compaction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roy, T. (2017). Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78801

Chicago Manual of Style (16th Edition):

Roy, Tonmoy. “Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/78801.

MLA Handbook (7th Edition):

Roy, Tonmoy. “Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.” 2017. Web. 21 Aug 2019.

Vancouver:

Roy T. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/78801.

Council of Science Editors:

Roy T. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78801


Virginia Tech

9. Gupta, Prakriti. Spatio-Temporal Analysis of Urban Data and its Application for Smart Cities.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 With the advent of smart sensor devices and Internet of Things (IoT) in the rapid urbanizing cities, data is being generated, collected and analyzed to… (more)

Subjects/Keywords: Traffic Analysis; Electric Vehicle Charging Demand; Quantitative Criminology; Spatio-Temporal Analysis; Data Mining

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gupta, P. (2017). Spatio-Temporal Analysis of Urban Data and its Application for Smart Cities. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/87418

Chicago Manual of Style (16th Edition):

Gupta, Prakriti. “Spatio-Temporal Analysis of Urban Data and its Application for Smart Cities.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/87418.

MLA Handbook (7th Edition):

Gupta, Prakriti. “Spatio-Temporal Analysis of Urban Data and its Application for Smart Cities.” 2017. Web. 21 Aug 2019.

Vancouver:

Gupta P. Spatio-Temporal Analysis of Urban Data and its Application for Smart Cities. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/87418.

Council of Science Editors:

Gupta P. Spatio-Temporal Analysis of Urban Data and its Application for Smart Cities. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/87418


Virginia Tech

10. Asathulla, Mudabir Kabir. A Sparsification Based Algorithm for Maximum-Cardinality Bipartite Matching in Planar Graphs.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Matching is one of the most fundamental algorithmic graph problems. Many variants of matching problems have been studied on different classes of graphs, the one… (more)

Subjects/Keywords: matching; maximum cardinality; bipartite; planar graph; planar separators

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Asathulla, M. K. (2017). A Sparsification Based Algorithm for Maximum-Cardinality Bipartite Matching in Planar Graphs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/88080

Chicago Manual of Style (16th Edition):

Asathulla, Mudabir Kabir. “A Sparsification Based Algorithm for Maximum-Cardinality Bipartite Matching in Planar Graphs.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/88080.

MLA Handbook (7th Edition):

Asathulla, Mudabir Kabir. “A Sparsification Based Algorithm for Maximum-Cardinality Bipartite Matching in Planar Graphs.” 2017. Web. 21 Aug 2019.

Vancouver:

Asathulla MK. A Sparsification Based Algorithm for Maximum-Cardinality Bipartite Matching in Planar Graphs. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/88080.

Council of Science Editors:

Asathulla MK. A Sparsification Based Algorithm for Maximum-Cardinality Bipartite Matching in Planar Graphs. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/88080


Virginia Tech

11. Deshpande, Chinmay Ravindra. Hardware Fault Attack Detection Methods for Secure Embedded Systems.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 In our daily life, we are increasingly putting our trust in embedded software applications, which run on a range of processor-based embedded systems from smartcards… (more)

Subjects/Keywords: Fault Attack; Countermeasures; Detection; Clock glitching; Electromagnetic Fault Injection

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Deshpande, C. R. (2018). Hardware Fault Attack Detection Methods for Secure Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82141

Chicago Manual of Style (16th Edition):

Deshpande, Chinmay Ravindra. “Hardware Fault Attack Detection Methods for Secure Embedded Systems.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/82141.

MLA Handbook (7th Edition):

Deshpande, Chinmay Ravindra. “Hardware Fault Attack Detection Methods for Secure Embedded Systems.” 2018. Web. 21 Aug 2019.

Vancouver:

Deshpande CR. Hardware Fault Attack Detection Methods for Secure Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/82141.

Council of Science Editors:

Deshpande CR. Hardware Fault Attack Detection Methods for Secure Embedded Systems. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82141


Virginia Tech

12. Shastry, Akshay Kumar. Functional Safety Assessment in Autonomous Vehicles.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Autonomous vehicles (AVs) are a class of safety-critical systems that are capable of decision-making and operate with little or no human intervention. For such complex… (more)

Subjects/Keywords: Functional Safety; Autonomous Vehicles; ISO 26262; Risk Mitigation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shastry, A. K. (2018). Functional Safety Assessment in Autonomous Vehicles. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/83483

Chicago Manual of Style (16th Edition):

Shastry, Akshay Kumar. “Functional Safety Assessment in Autonomous Vehicles.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/83483.

MLA Handbook (7th Edition):

Shastry, Akshay Kumar. “Functional Safety Assessment in Autonomous Vehicles.” 2018. Web. 21 Aug 2019.

Vancouver:

Shastry AK. Functional Safety Assessment in Autonomous Vehicles. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/83483.

Council of Science Editors:

Shastry AK. Functional Safety Assessment in Autonomous Vehicles. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/83483


Virginia Tech

13. Khanna, Tania. Guiding RTL Test Generation Using Relevant Potential Invariants.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 In this thesis, we propose to use relevant potential invariants in a simulation-based swarmintelligence-based test generation technique to generate relevant test vectors for design validation… (more)

Subjects/Keywords: Ant Colony Optimization; Potential Invariants; Branch Coverage; Verilator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khanna, T. (2018). Guiding RTL Test Generation Using Relevant Potential Invariants. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84483

Chicago Manual of Style (16th Edition):

Khanna, Tania. “Guiding RTL Test Generation Using Relevant Potential Invariants.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/84483.

MLA Handbook (7th Edition):

Khanna, Tania. “Guiding RTL Test Generation Using Relevant Potential Invariants.” 2018. Web. 21 Aug 2019.

Vancouver:

Khanna T. Guiding RTL Test Generation Using Relevant Potential Invariants. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/84483.

Council of Science Editors:

Khanna T. Guiding RTL Test Generation Using Relevant Potential Invariants. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84483


Virginia Tech

14. Kakusa, Takondwa Lisungu. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Natural Language processing is a growing field and widely used in both industrial and and commercial cases. Though it is difficult to create a natural… (more)

Subjects/Keywords: Natural Language Processing; Robotics; ROS

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kakusa, T. L. (2018). Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84521

Chicago Manual of Style (16th Edition):

Kakusa, Takondwa Lisungu. “Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/84521.

MLA Handbook (7th Edition):

Kakusa, Takondwa Lisungu. “Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.” 2018. Web. 21 Aug 2019.

Vancouver:

Kakusa TL. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/84521.

Council of Science Editors:

Kakusa TL. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84521


Virginia Tech

15. Bansal, Shamit. Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Model-based design based on the Simulink modeling formalism and the associated toolchain has gained its popularity in the development of complex embedded control systems. However,the… (more)

Subjects/Keywords: Simulink; Multicore; Software Synthesis; Partitioned scheduling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bansal, S. (2018). Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/85057

Chicago Manual of Style (16th Edition):

Bansal, Shamit. “Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/85057.

MLA Handbook (7th Edition):

Bansal, Shamit. “Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling.” 2018. Web. 21 Aug 2019.

Vancouver:

Bansal S. Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/85057.

Council of Science Editors:

Bansal S. Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/85057


Virginia Tech

16. Salman, Mohammed. Towards Improving Endurance and Performance in Flash Storage Clusters.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 NAND flash-based Solid State Devices (SSDs) provide high performance and energy efficiency and at the same time their capacity continues to grow at an unprecedented… (more)

Subjects/Keywords: Flash Storage; Wear Balancing; Flash Endurance; Write Off-loading

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Salman, M. (2017). Towards Improving Endurance and Performance in Flash Storage Clusters. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86413

Chicago Manual of Style (16th Edition):

Salman, Mohammed. “Towards Improving Endurance and Performance in Flash Storage Clusters.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/86413.

MLA Handbook (7th Edition):

Salman, Mohammed. “Towards Improving Endurance and Performance in Flash Storage Clusters.” 2017. Web. 21 Aug 2019.

Vancouver:

Salman M. Towards Improving Endurance and Performance in Flash Storage Clusters. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/86413.

Council of Science Editors:

Salman M. Towards Improving Endurance and Performance in Flash Storage Clusters. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/86413


Virginia Tech

17. Asokan, Pranav. Privacy Preserving Authentication Schemes and Applications.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 With the advent of smart devices, Internet of things and cloud computing the amount of information collected about an individual is enormous. Using this meta-data,… (more)

Subjects/Keywords: Privacy Preserving Authentication; Direct Anonymous Attestation; Trusted Platform Module

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Asokan, P. (2017). Privacy Preserving Authentication Schemes and Applications. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86422

Chicago Manual of Style (16th Edition):

Asokan, Pranav. “Privacy Preserving Authentication Schemes and Applications.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/86422.

MLA Handbook (7th Edition):

Asokan, Pranav. “Privacy Preserving Authentication Schemes and Applications.” 2017. Web. 21 Aug 2019.

Vancouver:

Asokan P. Privacy Preserving Authentication Schemes and Applications. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/86422.

Council of Science Editors:

Asokan P. Privacy Preserving Authentication Schemes and Applications. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/86422


Virginia Tech

18. Mysore Shamprasad, Shreyak. Validation of EcoRouting and an Analysis of the Impact of Traffic on Route Choice.

Degree: MS, Electrical and Computer Engineering, 2019, Virginia Tech

 Battery Electric Vehicles and Plug-in Hybrid Vehicles are increasingly becoming more popular in recent years. Stricter regulations from government agencies to curb emissions and reduce… (more)

Subjects/Keywords: EcoRouting; Energy consumption; Battery Electric Vehicle

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mysore Shamprasad, S. (2019). Validation of EcoRouting and an Analysis of the Impact of Traffic on Route Choice. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89537

Chicago Manual of Style (16th Edition):

Mysore Shamprasad, Shreyak. “Validation of EcoRouting and an Analysis of the Impact of Traffic on Route Choice.” 2019. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/89537.

MLA Handbook (7th Edition):

Mysore Shamprasad, Shreyak. “Validation of EcoRouting and an Analysis of the Impact of Traffic on Route Choice.” 2019. Web. 21 Aug 2019.

Vancouver:

Mysore Shamprasad S. Validation of EcoRouting and an Analysis of the Impact of Traffic on Route Choice. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/89537.

Council of Science Editors:

Mysore Shamprasad S. Validation of EcoRouting and an Analysis of the Impact of Traffic on Route Choice. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89537


Virginia Tech

19. Tolley, Joseph D. Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis.

Degree: MS, Electrical and Computer Engineering, 2019, Virginia Tech

 The thesis analyzes the steps and actions necessary to develop an application using a user identity management system, user permissions system, message distribution system, and… (more)

Subjects/Keywords: emergency response; computer system; mobile device; organization; identity; user permissions

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tolley, J. D. (2019). Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89907

Chicago Manual of Style (16th Edition):

Tolley, Joseph D. “Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis.” 2019. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/89907.

MLA Handbook (7th Edition):

Tolley, Joseph D. “Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis.” 2019. Web. 21 Aug 2019.

Vancouver:

Tolley JD. Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/89907.

Council of Science Editors:

Tolley JD. Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89907


Virginia Tech

20. Liu, Chenang. Smart Additive Manufacturing Using Advanced Data Analytics and Closed Loop Control.

Degree: PhD, Industrial and Systems Engineering, 2019, Virginia Tech

 Additive manufacturing (AM) is a powerful emerging technology for fabrication of components with complex geometries using a variety of materials. However, despite promising potential, due… (more)

Subjects/Keywords: Additive Manufacturing; Online Quality Assurance; Data Analytics; Spectral Graph Theory; Manifold Learning; Bilateral Time Series Model; Closed-Loop Control

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, C. (2019). Smart Additive Manufacturing Using Advanced Data Analytics and Closed Loop Control. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/91900

Chicago Manual of Style (16th Edition):

Liu, Chenang. “Smart Additive Manufacturing Using Advanced Data Analytics and Closed Loop Control.” 2019. Doctoral Dissertation, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/91900.

MLA Handbook (7th Edition):

Liu, Chenang. “Smart Additive Manufacturing Using Advanced Data Analytics and Closed Loop Control.” 2019. Web. 21 Aug 2019.

Vancouver:

Liu C. Smart Additive Manufacturing Using Advanced Data Analytics and Closed Loop Control. [Internet] [Doctoral dissertation]. Virginia Tech; 2019. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/91900.

Council of Science Editors:

Liu C. Smart Additive Manufacturing Using Advanced Data Analytics and Closed Loop Control. [Doctoral Dissertation]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/91900


Virginia Tech

21. Dutta, Bishwajit. Power Analysis and Prediction for Heterogeneous Computation.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Power, performance, and cost dictate the procurement and operation of high-performance computing (HPC) systems. These systems use graphics processing units (GPUs) for performance boost. In… (more)

Subjects/Keywords: Power and Performance; GPU; Heterogeneous Computation; Machine Learning

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dutta, B. (2018). Power Analysis and Prediction for Heterogeneous Computation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/92870

Chicago Manual of Style (16th Edition):

Dutta, Bishwajit. “Power Analysis and Prediction for Heterogeneous Computation.” 2018. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/92870.

MLA Handbook (7th Edition):

Dutta, Bishwajit. “Power Analysis and Prediction for Heterogeneous Computation.” 2018. Web. 21 Aug 2019.

Vancouver:

Dutta B. Power Analysis and Prediction for Heterogeneous Computation. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/92870.

Council of Science Editors:

Dutta B. Power Analysis and Prediction for Heterogeneous Computation. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/92870

22. Pinto, Sonal. RTL Functional Test Generation Using Factored Concolic Execution.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 This thesis presents a novel concolic testing methodology and CORT, a test generation framework that uses it for high-level functional test generation. The test generation… (more)

Subjects/Keywords: Functional Test Generation; Control-Flow Response; Concolic Execution; Branch Coverage; System State

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pinto, S. (2017). RTL Functional Test Generation Using Factored Concolic Execution. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78397

Chicago Manual of Style (16th Edition):

Pinto, Sonal. “RTL Functional Test Generation Using Factored Concolic Execution.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/78397.

MLA Handbook (7th Edition):

Pinto, Sonal. “RTL Functional Test Generation Using Factored Concolic Execution.” 2017. Web. 21 Aug 2019.

Vancouver:

Pinto S. RTL Functional Test Generation Using Factored Concolic Execution. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/78397.

Council of Science Editors:

Pinto S. RTL Functional Test Generation Using Factored Concolic Execution. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78397

23. Bangalore Narendranath Rao, Amith Kaushal. Online Message Delay Prediction for Model Predictive Control over Controller Area Network.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Today's Cyber-Physical Systems (CPS) are typically distributed over several computing nodes communicating by way of shared buses such as Controller Area Network (CAN). Their control… (more)

Subjects/Keywords: Model Predictive Control (MPC); Controller Area Network (CAN); Online delay prediction; delay

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bangalore Narendranath Rao, A. K. (2017). Online Message Delay Prediction for Model Predictive Control over Controller Area Network. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78626

Chicago Manual of Style (16th Edition):

Bangalore Narendranath Rao, Amith Kaushal. “Online Message Delay Prediction for Model Predictive Control over Controller Area Network.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/78626.

MLA Handbook (7th Edition):

Bangalore Narendranath Rao, Amith Kaushal. “Online Message Delay Prediction for Model Predictive Control over Controller Area Network.” 2017. Web. 21 Aug 2019.

Vancouver:

Bangalore Narendranath Rao AK. Online Message Delay Prediction for Model Predictive Control over Controller Area Network. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/78626.

Council of Science Editors:

Bangalore Narendranath Rao AK. Online Message Delay Prediction for Model Predictive Control over Controller Area Network. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78626

24. Vaka, Pradeep Reddy. Security and Performance Issues in Spectrum Sharing between Disparate Wireless Networks.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 The United States Federal Communications Commission (FCC) in its recent report and order has prescribed the creation of Citizens Broadband Radio Service (CRBS) in the… (more)

Subjects/Keywords: Location Privacy; Coexistence; Spectrum Sharing; NB-IoT; Radar Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vaka, P. R. (2017). Security and Performance Issues in Spectrum Sharing between Disparate Wireless Networks. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/77960

Chicago Manual of Style (16th Edition):

Vaka, Pradeep Reddy. “Security and Performance Issues in Spectrum Sharing between Disparate Wireless Networks.” 2017. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/77960.

MLA Handbook (7th Edition):

Vaka, Pradeep Reddy. “Security and Performance Issues in Spectrum Sharing between Disparate Wireless Networks.” 2017. Web. 21 Aug 2019.

Vancouver:

Vaka PR. Security and Performance Issues in Spectrum Sharing between Disparate Wireless Networks. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/77960.

Council of Science Editors:

Vaka PR. Security and Performance Issues in Spectrum Sharing between Disparate Wireless Networks. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/77960

25. Liu, Chang. An Automatic Solution to Checking Compatibility between Routing Metrics and Protocols.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Routing metrics are important mechanisms to adjust routing protocols' path selection according to the needs of a network system. However, if a routing metric design… (more)

Subjects/Keywords: Routing Metrics; Routing Protocols; Software Verification

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, C. (2016). An Automatic Solution to Checking Compatibility between Routing Metrics and Protocols. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/64476

Chicago Manual of Style (16th Edition):

Liu, Chang. “An Automatic Solution to Checking Compatibility between Routing Metrics and Protocols.” 2016. Masters Thesis, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/64476.

MLA Handbook (7th Edition):

Liu, Chang. “An Automatic Solution to Checking Compatibility between Routing Metrics and Protocols.” 2016. Web. 21 Aug 2019.

Vancouver:

Liu C. An Automatic Solution to Checking Compatibility between Routing Metrics and Protocols. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/64476.

Council of Science Editors:

Liu C. An Automatic Solution to Checking Compatibility between Routing Metrics and Protocols. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/64476


Virginia Tech

26. Tanwir, Sarmad. Online Techniques for Enhancing the Diagnosis of Digital Circuits.

Degree: PhD, Electrical and Computer Engineering, 2018, Virginia Tech

 The test process for semiconductor devices involves generation and application of test patterns, failure logging and diagnosis. Traditionally, most of these activities cater for all… (more)

Subjects/Keywords: Diagnosis; Digital Circuits; Online; Diagnostic Test Pattern Generation; Real-time; Failure Log Optimization; Failure Log Selection; Particle Swarm Optimization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tanwir, S. (2018). Online Techniques for Enhancing the Diagnosis of Digital Circuits. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82736

Chicago Manual of Style (16th Edition):

Tanwir, Sarmad. “Online Techniques for Enhancing the Diagnosis of Digital Circuits.” 2018. Doctoral Dissertation, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/82736.

MLA Handbook (7th Edition):

Tanwir, Sarmad. “Online Techniques for Enhancing the Diagnosis of Digital Circuits.” 2018. Web. 21 Aug 2019.

Vancouver:

Tanwir S. Online Techniques for Enhancing the Diagnosis of Digital Circuits. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/82736.

Council of Science Editors:

Tanwir S. Online Techniques for Enhancing the Diagnosis of Digital Circuits. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82736


Virginia Tech

27. Kusano, Markus Jan Urban. Constraint-Based Thread-Modular Abstract Interpretation.

Degree: PhD, Electrical and Computer Engineering, 2018, Virginia Tech

 In this dissertation, I present a set of novel constraint-based thread-modular abstract-interpretation techniques for static analysis of concurrent programs. Specifically, I integrate a lightweight constraint… (more)

Subjects/Keywords: abstract interpretation; concurrency; verification; static analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kusano, M. J. U. (2018). Constraint-Based Thread-Modular Abstract Interpretation. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84399

Chicago Manual of Style (16th Edition):

Kusano, Markus Jan Urban. “Constraint-Based Thread-Modular Abstract Interpretation.” 2018. Doctoral Dissertation, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/84399.

MLA Handbook (7th Edition):

Kusano, Markus Jan Urban. “Constraint-Based Thread-Modular Abstract Interpretation.” 2018. Web. 21 Aug 2019.

Vancouver:

Kusano MJU. Constraint-Based Thread-Modular Abstract Interpretation. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/84399.

Council of Science Editors:

Kusano MJU. Constraint-Based Thread-Modular Abstract Interpretation. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84399


Virginia Tech

28. Liu, Qingrui. Compiler-Directed Error Resilience for Reliable Computing.

Degree: PhD, Electrical and Computer Engineering, 2018, Virginia Tech

 Error resilience has become as important as power and performance in modern computing architecture. There are various sources of errors that can paralyze real-world computing… (more)

Subjects/Keywords: Reliability; Compiler Optimization; Computer Architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Q. (2018). Compiler-Directed Error Resilience for Reliable Computing. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84526

Chicago Manual of Style (16th Edition):

Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Doctoral Dissertation, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/84526.

MLA Handbook (7th Edition):

Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Web. 21 Aug 2019.

Vancouver:

Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/84526.

Council of Science Editors:

Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84526


Virginia Tech

29. Mahmoud, Abdallah Abdelrahman Hassan. Cooperative Automated Vehicle Movement Optimization at Uncontrolled Intersections using Distributed Multi-Agent System Modeling.

Degree: PhD, Electrical and ComputerEngineering, 2017, Virginia Tech

 Optimizing connected automated vehicle movements through roadway intersections is a challenging problem. Traditional traffic control strategies, such as traffic signals are not optimal, especially for… (more)

Subjects/Keywords: ITS; Automated Vehicles; Uncontrolled Intersections; Networked Intersections; Multi-agent Systems; Distributed Systems; Intelligent Agent Cooperation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mahmoud, A. A. H. (2017). Cooperative Automated Vehicle Movement Optimization at Uncontrolled Intersections using Distributed Multi-Agent System Modeling. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84896

Chicago Manual of Style (16th Edition):

Mahmoud, Abdallah Abdelrahman Hassan. “Cooperative Automated Vehicle Movement Optimization at Uncontrolled Intersections using Distributed Multi-Agent System Modeling.” 2017. Doctoral Dissertation, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/84896.

MLA Handbook (7th Edition):

Mahmoud, Abdallah Abdelrahman Hassan. “Cooperative Automated Vehicle Movement Optimization at Uncontrolled Intersections using Distributed Multi-Agent System Modeling.” 2017. Web. 21 Aug 2019.

Vancouver:

Mahmoud AAH. Cooperative Automated Vehicle Movement Optimization at Uncontrolled Intersections using Distributed Multi-Agent System Modeling. [Internet] [Doctoral dissertation]. Virginia Tech; 2017. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/84896.

Council of Science Editors:

Mahmoud AAH. Cooperative Automated Vehicle Movement Optimization at Uncontrolled Intersections using Distributed Multi-Agent System Modeling. [Doctoral Dissertation]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/84896


Virginia Tech

30. Zhang, Lu. Runtime Verification and Debugging of Concurrent Software.

Degree: PhD, Electrical and Computer Engineering, 2016, Virginia Tech

 Our reliance on software has been growing fast over the past decades as the pervasive use of computer and software penetrated not only our daily… (more)

Subjects/Keywords: Concurrency; Verification; Debugging; Program Repair; Quasi Linearizability; Concurrent Data Structure; Web Application; JavaScript

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, L. (2016). Runtime Verification and Debugging of Concurrent Software. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71882

Chicago Manual of Style (16th Edition):

Zhang, Lu. “Runtime Verification and Debugging of Concurrent Software.” 2016. Doctoral Dissertation, Virginia Tech. Accessed August 21, 2019. http://hdl.handle.net/10919/71882.

MLA Handbook (7th Edition):

Zhang, Lu. “Runtime Verification and Debugging of Concurrent Software.” 2016. Web. 21 Aug 2019.

Vancouver:

Zhang L. Runtime Verification and Debugging of Concurrent Software. [Internet] [Doctoral dissertation]. Virginia Tech; 2016. [cited 2019 Aug 21]. Available from: http://hdl.handle.net/10919/71882.

Council of Science Editors:

Zhang L. Runtime Verification and Debugging of Concurrent Software. [Doctoral Dissertation]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71882

[1] [2]

.