Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"Virginia Tech" +contributor:("Wang, Chao"). Showing records 1 – 30 of 36 total matches.

[1] [2]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

▼ Search Limiters


Virginia Tech

1. Shrestha, Gyanendra. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Globalization of semiconductor design and manufacturing has led to a concern of trust in the final product. The components may now be designed and manufactured… (more)

Subjects/Keywords: BMC; Miter; RTL; Hardware Trojan

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shrestha, G. (2012). Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/44889

Chicago Manual of Style (16th Edition):

Shrestha, Gyanendra. “Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.” 2012. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/44889.

MLA Handbook (7th Edition):

Shrestha, Gyanendra. “Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.” 2012. Web. 12 Apr 2021.

Vancouver:

Shrestha G. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/44889.

Council of Science Editors:

Shrestha G. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/44889


Virginia Tech

2. Katz, David Gabriel. Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 Proliferation of new computing hardware platforms that support increasing numbers of cores, as well as increasing ISA heterogeneity, is creating opportunity for systems software developers… (more)

Subjects/Keywords: OS; Multikernel

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Katz, D. G. (2014). Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52561

Chicago Manual of Style (16th Edition):

Katz, David Gabriel. “Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel.” 2014. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/52561.

MLA Handbook (7th Edition):

Katz, David Gabriel. “Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel.” 2014. Web. 12 Apr 2021.

Vancouver:

Katz DG. Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/52561.

Council of Science Editors:

Katz DG. Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/52561


Virginia Tech

3. Kracht, Matthew Wallace. Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 As embedded software and platforms become more complicated, many safety properties are left to simulation and testing. MRICDF is a formal polychronous language used to… (more)

Subjects/Keywords: Synchronous Languages; Real-Time Systems; Schedulability Analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kracht, M. W. (2014). Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46866

Chicago Manual of Style (16th Edition):

Kracht, Matthew Wallace. “Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages.” 2014. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/46866.

MLA Handbook (7th Edition):

Kracht, Matthew Wallace. “Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages.” 2014. Web. 12 Apr 2021.

Vancouver:

Kracht MW. Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/46866.

Council of Science Editors:

Kracht MW. Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/46866


Virginia Tech

4. Adhikari, Kiran. Verifying a Quantitative Relaxation of Linearizability via Refinement.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Concurrent data structures have found increasingly widespread use in both multicore and distributed computing environments, thereby escalating the priority for verifying their correctness. The thread… (more)

Subjects/Keywords: Quasi Linearizability; Refinement; Model Checking

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Adhikari, K. (2013). Verifying a Quantitative Relaxation of Linearizability via Refinement. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23222

Chicago Manual of Style (16th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/23222.

MLA Handbook (7th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Web. 12 Apr 2021.

Vancouver:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/23222.

Council of Science Editors:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23222


Virginia Tech

5. Pandit, Shuchi. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based… (more)

Subjects/Keywords: Trace Buffer Architecture; Signal Restoration; Invariants

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pandit, S. (2014). Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49151

Chicago Manual of Style (16th Edition):

Pandit, Shuchi. “Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.” 2014. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/49151.

MLA Handbook (7th Edition):

Pandit, Shuchi. “Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.” 2014. Web. 12 Apr 2021.

Vancouver:

Pandit S. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/49151.

Council of Science Editors:

Pandit S. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49151


Virginia Tech

6. Pan, Zhenhe. A software defined GPS signal simulator design.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 The Global Positioning System (GPS) signal simulator plays a critical role in developing and testing GPS receivers. Unfortunately, very few commercial GPS signal simulators are… (more)

Subjects/Keywords: GPS simulator; software defined; GPS interference; spoofing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pan, Z. (2014). A software defined GPS signal simulator design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56630

Chicago Manual of Style (16th Edition):

Pan, Zhenhe. “A software defined GPS signal simulator design.” 2014. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/56630.

MLA Handbook (7th Edition):

Pan, Zhenhe. “A software defined GPS signal simulator design.” 2014. Web. 12 Apr 2021.

Vancouver:

Pan Z. A software defined GPS signal simulator design. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/56630.

Council of Science Editors:

Pan Z. A software defined GPS signal simulator design. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/56630


Virginia Tech

7. Albert, Frank Curtis. Applying Source Level Auto-Vectorization to Aparapi Java.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 Ever since chip manufacturers hit the power wall preventing them from increasing processor clock speed, there has been an increased push towards parallelism for performance… (more)

Subjects/Keywords: Auto-Vectorization; Aparapi; Java; GPGPU Computing; SIMD; Parallelism; Threaded

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Albert, F. C. (2014). Applying Source Level Auto-Vectorization to Aparapi Java. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49022

Chicago Manual of Style (16th Edition):

Albert, Frank Curtis. “Applying Source Level Auto-Vectorization to Aparapi Java.” 2014. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/49022.

MLA Handbook (7th Edition):

Albert, Frank Curtis. “Applying Source Level Auto-Vectorization to Aparapi Java.” 2014. Web. 12 Apr 2021.

Vancouver:

Albert FC. Applying Source Level Auto-Vectorization to Aparapi Java. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/49022.

Council of Science Editors:

Albert FC. Applying Source Level Auto-Vectorization to Aparapi Java. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49022


Virginia Tech

8. Pahlavan Yali, Moein. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance… (more)

Subjects/Keywords: Embedded Systems; FPGA; Hardware Accelerator; Performance Model

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pahlavan Yali, M. (2015). FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51193

Chicago Manual of Style (16th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/51193.

MLA Handbook (7th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Web. 12 Apr 2021.

Vancouver:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/51193.

Council of Science Editors:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51193


Virginia Tech

9. Khoshnood, Sepideh. Constraint Solving for Diagnosing Concurrency Bugs.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 Programmers often have to spend a significant amount of time inspecting the software code and execution traces to identify the root cause of a software… (more)

Subjects/Keywords: Concurrency; Bug Localization; Bounded Model Checking; MAX-SAT

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khoshnood, S. (2015). Constraint Solving for Diagnosing Concurrency Bugs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52784

Chicago Manual of Style (16th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/52784.

MLA Handbook (7th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Web. 12 Apr 2021.

Vancouver:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/52784.

Council of Science Editors:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52784


Virginia Tech

10. Desai, Avinash R. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First,… (more)

Subjects/Keywords: Anti-Counterfeit; Anti-Tamper; Trojan Detection Integrated Circuits; Seal; Time-Stamp

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Desai, A. R. (2013). Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23756

Chicago Manual of Style (16th Edition):

Desai, Avinash R. “Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation.” 2013. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/23756.

MLA Handbook (7th Edition):

Desai, Avinash R. “Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation.” 2013. Web. 12 Apr 2021.

Vancouver:

Desai AR. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/23756.

Council of Science Editors:

Desai AR. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23756


Virginia Tech

11. Puri, Prateek. Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and… (more)

Subjects/Keywords: Design Verification; Particle Swarm Optimization; Static Analysis; Symbolic Backward Execution; Satisfiability Modulo Theory; Pattern Search Methods

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Puri, P. (2015). Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/55815

Chicago Manual of Style (16th Edition):

Puri, Prateek. “Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution.” 2015. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/55815.

MLA Handbook (7th Edition):

Puri, Prateek. “Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution.” 2015. Web. 12 Apr 2021.

Vancouver:

Puri P. Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/55815.

Council of Science Editors:

Puri P. Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/55815


Virginia Tech

12. Prabhu, Sarvesh P. Techniques for Enhancing Test and Diagnosis of Digital Circuits.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for… (more)

Subjects/Keywords: LBIST; LFSR-reseeding; Diagnostic Test Generation; Automated Test Pattern Generation (ATPG); Property Checking

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prabhu, S. P. (2015). Techniques for Enhancing Test and Diagnosis of Digital Circuits. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51181

Chicago Manual of Style (16th Edition):

Prabhu, Sarvesh P. “Techniques for Enhancing Test and Diagnosis of Digital Circuits.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/51181.

MLA Handbook (7th Edition):

Prabhu, Sarvesh P. “Techniques for Enhancing Test and Diagnosis of Digital Circuits.” 2015. Web. 12 Apr 2021.

Vancouver:

Prabhu SP. Techniques for Enhancing Test and Diagnosis of Digital Circuits. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/51181.

Council of Science Editors:

Prabhu SP. Techniques for Enhancing Test and Diagnosis of Digital Circuits. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51181


Virginia Tech

13. Eldib, Hassan Shoukry. Constraint Based Program Synthesis for Embedded Software.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 In the world that we live in today, we greatly rely on software in nearly every aspect of our lives. In many critical applications, such… (more)

Subjects/Keywords: Program Synthesis; Formal Verification; Embedded Software; Security; Cryptography; Side-Channel Attacks and Countermeasures

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Eldib, H. S. (2015). Constraint Based Program Synthesis for Embedded Software. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/55120

Chicago Manual of Style (16th Edition):

Eldib, Hassan Shoukry. “Constraint Based Program Synthesis for Embedded Software.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/55120.

MLA Handbook (7th Edition):

Eldib, Hassan Shoukry. “Constraint Based Program Synthesis for Embedded Software.” 2015. Web. 12 Apr 2021.

Vancouver:

Eldib HS. Constraint Based Program Synthesis for Embedded Software. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/55120.

Council of Science Editors:

Eldib HS. Constraint Based Program Synthesis for Embedded Software. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/55120


Virginia Tech

14. Nanjundappa, Mahesh. Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Formally-based design and implementation techniques for complex safety-critical embedded systems are required not only to handle the complexity, but also to provide correctness guarantees. Traditional… (more)

Subjects/Keywords: Model-based Design; MBD; Software Synthesis; Formal techniques; Code generation; Formal analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nanjundappa, M. (2015). Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/73483

Chicago Manual of Style (16th Edition):

Nanjundappa, Mahesh. “Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/73483.

MLA Handbook (7th Edition):

Nanjundappa, Mahesh. “Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models.” 2015. Web. 12 Apr 2021.

Vancouver:

Nanjundappa M. Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/73483.

Council of Science Editors:

Nanjundappa M. Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/73483


Virginia Tech

15. Zeng, Kevin. An Exploration of Circuit Similarity for Discovering and Predicting Reusable Hardware.

Degree: PhD, Computer Engineering, 2016, Virginia Tech

 A modular reuse-based design methodology has been one of the most important factors in improving hardware design productivity. Traditionally, reuse involves manually searching through repositories… (more)

Subjects/Keywords: Productivity; Reuse; Hardware; FPGA; Similarity Matching; Birthmarking

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zeng, K. (2016). An Exploration of Circuit Similarity for Discovering and Predicting Reusable Hardware. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/70863

Chicago Manual of Style (16th Edition):

Zeng, Kevin. “An Exploration of Circuit Similarity for Discovering and Predicting Reusable Hardware.” 2016. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/70863.

MLA Handbook (7th Edition):

Zeng, Kevin. “An Exploration of Circuit Similarity for Discovering and Predicting Reusable Hardware.” 2016. Web. 12 Apr 2021.

Vancouver:

Zeng K. An Exploration of Circuit Similarity for Discovering and Predicting Reusable Hardware. [Internet] [Doctoral dissertation]. Virginia Tech; 2016. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/70863.

Council of Science Editors:

Zeng K. An Exploration of Circuit Similarity for Discovering and Predicting Reusable Hardware. [Doctoral Dissertation]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/70863

16. Turcu, Alexandru. On Improving Distributed Transactional Memory through Nesting, Partitioning and Ordering.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Distributed Transactional Memory (DTM) is an emerging, alternative concurrency control model that aims to overcome the challenges of distributed-lock based synchronization. DTM employs transactions in… (more)

Subjects/Keywords: Distributed Transactional Memory; Distributed Systems; Nested Transactions; Automated Partitioning; Consensus

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Turcu, A. (2015). On Improving Distributed Transactional Memory through Nesting, Partitioning and Ordering. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51593

Chicago Manual of Style (16th Edition):

Turcu, Alexandru. “On Improving Distributed Transactional Memory through Nesting, Partitioning and Ordering.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/51593.

MLA Handbook (7th Edition):

Turcu, Alexandru. “On Improving Distributed Transactional Memory through Nesting, Partitioning and Ordering.” 2015. Web. 12 Apr 2021.

Vancouver:

Turcu A. On Improving Distributed Transactional Memory through Nesting, Partitioning and Ordering. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/51593.

Council of Science Editors:

Turcu A. On Improving Distributed Transactional Memory through Nesting, Partitioning and Ordering. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51593

17. Hirve, Sachin. On the Fault-tolerance and High Performance of Replicated Transactional Systems.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 With the recent technological developments in last few decades, there is a notable shift in the way business/consumer transactions are conducted. These transactions are usually… (more)

Subjects/Keywords: Distributed Transaction Memory; Fault-tolerance; Active Replication; Distributed Systems; On-line Transaction Processing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hirve, S. (2015). On the Fault-tolerance and High Performance of Replicated Transactional Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56668

Chicago Manual of Style (16th Edition):

Hirve, Sachin. “On the Fault-tolerance and High Performance of Replicated Transactional Systems.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/56668.

MLA Handbook (7th Edition):

Hirve, Sachin. “On the Fault-tolerance and High Performance of Replicated Transactional Systems.” 2015. Web. 12 Apr 2021.

Vancouver:

Hirve S. On the Fault-tolerance and High Performance of Replicated Transactional Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/56668.

Council of Science Editors:

Hirve S. On the Fault-tolerance and High Performance of Replicated Transactional Systems. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56668


Virginia Tech

18. Hassan, Ahmed Mohamed Elsayed. Designing, Modeling, and Optimizing Transactional Data Structures.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Transactional memory (TM) has emerged as a promising synchronization abstraction for multi-core architectures. Unlike traditional lock-based approaches, TM shifts the burden of implementing threads synchronization… (more)

Subjects/Keywords: Transactional Memory; STM; HTM; Transactional Boosting; Concurrent Data Structures; Optimistic Semantic Synchronization; Lazy List; Balanced Trees; Hybrid Transactions; Semantic Validation; Remote Transaction Commit; Modeling; Linearizability

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, A. M. E. (2015). Designing, Modeling, and Optimizing Transactional Data Structures. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56656

Chicago Manual of Style (16th Edition):

Hassan, Ahmed Mohamed Elsayed. “Designing, Modeling, and Optimizing Transactional Data Structures.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/56656.

MLA Handbook (7th Edition):

Hassan, Ahmed Mohamed Elsayed. “Designing, Modeling, and Optimizing Transactional Data Structures.” 2015. Web. 12 Apr 2021.

Vancouver:

Hassan AME. Designing, Modeling, and Optimizing Transactional Data Structures. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/56656.

Council of Science Editors:

Hassan AME. Designing, Modeling, and Optimizing Transactional Data Structures. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56656


Virginia Tech

19. Gent, Kelson Andrew. High Quality Test Generation at the Register Transfer Level.

Degree: PhD, Computer Engineering, 2016, Virginia Tech

 Integrated circuits, from general purpose microprocessors to application specific designs (ASICs), have become ubiquitous in modern technology. As our applications have become more complex, so… (more)

Subjects/Keywords: Hardware Test; ATPG; Functional Test; Swarm Intelligence; Verification; RTL ATPG

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gent, K. A. (2016). High Quality Test Generation at the Register Transfer Level. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/73544

Chicago Manual of Style (16th Edition):

Gent, Kelson Andrew. “High Quality Test Generation at the Register Transfer Level.” 2016. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/73544.

MLA Handbook (7th Edition):

Gent, Kelson Andrew. “High Quality Test Generation at the Register Transfer Level.” 2016. Web. 12 Apr 2021.

Vancouver:

Gent KA. High Quality Test Generation at the Register Transfer Level. [Internet] [Doctoral dissertation]. Virginia Tech; 2016. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/73544.

Council of Science Editors:

Gent KA. High Quality Test Generation at the Register Transfer Level. [Doctoral Dissertation]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/73544


Virginia Tech

20. Zhang, Lu. Runtime Verification and Debugging of Concurrent Software.

Degree: PhD, Computer Engineering, 2016, Virginia Tech

 Our reliance on software has been growing fast over the past decades as the pervasive use of computer and software penetrated not only our daily… (more)

Subjects/Keywords: Concurrency; Verification; Debugging; Program Repair; Quasi Linearizability; Concurrent Data Structure; Web Application; JavaScript

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, L. (2016). Runtime Verification and Debugging of Concurrent Software. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71882

Chicago Manual of Style (16th Edition):

Zhang, Lu. “Runtime Verification and Debugging of Concurrent Software.” 2016. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/71882.

MLA Handbook (7th Edition):

Zhang, Lu. “Runtime Verification and Debugging of Concurrent Software.” 2016. Web. 12 Apr 2021.

Vancouver:

Zhang L. Runtime Verification and Debugging of Concurrent Software. [Internet] [Doctoral dissertation]. Virginia Tech; 2016. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/71882.

Council of Science Editors:

Zhang L. Runtime Verification and Debugging of Concurrent Software. [Doctoral Dissertation]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71882


Virginia Tech

21. Kusano, Markus Jan Urban. Constraint-Based Thread-Modular Abstract Interpretation.

Degree: PhD, Computer Engineering, 2018, Virginia Tech

 In this dissertation, I present a set of novel constraint-based thread-modular abstract-interpretation techniques for static analysis of concurrent programs. Specifically, I integrate a lightweight constraint… (more)

Subjects/Keywords: abstract interpretation; concurrency; verification; static analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kusano, M. J. U. (2018). Constraint-Based Thread-Modular Abstract Interpretation. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84399

Chicago Manual of Style (16th Edition):

Kusano, Markus Jan Urban. “Constraint-Based Thread-Modular Abstract Interpretation.” 2018. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/84399.

MLA Handbook (7th Edition):

Kusano, Markus Jan Urban. “Constraint-Based Thread-Modular Abstract Interpretation.” 2018. Web. 12 Apr 2021.

Vancouver:

Kusano MJU. Constraint-Based Thread-Modular Abstract Interpretation. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/84399.

Council of Science Editors:

Kusano MJU. Constraint-Based Thread-Modular Abstract Interpretation. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84399


Virginia Tech

22. Elbayoumi, Mahmoud Atef Mahmoud Sayed. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity… (more)

Subjects/Keywords: Verification; logic synthesis; SAT; BDDs; Low power; timing aware

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Elbayoumi, M. A. M. S. (2015). Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51221

Chicago Manual of Style (16th Edition):

Elbayoumi, Mahmoud Atef Mahmoud Sayed. “Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.” 2015. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/51221.

MLA Handbook (7th Edition):

Elbayoumi, Mahmoud Atef Mahmoud Sayed. “Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.” 2015. Web. 12 Apr 2021.

Vancouver:

Elbayoumi MAMS. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/51221.

Council of Science Editors:

Elbayoumi MAMS. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51221


Virginia Tech

23. Wu, Meng. Analysis and Enforcement of Properties in Software Systems.

Degree: PhD, Computer Engineering, 2019, Virginia Tech

 It is important for everything around us to follow some rules to work correctly. That is the same for our software systems to follow the… (more)

Subjects/Keywords: Shield Synthesis; Program Analysis; Timing Side Channel; Cache Timing Leak; Speculative Execution; Abstract Interpretation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, M. (2019). Analysis and Enforcement of Properties in Software Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/90887

Chicago Manual of Style (16th Edition):

Wu, Meng. “Analysis and Enforcement of Properties in Software Systems.” 2019. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/90887.

MLA Handbook (7th Edition):

Wu, Meng. “Analysis and Enforcement of Properties in Software Systems.” 2019. Web. 12 Apr 2021.

Vancouver:

Wu M. Analysis and Enforcement of Properties in Software Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2019. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/90887.

Council of Science Editors:

Wu M. Analysis and Enforcement of Properties in Software Systems. [Doctoral Dissertation]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/90887


Virginia Tech

24. Farhady Ghalaty, Nahid. Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics.

Degree: PhD, Computer Engineering, 2016, Virginia Tech

 Recent research has demonstrated that there is no sharp distinction between passive attacks based on side-channel leakage and active attacks based on fault injection. Fault… (more)

Subjects/Keywords: Hardware Security; Physical Attacks; Cryptography

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Farhady Ghalaty, N. (2016). Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72280

Chicago Manual of Style (16th Edition):

Farhady Ghalaty, Nahid. “Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics.” 2016. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/72280.

MLA Handbook (7th Edition):

Farhady Ghalaty, Nahid. “Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics.” 2016. Web. 12 Apr 2021.

Vancouver:

Farhady Ghalaty N. Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics. [Internet] [Doctoral dissertation]. Virginia Tech; 2016. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/72280.

Council of Science Editors:

Farhady Ghalaty N. Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics. [Doctoral Dissertation]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72280


Virginia Tech

25. Kumar, Vireshwar. Transmitter Authentication in Dynamic Spectrum Sharing.

Degree: PhD, Computer Engineering, 2017, Virginia Tech

 Recent advances in spectrum access technologies, such as software-defined radios, have made dynamic spectrum sharing (DSS) a viable option for addressing the spectrum shortage problem.… (more)

Subjects/Keywords: Dynamic spectrum sharing; spectrum security and enforcement; privacy-preserving authentication; anonymous attestation; blind authentication.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, V. (2017). Transmitter Authentication in Dynamic Spectrum Sharing. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/74917

Chicago Manual of Style (16th Edition):

Kumar, Vireshwar. “Transmitter Authentication in Dynamic Spectrum Sharing.” 2017. Doctoral Dissertation, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/74917.

MLA Handbook (7th Edition):

Kumar, Vireshwar. “Transmitter Authentication in Dynamic Spectrum Sharing.” 2017. Web. 12 Apr 2021.

Vancouver:

Kumar V. Transmitter Authentication in Dynamic Spectrum Sharing. [Internet] [Doctoral dissertation]. Virginia Tech; 2017. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/74917.

Council of Science Editors:

Kumar V. Transmitter Authentication in Dynamic Spectrum Sharing. [Doctoral Dissertation]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/74917

26. Chattopadhyay, Arijit. Dynamic Invariant Generation for Concurrent Programs.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 We propose a fully automated and dynamic method for generating likely invariants from multithreaded programs and then leveraging these invariants to infer atomic regions and… (more)

Subjects/Keywords: Concurrency; Likely Invariant; Dynamic Invariant Generation; Partial Order Reduction; Error Diagnosis; Atomic Region

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chattopadhyay, A. (2014). Dynamic Invariant Generation for Concurrent Programs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49103

Chicago Manual of Style (16th Edition):

Chattopadhyay, Arijit. “Dynamic Invariant Generation for Concurrent Programs.” 2014. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/49103.

MLA Handbook (7th Edition):

Chattopadhyay, Arijit. “Dynamic Invariant Generation for Concurrent Programs.” 2014. Web. 12 Apr 2021.

Vancouver:

Chattopadhyay A. Dynamic Invariant Generation for Concurrent Programs. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/49103.

Council of Science Editors:

Chattopadhyay A. Dynamic Invariant Generation for Concurrent Programs. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49103

27. Dsouza, Michael Dylan. Fast Static Learning and Inductive Reasoning with Applications to ATPG Problems.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 Relations among various nodes in the circuit, as captured by static and inductive invariants, have shown to have a positive impact on a wide range… (more)

Subjects/Keywords: Static learning; inductive reasoning; multi-node invariants; logic implications; boolean constraint propagation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dsouza, M. D. (2015). Fast Static Learning and Inductive Reasoning with Applications to ATPG Problems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51591

Chicago Manual of Style (16th Edition):

Dsouza, Michael Dylan. “Fast Static Learning and Inductive Reasoning with Applications to ATPG Problems.” 2015. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/51591.

MLA Handbook (7th Edition):

Dsouza, Michael Dylan. “Fast Static Learning and Inductive Reasoning with Applications to ATPG Problems.” 2015. Web. 12 Apr 2021.

Vancouver:

Dsouza MD. Fast Static Learning and Inductive Reasoning with Applications to ATPG Problems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/51591.

Council of Science Editors:

Dsouza MD. Fast Static Learning and Inductive Reasoning with Applications to ATPG Problems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51591

28. Roy, Tonmoy. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.

Degree: MS, Computer Engineering, 2017, Virginia Tech

 In the first half of this thesis, a novel approach for k-induction bounded model checking using signal domain constraints and property partitioning for proving unreachability… (more)

Subjects/Keywords: RTL Verification; Reachability; k-Induction; Bounded Model Checking; Test Vector Compaction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roy, T. (2017). Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78801

Chicago Manual of Style (16th Edition):

Roy, Tonmoy. “Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.” 2017. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/78801.

MLA Handbook (7th Edition):

Roy, Tonmoy. “Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.” 2017. Web. 12 Apr 2021.

Vancouver:

Roy T. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/78801.

Council of Science Editors:

Roy T. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78801

29. Pandey, Utkarsh. Optimizing Distributed Transactions: Speculative Client Execution, Certified Serializability, and High Performance Run-Time.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 On-line services already form an important part of modern life with an immense potential for growth. Most of these services are supported by transactional systems,… (more)

Subjects/Keywords: Distributed systems; Transactions; Databases; Verification; Run-time; Concurrency; Paxos; Replication.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pandey, U. (2016). Optimizing Distributed Transactions: Speculative Client Execution, Certified Serializability, and High Performance Run-Time. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72867

Chicago Manual of Style (16th Edition):

Pandey, Utkarsh. “Optimizing Distributed Transactions: Speculative Client Execution, Certified Serializability, and High Performance Run-Time.” 2016. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/72867.

MLA Handbook (7th Edition):

Pandey, Utkarsh. “Optimizing Distributed Transactions: Speculative Client Execution, Certified Serializability, and High Performance Run-Time.” 2016. Web. 12 Apr 2021.

Vancouver:

Pandey U. Optimizing Distributed Transactions: Speculative Client Execution, Certified Serializability, and High Performance Run-Time. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/72867.

Council of Science Editors:

Pandey U. Optimizing Distributed Transactions: Speculative Client Execution, Certified Serializability, and High Performance Run-Time. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72867

30. Bagri, Sharad. Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 Considerable research has been directed towards efficient test stimuli generation for Register Transfer Level (RTL) circuits. However, stimuli generation frameworks are still not capable of… (more)

Subjects/Keywords: RTL circuits; Validation; Verification; Reachability; Unreachable; Branch Coverage; Signal Domain; Test Generation; Symbolic Execution

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bagri, S. (2015). Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51625

Chicago Manual of Style (16th Edition):

Bagri, Sharad. “Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution.” 2015. Masters Thesis, Virginia Tech. Accessed April 12, 2021. http://hdl.handle.net/10919/51625.

MLA Handbook (7th Edition):

Bagri, Sharad. “Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution.” 2015. Web. 12 Apr 2021.

Vancouver:

Bagri S. Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10919/51625.

Council of Science Editors:

Bagri S. Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51625

[1] [2]

.