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You searched for +publisher:"Virginia Tech" +contributor:("Shukla, Sandeep K."). Showing records 1 – 30 of 85 total matches.

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1. Chattopadhyay, Arijit. Dynamic Invariant Generation for Concurrent Programs.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 We propose a fully automated and dynamic method for generating likely invariants from multithreaded programs and then leveraging these invariants to infer atomic regions and… (more)

Subjects/Keywords: Concurrency; Likely Invariant; Dynamic Invariant Generation; Partial Order Reduction; Error Diagnosis; Atomic Region

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APA (6th Edition):

Chattopadhyay, A. (2014). Dynamic Invariant Generation for Concurrent Programs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49103

Chicago Manual of Style (16th Edition):

Chattopadhyay, Arijit. “Dynamic Invariant Generation for Concurrent Programs.” 2014. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/49103.

MLA Handbook (7th Edition):

Chattopadhyay, Arijit. “Dynamic Invariant Generation for Concurrent Programs.” 2014. Web. 26 Feb 2021.

Vancouver:

Chattopadhyay A. Dynamic Invariant Generation for Concurrent Programs. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/49103.

Council of Science Editors:

Chattopadhyay A. Dynamic Invariant Generation for Concurrent Programs. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49103


Virginia Tech

2. Bakshi, Dhrumeel. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in… (more)

Subjects/Keywords: Satisfiability Modulo Theories (SMT); LFSR Reseeding; Logic Built-In Self Test (LBIST); Integer Linear Programming (ILP); Test-point Insertion

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APA (6th Edition):

Bakshi, D. (2012). Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35474

Chicago Manual of Style (16th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/35474.

MLA Handbook (7th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Web. 26 Feb 2021.

Vancouver:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/35474.

Council of Science Editors:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/35474


Virginia Tech

3. Misra, Supratik Kumar. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test… (more)

Subjects/Keywords: Directed Acyclic Graph; Partial Scan Design; Pattern Debugger; Implication Graphs

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APA (6th Edition):

Misra, S. K. (2012). Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31153

Chicago Manual of Style (16th Edition):

Misra, Supratik Kumar. “Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.” 2012. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/31153.

MLA Handbook (7th Edition):

Misra, Supratik Kumar. “Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.” 2012. Web. 26 Feb 2021.

Vancouver:

Misra SK. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/31153.

Council of Science Editors:

Misra SK. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31153


Virginia Tech

4. Iyer, Srikrishna. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low… (more)

Subjects/Keywords: Communication Interface-Abstraction Architecture; automatic code-generation; TinyOS; nesC; GEZEL; hardware/software co-design; co-processor; wireless sensor nodes; CPU; FPGA

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APA (6th Edition):

Iyer, S. (2011). A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34625

Chicago Manual of Style (16th Edition):

Iyer, Srikrishna. “A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes.” 2011. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/34625.

MLA Handbook (7th Edition):

Iyer, Srikrishna. “A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes.” 2011. Web. 26 Feb 2021.

Vancouver:

Iyer S. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/34625.

Council of Science Editors:

Iyer S. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34625


Virginia Tech

5. Murali, Dilip Venkateswaran. Verification of Cyber Physical Systems.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Due to the increasing complexity of today\'s cyber-physical systems, defects become inevitable and harder to detect. The complexity of such software is generally huge, with… (more)

Subjects/Keywords: Invariants detection; Symbolic Execution; KLEE; Cloud9; VCC

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APA (6th Edition):

Murali, D. V. (2013). Verification of Cyber Physical Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23824

Chicago Manual of Style (16th Edition):

Murali, Dilip Venkateswaran. “Verification of Cyber Physical Systems.” 2013. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/23824.

MLA Handbook (7th Edition):

Murali, Dilip Venkateswaran. “Verification of Cyber Physical Systems.” 2013. Web. 26 Feb 2021.

Vancouver:

Murali DV. Verification of Cyber Physical Systems. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/23824.

Council of Science Editors:

Murali DV. Verification of Cyber Physical Systems. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23824


Virginia Tech

6. Zuo, Yongbo. Fair Comparison of ASIC Performance for SHA-3 Finalists.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems,… (more)

Subjects/Keywords: SHA; NIST; ASIC; Finalist; Hardware; Encryption; Hash; Cipher; Key

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APA (6th Edition):

Zuo, Y. (2012). Fair Comparison of ASIC Performance for SHA-3 Finalists. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33446

Chicago Manual of Style (16th Edition):

Zuo, Yongbo. “Fair Comparison of ASIC Performance for SHA-3 Finalists.” 2012. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/33446.

MLA Handbook (7th Edition):

Zuo, Yongbo. “Fair Comparison of ASIC Performance for SHA-3 Finalists.” 2012. Web. 26 Feb 2021.

Vancouver:

Zuo Y. Fair Comparison of ASIC Performance for SHA-3 Finalists. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/33446.

Council of Science Editors:

Zuo Y. Fair Comparison of ASIC Performance for SHA-3 Finalists. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/33446


Virginia Tech

7. Kracht, Matthew Wallace. Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 As embedded software and platforms become more complicated, many safety properties are left to simulation and testing. MRICDF is a formal polychronous language used to… (more)

Subjects/Keywords: Synchronous Languages; Real-Time Systems; Schedulability Analysis

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APA (6th Edition):

Kracht, M. W. (2014). Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46866

Chicago Manual of Style (16th Edition):

Kracht, Matthew Wallace. “Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages.” 2014. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/46866.

MLA Handbook (7th Edition):

Kracht, Matthew Wallace. “Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages.” 2014. Web. 26 Feb 2021.

Vancouver:

Kracht MW. Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/46866.

Council of Science Editors:

Kracht MW. Real-Time Embedded Software Modeling and Synthesis using Polychronous Data Flow Languages. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/46866


Virginia Tech

8. Messaoud, Safa. Translating Discrete Time SIMULINK to SIGNAL.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 As Cyber Physical Systems (CPS) are getting more complex and safety critical, Model Based Design (MBD), which consists of building formal models of a system… (more)

Subjects/Keywords: SIMULINK; SIGNAL; Embedded Software; Code Generation

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APA (6th Edition):

Messaoud, S. (2014). Translating Discrete Time SIMULINK to SIGNAL. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49299

Chicago Manual of Style (16th Edition):

Messaoud, Safa. “Translating Discrete Time SIMULINK to SIGNAL.” 2014. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/49299.

MLA Handbook (7th Edition):

Messaoud, Safa. “Translating Discrete Time SIMULINK to SIGNAL.” 2014. Web. 26 Feb 2021.

Vancouver:

Messaoud S. Translating Discrete Time SIMULINK to SIGNAL. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/49299.

Council of Science Editors:

Messaoud S. Translating Discrete Time SIMULINK to SIGNAL. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49299


Virginia Tech

9. Hu, Wei. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Verification, as opposed to Testing and Post-Silicon Validation, is a critical step for Integrated Circuits (IC) Design, answering the question â Are we designing the… (more)

Subjects/Keywords: Invariant filtering; Assume and Verify; Boolean Satisfiability(SAT); Sequential Equivalence Checking(SEC)

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APA (6th Edition):

Hu, W. (2011). Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31121

Chicago Manual of Style (16th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/31121.

MLA Handbook (7th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Web. 26 Feb 2021.

Vancouver:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/31121.

Council of Science Editors:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31121


Virginia Tech

10. Rafeei, Lalleh. Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage… (more)

Subjects/Keywords: subthreshold; approximation framework; power; timing; CMOS; VLSI; Ultra-Low-Voltage

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APA (6th Edition):

Rafeei, L. (2012). Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31678

Chicago Manual of Style (16th Edition):

Rafeei, Lalleh. “Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits.” 2012. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/31678.

MLA Handbook (7th Edition):

Rafeei, Lalleh. “Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits.” 2012. Web. 26 Feb 2021.

Vancouver:

Rafeei L. Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/31678.

Council of Science Editors:

Rafeei L. Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31678


Virginia Tech

11. Duong, Khanh Viet. On Enhancing Deterministic Sequential ATPG.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of… (more)

Subjects/Keywords: Automatic Test Pattern Generation; Logic Testing; Sequential Circuits

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APA (6th Edition):

Duong, K. V. (2011). On Enhancing Deterministic Sequential ATPG. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31283

Chicago Manual of Style (16th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/31283.

MLA Handbook (7th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Web. 26 Feb 2021.

Vancouver:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/31283.

Council of Science Editors:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31283


Virginia Tech

12. Sinha, Ambuj Sudhir. Design Techniques for Side-channel Resistant Embedded Software.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is… (more)

Subjects/Keywords: Bitslice Cryptography; Side Channel Attacks; Virtual Secure Circuit; Secure Embedded Systems; Side-channel Countermeasures

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APA (6th Edition):

Sinha, A. S. (2011). Design Techniques for Side-channel Resistant Embedded Software. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34465

Chicago Manual of Style (16th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/34465.

MLA Handbook (7th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Web. 26 Feb 2021.

Vancouver:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/34465.

Council of Science Editors:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34465


Virginia Tech

13. Prabhu, Sarvesh P. An Efficient 2-Phase Strategy to Achieve High Branch Coverage.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Symbolic execution-based test generation is gaining popularity for software test generation. The increasing complexity of the software program is posing new challenges in software execution-based… (more)

Subjects/Keywords: Branch Coverage; Conflict-driven Learning; Symbolic Execution; Software Testing

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APA (6th Edition):

Prabhu, S. P. (2012). An Efficient 2-Phase Strategy to Achieve High Branch Coverage. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/40931

Chicago Manual of Style (16th Edition):

Prabhu, Sarvesh P. “An Efficient 2-Phase Strategy to Achieve High Branch Coverage.” 2012. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/40931.

MLA Handbook (7th Edition):

Prabhu, Sarvesh P. “An Efficient 2-Phase Strategy to Achieve High Branch Coverage.” 2012. Web. 26 Feb 2021.

Vancouver:

Prabhu SP. An Efficient 2-Phase Strategy to Achieve High Branch Coverage. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/40931.

Council of Science Editors:

Prabhu SP. An Efficient 2-Phase Strategy to Achieve High Branch Coverage. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/40931


Virginia Tech

14. Munagani, Indira Priya Darshini. Mining Rare Features in Fingerprints using Core points and Triplet-based Features.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 A fingerprint matching algorithm with a novel set of matching parameters based on core points and triangular descriptors is proposed to discover rarity in fingerprints.… (more)

Subjects/Keywords: Fingerprints; Rare Features; Rarity; Latent; Core Points; Triplets; GPU

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APA (6th Edition):

Munagani, I. P. D. (2014). Mining Rare Features in Fingerprints using Core points and Triplet-based Features. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/24784

Chicago Manual of Style (16th Edition):

Munagani, Indira Priya Darshini. “Mining Rare Features in Fingerprints using Core points and Triplet-based Features.” 2014. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/24784.

MLA Handbook (7th Edition):

Munagani, Indira Priya Darshini. “Mining Rare Features in Fingerprints using Core points and Triplet-based Features.” 2014. Web. 26 Feb 2021.

Vancouver:

Munagani IPD. Mining Rare Features in Fingerprints using Core points and Triplet-based Features. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/24784.

Council of Science Editors:

Munagani IPD. Mining Rare Features in Fingerprints using Core points and Triplet-based Features. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/24784


Virginia Tech

15. Sowers, David Albert. Architecture for Issuing DoD Mobile Derived Credentials.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 With an increase in performance, dependency and ubiquitousness, the necessity for secure mobile device functionality is rapidly increasing. Authentication of an individual's identity is the… (more)

Subjects/Keywords: Derived Credentials; Public Key Infrastructure; Common Access Card; Department of Defense; x509; Mobile Phone

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APA (6th Edition):

Sowers, D. A. (2014). Architecture for Issuing DoD Mobile Derived Credentials. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/64351

Chicago Manual of Style (16th Edition):

Sowers, David Albert. “Architecture for Issuing DoD Mobile Derived Credentials.” 2014. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/64351.

MLA Handbook (7th Edition):

Sowers, David Albert. “Architecture for Issuing DoD Mobile Derived Credentials.” 2014. Web. 26 Feb 2021.

Vancouver:

Sowers DA. Architecture for Issuing DoD Mobile Derived Credentials. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/64351.

Council of Science Editors:

Sowers DA. Architecture for Issuing DoD Mobile Derived Credentials. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/64351


Virginia Tech

16. Huang, Sinan. Hardware Evaluation of SHA-3 Candidates.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Cryptographic hash functions are used extensively in information security, most notably in digital authentication and data integrity verification. Their performance is an important factor of… (more)

Subjects/Keywords: Cryptography; Security; SHA-3; Hardware Evaluation

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APA (6th Edition):

Huang, S. (2011). Hardware Evaluation of SHA-3 Candidates. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32932

Chicago Manual of Style (16th Edition):

Huang, Sinan. “Hardware Evaluation of SHA-3 Candidates.” 2011. Masters Thesis, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/32932.

MLA Handbook (7th Edition):

Huang, Sinan. “Hardware Evaluation of SHA-3 Candidates.” 2011. Web. 26 Feb 2021.

Vancouver:

Huang S. Hardware Evaluation of SHA-3 Candidates. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/32932.

Council of Science Editors:

Huang S. Hardware Evaluation of SHA-3 Candidates. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32932


Virginia Tech

17. Prabhu, Sarvesh P. Techniques for Enhancing Test and Diagnosis of Digital Circuits.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for… (more)

Subjects/Keywords: LBIST; LFSR-reseeding; Diagnostic Test Generation; Automated Test Pattern Generation (ATPG); Property Checking

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APA (6th Edition):

Prabhu, S. P. (2015). Techniques for Enhancing Test and Diagnosis of Digital Circuits. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51181

Chicago Manual of Style (16th Edition):

Prabhu, Sarvesh P. “Techniques for Enhancing Test and Diagnosis of Digital Circuits.” 2015. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/51181.

MLA Handbook (7th Edition):

Prabhu, Sarvesh P. “Techniques for Enhancing Test and Diagnosis of Digital Circuits.” 2015. Web. 26 Feb 2021.

Vancouver:

Prabhu SP. Techniques for Enhancing Test and Diagnosis of Digital Circuits. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/51181.

Council of Science Editors:

Prabhu SP. Techniques for Enhancing Test and Diagnosis of Digital Circuits. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51181


Virginia Tech

18. Garlapati, Shravan Kumar Reddy. Enabling Communication and Networking Technologies for Smart Grid.

Degree: PhD, Computer Engineering, 2014, Virginia Tech

 Transforming the aging electric grid to a smart grid is an active area of research in industry and the government. One of the main objectives… (more)

Subjects/Keywords: Distance Relays; Hidden Failures; Blackouts; Agents; DFS; IEEE C37.118; Multiple Facility Location; AMI; Spread Spectrum; Markov Chain Analysis; Backward Recursive Dynamic Programming

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APA (6th Edition):

Garlapati, S. K. R. (2014). Enabling Communication and Networking Technologies for Smart Grid. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56629

Chicago Manual of Style (16th Edition):

Garlapati, Shravan Kumar Reddy. “Enabling Communication and Networking Technologies for Smart Grid.” 2014. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/56629.

MLA Handbook (7th Edition):

Garlapati, Shravan Kumar Reddy. “Enabling Communication and Networking Technologies for Smart Grid.” 2014. Web. 26 Feb 2021.

Vancouver:

Garlapati SKR. Enabling Communication and Networking Technologies for Smart Grid. [Internet] [Doctoral dissertation]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/56629.

Council of Science Editors:

Garlapati SKR. Enabling Communication and Networking Technologies for Smart Grid. [Doctoral Dissertation]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/56629


Virginia Tech

19. Eldib, Hassan Shoukry. Constraint Based Program Synthesis for Embedded Software.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 In the world that we live in today, we greatly rely on software in nearly every aspect of our lives. In many critical applications, such… (more)

Subjects/Keywords: Program Synthesis; Formal Verification; Embedded Software; Security; Cryptography; Side-Channel Attacks and Countermeasures

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APA (6th Edition):

Eldib, H. S. (2015). Constraint Based Program Synthesis for Embedded Software. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/55120

Chicago Manual of Style (16th Edition):

Eldib, Hassan Shoukry. “Constraint Based Program Synthesis for Embedded Software.” 2015. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/55120.

MLA Handbook (7th Edition):

Eldib, Hassan Shoukry. “Constraint Based Program Synthesis for Embedded Software.” 2015. Web. 26 Feb 2021.

Vancouver:

Eldib HS. Constraint Based Program Synthesis for Embedded Software. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/55120.

Council of Science Editors:

Eldib HS. Constraint Based Program Synthesis for Embedded Software. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/55120


Virginia Tech

20. Nanjundappa, Mahesh. Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Formally-based design and implementation techniques for complex safety-critical embedded systems are required not only to handle the complexity, but also to provide correctness guarantees. Traditional… (more)

Subjects/Keywords: Model-based Design; MBD; Software Synthesis; Formal techniques; Code generation; Formal analysis

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APA (6th Edition):

Nanjundappa, M. (2015). Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/73483

Chicago Manual of Style (16th Edition):

Nanjundappa, Mahesh. “Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models.” 2015. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/73483.

MLA Handbook (7th Edition):

Nanjundappa, Mahesh. “Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models.” 2015. Web. 26 Feb 2021.

Vancouver:

Nanjundappa M. Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/73483.

Council of Science Editors:

Nanjundappa M. Formal Techniques for Design and Development of Safety Critical Embedded Systems from Polychronous Models. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/73483


Virginia Tech

21. Li, Min. Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 With the advances of very large scale integration (VLSI) technology, the feature size has been shrinking steadily together with the increase in the design complexity… (more)

Subjects/Keywords: general purpose computation on graphics processing; parallel algorithm; design validation; fault diagnosis; Fault simulation

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APA (6th Edition):

Li, M. (2012). Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29129

Chicago Manual of Style (16th Edition):

Li, Min. “Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units.” 2012. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/29129.

MLA Handbook (7th Edition):

Li, Min. “Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units.” 2012. Web. 26 Feb 2021.

Vancouver:

Li M. Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/29129.

Council of Science Editors:

Li M. Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/29129


Virginia Tech

22. La Pan, Matthew Jonathan. Security Issues for Modern Communications Systems: Fundamental Electronic Warfare Tactics for 4G Systems and Beyond.

Degree: PhD, Electrical Engineering, 2014, Virginia Tech

 In the modern era of wireless communications, radios are becoming increasingly more cognitive. As the complexity and robustness of friendly communications increases, so do the… (more)

Subjects/Keywords: Wireless Communications

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APA (6th Edition):

La Pan, M. J. (2014). Security Issues for Modern Communications Systems: Fundamental Electronic Warfare Tactics for 4G Systems and Beyond. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51042

Chicago Manual of Style (16th Edition):

La Pan, Matthew Jonathan. “Security Issues for Modern Communications Systems: Fundamental Electronic Warfare Tactics for 4G Systems and Beyond.” 2014. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/51042.

MLA Handbook (7th Edition):

La Pan, Matthew Jonathan. “Security Issues for Modern Communications Systems: Fundamental Electronic Warfare Tactics for 4G Systems and Beyond.” 2014. Web. 26 Feb 2021.

Vancouver:

La Pan MJ. Security Issues for Modern Communications Systems: Fundamental Electronic Warfare Tactics for 4G Systems and Beyond. [Internet] [Doctoral dissertation]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/51042.

Council of Science Editors:

La Pan MJ. Security Issues for Modern Communications Systems: Fundamental Electronic Warfare Tactics for 4G Systems and Beyond. [Doctoral Dissertation]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/51042


Virginia Tech

23. Wang, Ting. Wireless Network Physical Layer Security with Smart Antenna.

Degree: PhD, Computer Engineering, 2013, Virginia Tech

 Smart antenna technique has emerged as one of the leading technologies for enhancing the quality of service in wireless networks. Because of its ability to… (more)

Subjects/Keywords: Wireless Network Security; Localization; Location privacy; Anti-eavesdropping; Smart Antenna; Beamforming; Location Spoofing

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APA (6th Edition):

Wang, T. (2013). Wireless Network Physical Layer Security with Smart Antenna. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23243

Chicago Manual of Style (16th Edition):

Wang, Ting. “Wireless Network Physical Layer Security with Smart Antenna.” 2013. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/23243.

MLA Handbook (7th Edition):

Wang, Ting. “Wireless Network Physical Layer Security with Smart Antenna.” 2013. Web. 26 Feb 2021.

Vancouver:

Wang T. Wireless Network Physical Layer Security with Smart Antenna. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/23243.

Council of Science Editors:

Wang T. Wireless Network Physical Layer Security with Smart Antenna. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23243

24. Gao, Bo. Coexistence of Wireless Networks for Shared Spectrum Access.

Degree: PhD, Computer Engineering, 2014, Virginia Tech

 The radio frequency spectrum is not being efficiently utilized partly due to the current policy of allocating the frequency bands to specific services and users.… (more)

Subjects/Keywords: Opportunistic Spectrum Access; Cognitive Radio Networks; White Space Networks; Shared Spectrum Access; Spectrum Sharing; Network Coexistence

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APA (6th Edition):

Gao, B. (2014). Coexistence of Wireless Networks for Shared Spectrum Access. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50525

Chicago Manual of Style (16th Edition):

Gao, Bo. “Coexistence of Wireless Networks for Shared Spectrum Access.” 2014. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/50525.

MLA Handbook (7th Edition):

Gao, Bo. “Coexistence of Wireless Networks for Shared Spectrum Access.” 2014. Web. 26 Feb 2021.

Vancouver:

Gao B. Coexistence of Wireless Networks for Shared Spectrum Access. [Internet] [Doctoral dissertation]. Virginia Tech; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/50525.

Council of Science Editors:

Gao B. Coexistence of Wireless Networks for Shared Spectrum Access. [Doctoral Dissertation]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/50525


Virginia Tech

25. Lerner, Lee Wilmoth. Trustworthy Embedded Computing for Cyber-Physical Control.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 A cyber-physical controller (CPC) uses computing to control a physical process. Example CPCs can be found in self-driving automobiles, unmanned aerial vehicles, and other autonomous… (more)

Subjects/Keywords: Trustworthy Computing; Secure Computing; Autonomic Computing; Cybersecurity; Embedded Systems; Cyber-Physical Systems; Process Control Systems

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APA (6th Edition):

Lerner, L. W. (2015). Trustworthy Embedded Computing for Cyber-Physical Control. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51545

Chicago Manual of Style (16th Edition):

Lerner, Lee Wilmoth. “Trustworthy Embedded Computing for Cyber-Physical Control.” 2015. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/51545.

MLA Handbook (7th Edition):

Lerner, Lee Wilmoth. “Trustworthy Embedded Computing for Cyber-Physical Control.” 2015. Web. 26 Feb 2021.

Vancouver:

Lerner LW. Trustworthy Embedded Computing for Cyber-Physical Control. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/51545.

Council of Science Editors:

Lerner LW. Trustworthy Embedded Computing for Cyber-Physical Control. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51545


Virginia Tech

26. Lin, Hua. Communication Infrastructure for the Smart Grid: A Co-Simulation Based Study on Techniques to Improve the Power Transmission System Functions with Efficient Data Networks.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 The vision of the smart grid is predicated upon pervasive use of modern digital communication techniques in today's power system. As wide area measurements and… (more)

Subjects/Keywords: Co-Simulation; Wide Area Measurement System; Smart Grid; Remote Backup Relay; All-PMU State Estimation; Out-of-Step Protection

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APA (6th Edition):

Lin, H. (2012). Communication Infrastructure for the Smart Grid: A Co-Simulation Based Study on Techniques to Improve the Power Transmission System Functions with Efficient Data Networks. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29248

Chicago Manual of Style (16th Edition):

Lin, Hua. “Communication Infrastructure for the Smart Grid: A Co-Simulation Based Study on Techniques to Improve the Power Transmission System Functions with Efficient Data Networks.” 2012. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/29248.

MLA Handbook (7th Edition):

Lin, Hua. “Communication Infrastructure for the Smart Grid: A Co-Simulation Based Study on Techniques to Improve the Power Transmission System Functions with Efficient Data Networks.” 2012. Web. 26 Feb 2021.

Vancouver:

Lin H. Communication Infrastructure for the Smart Grid: A Co-Simulation Based Study on Techniques to Improve the Power Transmission System Functions with Efficient Data Networks. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/29248.

Council of Science Editors:

Lin H. Communication Infrastructure for the Smart Grid: A Co-Simulation Based Study on Techniques to Improve the Power Transmission System Functions with Efficient Data Networks. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/29248


Virginia Tech

27. Maiti, Abhranil. A Systematic Approach to Design an Efficient Physical Unclonable Function.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 A Physical Unclonable Function (PUF) has shown a lot of promise to solve many security issues due to its ability to generate a random yet… (more)

Subjects/Keywords: Process variation; Physical Unclonable Function; Security

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APA (6th Edition):

Maiti, A. (2012). A Systematic Approach to Design an Efficient Physical Unclonable Function. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51257

Chicago Manual of Style (16th Edition):

Maiti, Abhranil. “A Systematic Approach to Design an Efficient Physical Unclonable Function.” 2012. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/51257.

MLA Handbook (7th Edition):

Maiti, Abhranil. “A Systematic Approach to Design an Efficient Physical Unclonable Function.” 2012. Web. 26 Feb 2021.

Vancouver:

Maiti A. A Systematic Approach to Design an Efficient Physical Unclonable Function. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/51257.

Council of Science Editors:

Maiti A. A Systematic Approach to Design an Efficient Physical Unclonable Function. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/51257

28. Ganta, Dinesh. An Effort toward Building more Secure and Efficient Physical Unclonable Functions.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 Over the last decade, there has been a tremendous growth in the number of electronic devices and applications. One of the very important aspects to… (more)

Subjects/Keywords: Physical Unclonable Functions; Security; Fingerprinting; Integrated Circuits; Identifiers

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APA (6th Edition):

Ganta, D. (2015). An Effort toward Building more Secure and Efficient Physical Unclonable Functions. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51217

Chicago Manual of Style (16th Edition):

Ganta, Dinesh. “An Effort toward Building more Secure and Efficient Physical Unclonable Functions.” 2015. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/51217.

MLA Handbook (7th Edition):

Ganta, Dinesh. “An Effort toward Building more Secure and Efficient Physical Unclonable Functions.” 2015. Web. 26 Feb 2021.

Vancouver:

Ganta D. An Effort toward Building more Secure and Efficient Physical Unclonable Functions. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/51217.

Council of Science Editors:

Ganta D. An Effort toward Building more Secure and Efficient Physical Unclonable Functions. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51217

29. Anderson, Matthew Eric. APECS: A Polychrony based End-to-End Embedded System Design and Code Synthesis.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 The development of high integrity embedded systems remains an arduous and error-prone task, despite the efforts by researchers in inventing tools and techniques for design… (more)

Subjects/Keywords: AADL; CPS; Model-based code synthesis; correct-by-construction code synthesis; Polychrony; code generators; OSATE; Ocarina

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APA (6th Edition):

Anderson, M. E. (2015). APECS: A Polychrony based End-to-End Embedded System Design and Code Synthesis. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52369

Chicago Manual of Style (16th Edition):

Anderson, Matthew Eric. “APECS: A Polychrony based End-to-End Embedded System Design and Code Synthesis.” 2015. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/52369.

MLA Handbook (7th Edition):

Anderson, Matthew Eric. “APECS: A Polychrony based End-to-End Embedded System Design and Code Synthesis.” 2015. Web. 26 Feb 2021.

Vancouver:

Anderson ME. APECS: A Polychrony based End-to-End Embedded System Design and Code Synthesis. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/52369.

Council of Science Editors:

Anderson ME. APECS: A Polychrony based End-to-End Embedded System Design and Code Synthesis. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52369


Virginia Tech

30. Short, Nathaniel Jackson. Robust Feature Extraction and Temporal Analysis for Partial Fingerprint Identification.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 Identification of an individual from discriminating features of the friction ridge surface is one of the oldest and most commonly used biometric techniques. Methods for… (more)

Subjects/Keywords: Bayesian Estimation; Fingerprint; Biometrics; Extended Features; Temporal Analysis

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APA (6th Edition):

Short, N. J. (2012). Robust Feature Extraction and Temporal Analysis for Partial Fingerprint Identification. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29033

Chicago Manual of Style (16th Edition):

Short, Nathaniel Jackson. “Robust Feature Extraction and Temporal Analysis for Partial Fingerprint Identification.” 2012. Doctoral Dissertation, Virginia Tech. Accessed February 26, 2021. http://hdl.handle.net/10919/29033.

MLA Handbook (7th Edition):

Short, Nathaniel Jackson. “Robust Feature Extraction and Temporal Analysis for Partial Fingerprint Identification.” 2012. Web. 26 Feb 2021.

Vancouver:

Short NJ. Robust Feature Extraction and Temporal Analysis for Partial Fingerprint Identification. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/10919/29033.

Council of Science Editors:

Short NJ. Robust Feature Extraction and Temporal Analysis for Partial Fingerprint Identification. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/29033

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